| Arnd Bergmann | 48be9ac | 2013-02-28 18:19:16 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-dove/board-dt.c |
| 3 | * |
| 4 | * Marvell Dove 88AP510 System On Chip FDT Board |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/clk-provider.h> |
| 13 | #include <linux/clk/mvebu.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/of_platform.h> |
| 16 | #include <linux/platform_data/usb-ehci-orion.h> |
| 17 | #include <asm/hardware/cache-tauros2.h> |
| 18 | #include <asm/mach/arch.h> |
| 19 | #include <mach/pm.h> |
| 20 | #include <plat/common.h> |
| 21 | #include <plat/irq.h> |
| 22 | #include "common.h" |
| 23 | |
| 24 | /* |
| 25 | * There are still devices that doesn't even know about DT, |
| 26 | * get clock gates here and add a clock lookup. |
| 27 | */ |
| 28 | static void __init dove_legacy_clk_init(void) |
| 29 | { |
| 30 | struct device_node *np = of_find_compatible_node(NULL, NULL, |
| 31 | "marvell,dove-gating-clock"); |
| 32 | struct of_phandle_args clkspec; |
| 33 | |
| 34 | clkspec.np = np; |
| 35 | clkspec.args_count = 1; |
| 36 | |
| 37 | clkspec.args[0] = CLOCK_GATING_BIT_USB0; |
| 38 | orion_clkdev_add(NULL, "orion-ehci.0", |
| 39 | of_clk_get_from_provider(&clkspec)); |
| 40 | |
| 41 | clkspec.args[0] = CLOCK_GATING_BIT_USB1; |
| 42 | orion_clkdev_add(NULL, "orion-ehci.1", |
| 43 | of_clk_get_from_provider(&clkspec)); |
| 44 | |
| 45 | clkspec.args[0] = CLOCK_GATING_BIT_GBE; |
| 46 | orion_clkdev_add(NULL, "mv643xx_eth_port.0", |
| 47 | of_clk_get_from_provider(&clkspec)); |
| 48 | |
| 49 | clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; |
| 50 | orion_clkdev_add("0", "pcie", |
| 51 | of_clk_get_from_provider(&clkspec)); |
| 52 | |
| 53 | clkspec.args[0] = CLOCK_GATING_BIT_PCIE1; |
| 54 | orion_clkdev_add("1", "pcie", |
| 55 | of_clk_get_from_provider(&clkspec)); |
| 56 | } |
| 57 | |
| 58 | static void __init dove_of_clk_init(void) |
| 59 | { |
| 60 | mvebu_clocks_init(); |
| 61 | dove_legacy_clk_init(); |
| 62 | } |
| 63 | |
| 64 | static struct mv643xx_eth_platform_data dove_dt_ge00_data = { |
| 65 | .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, |
| 66 | }; |
| 67 | |
| 68 | static void __init dove_dt_init(void) |
| 69 | { |
| 70 | pr_info("Dove 88AP510 SoC\n"); |
| 71 | |
| 72 | #ifdef CONFIG_CACHE_TAUROS2 |
| 73 | tauros2_init(0); |
| 74 | #endif |
| 75 | dove_setup_cpu_mbus(); |
| 76 | |
| 77 | /* Setup root of clk tree */ |
| 78 | dove_of_clk_init(); |
| 79 | |
| 80 | /* Internal devices not ported to DT yet */ |
| 81 | dove_ge00_init(&dove_dt_ge00_data); |
| 82 | dove_ehci0_init(); |
| 83 | dove_ehci1_init(); |
| 84 | dove_pcie_init(1, 1); |
| 85 | |
| 86 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
| 87 | } |
| 88 | |
| 89 | static const char * const dove_dt_board_compat[] = { |
| 90 | "marvell,dove", |
| 91 | NULL |
| 92 | }; |
| 93 | |
| 94 | DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") |
| 95 | .map_io = dove_map_io, |
| 96 | .init_early = dove_init_early, |
| 97 | .init_irq = orion_dt_init_irq, |
| 98 | .init_time = dove_timer_init, |
| 99 | .init_machine = dove_dt_init, |
| 100 | .restart = dove_restart, |
| 101 | .dt_compat = dove_dt_board_compat, |
| 102 | MACHINE_END |