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gerrit-public.fairphone.software / kernel / msm-5.4 / 490e687eb8b274b5d942e1cf61fb01392b86ecce / . / drivers / pinctrl / sh-pfc / pfc-r8a77965.c
blob: 3583e20185346b128fa2f28c47496ec8ec6f0251 [file] [log] [blame]
Jacopo Mondi490e6872018-02-20 16:12:07 +0100[diff] [blame^]1// SPDX-License-Identifier: GPL-2.
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Copyright (C) 2016 Renesas Electronics Corp.
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <linux/kernel.h>
16
17#include "core.h"
18#include "sh_pfc.h"
19
20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
23
24#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37/*
38 * F_() : just information
39 * FM() : macro for FN_xxx / xxx_MARK
40 */
41
42/* GPSR0 */
43#define GPSR0_15 F_(D15, IP7_11_8)
44#define GPSR0_14 F_(D14, IP7_7_4)
45#define GPSR0_13 F_(D13, IP7_3_0)
46#define GPSR0_12 F_(D12, IP6_31_28)
47#define GPSR0_11 F_(D11, IP6_27_24)
48#define GPSR0_10 F_(D10, IP6_23_20)
49#define GPSR0_9 F_(D9, IP6_19_16)
50#define GPSR0_8 F_(D8, IP6_15_12)
51#define GPSR0_7 F_(D7, IP6_11_8)
52#define GPSR0_6 F_(D6, IP6_7_4)
53#define GPSR0_5 F_(D5, IP6_3_0)
54#define GPSR0_4 F_(D4, IP5_31_28)
55#define GPSR0_3 F_(D3, IP5_27_24)
56#define GPSR0_2 F_(D2, IP5_23_20)
57#define GPSR0_1 F_(D1, IP5_19_16)
58#define GPSR0_0 F_(D0, IP5_15_12)
59
60/* GPSR1 */
61#define GPSR1_28 FM(CLKOUT)
62#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63#define GPSR1_26 F_(WE1_N, IP5_7_4)
64#define GPSR1_25 F_(WE0_N, IP5_3_0)
65#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66#define GPSR1_23 F_(RD_N, IP4_27_24)
67#define GPSR1_22 F_(BS_N, IP4_23_20)
68#define GPSR1_21 F_(CS1_N, IP4_19_16)
69#define GPSR1_20 F_(CS0_N, IP4_15_12)
70#define GPSR1_19 F_(A19, IP4_11_8)
71#define GPSR1_18 F_(A18, IP4_7_4)
72#define GPSR1_17 F_(A17, IP4_3_0)
73#define GPSR1_16 F_(A16, IP3_31_28)
74#define GPSR1_15 F_(A15, IP3_27_24)
75#define GPSR1_14 F_(A14, IP3_23_20)
76#define GPSR1_13 F_(A13, IP3_19_16)
77#define GPSR1_12 F_(A12, IP3_15_12)
78#define GPSR1_11 F_(A11, IP3_11_8)
79#define GPSR1_10 F_(A10, IP3_7_4)
80#define GPSR1_9 F_(A9, IP3_3_0)
81#define GPSR1_8 F_(A8, IP2_31_28)
82#define GPSR1_7 F_(A7, IP2_27_24)
83#define GPSR1_6 F_(A6, IP2_23_20)
84#define GPSR1_5 F_(A5, IP2_19_16)
85#define GPSR1_4 F_(A4, IP2_15_12)
86#define GPSR1_3 F_(A3, IP2_11_8)
87#define GPSR1_2 F_(A2, IP2_7_4)
88#define GPSR1_1 F_(A1, IP2_3_0)
89#define GPSR1_0 F_(A0, IP1_31_28)
90
91/* GPSR2 */
92#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98#define GPSR2_8 F_(PWM2_A, IP1_27_24)
99#define GPSR2_7 F_(PWM1_A, IP1_23_20)
100#define GPSR2_6 F_(PWM0, IP1_19_16)
101#define GPSR2_5 F_(IRQ5, IP1_15_12)
102#define GPSR2_4 F_(IRQ4, IP1_11_8)
103#define GPSR2_3 F_(IRQ3, IP1_7_4)
104#define GPSR2_2 F_(IRQ2, IP1_3_0)
105#define GPSR2_1 F_(IRQ1, IP0_31_28)
106#define GPSR2_0 F_(IRQ0, IP0_27_24)
107
108/* GPSR3 */
109#define GPSR3_15 F_(SD1_WP, IP11_23_20)
110#define GPSR3_14 F_(SD1_CD, IP11_19_16)
111#define GPSR3_13 F_(SD0_WP, IP11_15_12)
112#define GPSR3_12 F_(SD0_CD, IP11_11_8)
113#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125
126/* GPSR4 */
127#define GPSR4_17 F_(SD3_DS, IP11_7_4)
128#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138#define GPSR4_6 F_(SD2_DS, IP9_27_24)
139#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145
146/* GPSR5 */
147#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150#define GPSR5_22 FM(MSIOF0_RXD)
151#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152#define GPSR5_20 FM(MSIOF0_TXD)
153#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155#define GPSR5_17 FM(MSIOF0_SCK)
156#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158#define GPSR5_14 F_(HTX0, IP13_19_16)
159#define GPSR5_13 F_(HRX0, IP13_15_12)
160#define GPSR5_12 F_(HSCK0, IP13_11_8)
161#define GPSR5_11 F_(RX2_A, IP13_7_4)
162#define GPSR5_10 F_(TX2_A, IP13_3_0)
163#define GPSR5_9 F_(SCK2, IP12_31_28)
164#define GPSR5_8 F_(RTS1_N, IP12_27_24)
165#define GPSR5_7 F_(CTS1_N, IP12_23_20)
166#define GPSR5_6 F_(TX1_A, IP12_19_16)
167#define GPSR5_5 F_(RX1_A, IP12_15_12)
168#define GPSR5_4 F_(RTS0_N, IP12_11_8)
169#define GPSR5_3 F_(CTS0_N, IP12_7_4)
170#define GPSR5_2 F_(TX0, IP12_3_0)
171#define GPSR5_1 F_(RX0, IP11_31_28)
172#define GPSR5_0 F_(SCK0, IP11_27_24)
173
174/* GPSR6 */
175#define GPSR6_31 F_(GP6_31, IP18_7_4)
176#define GPSR6_30 F_(GP6_30, IP18_3_0)
177#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193#define GPSR6_13 FM(SSI_SDATA5)
194#define GPSR6_12 FM(SSI_WS5)
195#define GPSR6_11 FM(SSI_SCK5)
196#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207
208/* GPSR7 */
209#define GPSR7_3 FM(GP7_03)
210#define GPSR7_2 FM(HDMI0_CEC)
211#define GPSR7_1 FM(AVS2)
212#define GPSR7_0 FM(AVS1)
213
214
215/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
216#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243
244/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
245#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340
341/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
342#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369
370#define PINMUX_GPSR \
371\
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404
405#define PINMUX_IPSR \
406\
407FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415\
416FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424\
425FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433\
434FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442\
443FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
451
452/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
453#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
471
472/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
495
496/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510
511#define PINMUX_MOD_SELS \
512\
513MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516MOD_SEL0_28_27 MOD_SEL2_28_27 \
517MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519MOD_SEL0_23 MOD_SEL1_23_22_21 \
520MOD_SEL0_22 MOD_SEL2_22 \
521MOD_SEL0_21 MOD_SEL2_21 \
522MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530MOD_SEL0_12 MOD_SEL1_12 \
531MOD_SEL0_11 MOD_SEL1_11 \
532MOD_SEL0_10 MOD_SEL1_10 \
533MOD_SEL0_9_8 MOD_SEL1_9 \
534MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536MOD_SEL0_5 MOD_SEL1_5 \
537MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
542
543/*
544 * These pins are not able to be muxed but have other properties
545 * that can be set, such as drive-strength or pull-up/pull-down enable.
546 */
547#define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559
560enum {
561 PINMUX_RESERVED = 0,
562
563 PINMUX_DATA_BEGIN,
564 GP_ALL(DATA),
565 PINMUX_DATA_END,
566
567#define F_(x, y)
568#define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
570 GP_ALL(FN),
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575#undef F_
576#undef FM
577
578#define F_(x, y)
579#define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586#undef F_
587#undef FM
588};
589
590static const u16 pinmux_data[] = {
591 PINMUX_DATA_GP_ALL(),
592
593 PINMUX_SINGLE(AVS1),
594 PINMUX_SINGLE(AVS2),
595 PINMUX_SINGLE(CLKOUT),
596 PINMUX_SINGLE(GP7_03),
597 PINMUX_SINGLE(HDMI0_CEC),
598 PINMUX_SINGLE(MSIOF0_RXD),
599 PINMUX_SINGLE(MSIOF0_SCK),
600 PINMUX_SINGLE(MSIOF0_TXD),
601 PINMUX_SINGLE(SSI_SCK5),
602 PINMUX_SINGLE(SSI_SDATA5),
603 PINMUX_SINGLE(SSI_WS5),
604
605 /* IPSR0 */
606 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
607 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
608
609 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
610 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
611 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
612
613 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
614 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
615 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
616
617 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
618 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
619 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
621
622 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
625
626 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
629
630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
632 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
633 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
637
638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
645
646 /* IPSR1 */
647 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
648 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
649 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
650 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
653
654 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
655 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
660
661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
664 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
667
668 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
669 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697 /* IPSR2 */
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758 /* IPSR3 */
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812 /* IPSR4 */
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858 /* IPSR5 */
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908 /* IPSR6 */
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960 /* IPSR7 */
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002 /* IPSR8 */
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051 /* IPSR9 */
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1073
1074 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1075 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1076
1077 /* IPSR10 */
1078 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1079 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1080
1081 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1082 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1083
1084 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1085 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1086
1087 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1088 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1089
1090 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1091 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1092
1093 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1094 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1095 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1096
1097 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1098 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1099 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1100
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1102 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1103 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1104
1105 /* IPSR11 */
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1107 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1108 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1109
1110 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1111 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1112
1113 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1123 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1128 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1137 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1138 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1140
1141 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1142 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1143 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1146
1147 /* IPSR12 */
1148 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1149 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1153
1154 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1155 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1160 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1161 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1162
1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1170 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1171
1172 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1183
1184 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1185 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1190 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1191
1192 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1193 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1195 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1198 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1199
1200 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1201 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1206 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1207
1208 /* IPSR13 */
1209 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1214 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1215
1216 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1222
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1231
1232 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1233 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1234 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1235 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1238
1239 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1240 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1248 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1249 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1250 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1253 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1254
1255 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1258 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1259 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1261 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1262
1263 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1264 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1265 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1266 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1267
1268 /* IPSR14 */
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1271 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1276 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1277
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1288 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1292 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1297 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1298 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1301 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1304 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1307 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1308
1309 /* IPSR15 */
1310 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1311
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1314
1315 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1316 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1320 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1323
1324 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1325 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1333 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1339
1340 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1341 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1347
1348 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1355
1356 /* IPSR16 */
1357 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1362
1363 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1364 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1365 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1366
1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1374
1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1391
1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1399
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408
1409 /* IPSR17 */
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1418
1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1426
1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1443
1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1453
1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1475
1476 /* IPSR18 */
1477 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1486
1487 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496
1497 /* I2C */
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
1512};
1513
1514/*
1515 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521#define PIN_NONE U16_MAX
1522
1523static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1525
1526 /*
1527 * Pins not associated with a GPIO port.
1528 *
1529 * The pin positions are different between different r8a77965
1530 * packages, all that is needed for the pfc driver is a unique
1531 * number for each pin. To this end use the pin layout from
1532 * R-Car M3SiP to calculate a unique number for each pin.
1533 */
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576};
1577
1578static const struct sh_pfc_pin_group pinmux_groups[] = {
1579};
1580
1581static const struct sh_pfc_function pinmux_functions[] = {
1582};
1583
1584static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1585#define F_(x, y) FN_##y
1586#define FM(x) FN_##x
1587 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
1588 0, 0,
1589 0, 0,
1590 0, 0,
1591 0, 0,
1592 0, 0,
1593 0, 0,
1594 0, 0,
1595 0, 0,
1596 0, 0,
1597 0, 0,
1598 0, 0,
1599 0, 0,
1600 0, 0,
1601 0, 0,
1602 0, 0,
1603 0, 0,
1604 GP_0_15_FN, GPSR0_15,
1605 GP_0_14_FN, GPSR0_14,
1606 GP_0_13_FN, GPSR0_13,
1607 GP_0_12_FN, GPSR0_12,
1608 GP_0_11_FN, GPSR0_11,
1609 GP_0_10_FN, GPSR0_10,
1610 GP_0_9_FN, GPSR0_9,
1611 GP_0_8_FN, GPSR0_8,
1612 GP_0_7_FN, GPSR0_7,
1613 GP_0_6_FN, GPSR0_6,
1614 GP_0_5_FN, GPSR0_5,
1615 GP_0_4_FN, GPSR0_4,
1616 GP_0_3_FN, GPSR0_3,
1617 GP_0_2_FN, GPSR0_2,
1618 GP_0_1_FN, GPSR0_1,
1619 GP_0_0_FN, GPSR0_0, }
1620 },
1621 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
1622 0, 0,
1623 0, 0,
1624 0, 0,
1625 GP_1_28_FN, GPSR1_28,
1626 GP_1_27_FN, GPSR1_27,
1627 GP_1_26_FN, GPSR1_26,
1628 GP_1_25_FN, GPSR1_25,
1629 GP_1_24_FN, GPSR1_24,
1630 GP_1_23_FN, GPSR1_23,
1631 GP_1_22_FN, GPSR1_22,
1632 GP_1_21_FN, GPSR1_21,
1633 GP_1_20_FN, GPSR1_20,
1634 GP_1_19_FN, GPSR1_19,
1635 GP_1_18_FN, GPSR1_18,
1636 GP_1_17_FN, GPSR1_17,
1637 GP_1_16_FN, GPSR1_16,
1638 GP_1_15_FN, GPSR1_15,
1639 GP_1_14_FN, GPSR1_14,
1640 GP_1_13_FN, GPSR1_13,
1641 GP_1_12_FN, GPSR1_12,
1642 GP_1_11_FN, GPSR1_11,
1643 GP_1_10_FN, GPSR1_10,
1644 GP_1_9_FN, GPSR1_9,
1645 GP_1_8_FN, GPSR1_8,
1646 GP_1_7_FN, GPSR1_7,
1647 GP_1_6_FN, GPSR1_6,
1648 GP_1_5_FN, GPSR1_5,
1649 GP_1_4_FN, GPSR1_4,
1650 GP_1_3_FN, GPSR1_3,
1651 GP_1_2_FN, GPSR1_2,
1652 GP_1_1_FN, GPSR1_1,
1653 GP_1_0_FN, GPSR1_0, }
1654 },
1655 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
1656 0, 0,
1657 0, 0,
1658 0, 0,
1659 0, 0,
1660 0, 0,
1661 0, 0,
1662 0, 0,
1663 0, 0,
1664 0, 0,
1665 0, 0,
1666 0, 0,
1667 0, 0,
1668 0, 0,
1669 0, 0,
1670 0, 0,
1671 0, 0,
1672 0, 0,
1673 GP_2_14_FN, GPSR2_14,
1674 GP_2_13_FN, GPSR2_13,
1675 GP_2_12_FN, GPSR2_12,
1676 GP_2_11_FN, GPSR2_11,
1677 GP_2_10_FN, GPSR2_10,
1678 GP_2_9_FN, GPSR2_9,
1679 GP_2_8_FN, GPSR2_8,
1680 GP_2_7_FN, GPSR2_7,
1681 GP_2_6_FN, GPSR2_6,
1682 GP_2_5_FN, GPSR2_5,
1683 GP_2_4_FN, GPSR2_4,
1684 GP_2_3_FN, GPSR2_3,
1685 GP_2_2_FN, GPSR2_2,
1686 GP_2_1_FN, GPSR2_1,
1687 GP_2_0_FN, GPSR2_0, }
1688 },
1689 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
1690 0, 0,
1691 0, 0,
1692 0, 0,
1693 0, 0,
1694 0, 0,
1695 0, 0,
1696 0, 0,
1697 0, 0,
1698 0, 0,
1699 0, 0,
1700 0, 0,
1701 0, 0,
1702 0, 0,
1703 0, 0,
1704 0, 0,
1705 0, 0,
1706 GP_3_15_FN, GPSR3_15,
1707 GP_3_14_FN, GPSR3_14,
1708 GP_3_13_FN, GPSR3_13,
1709 GP_3_12_FN, GPSR3_12,
1710 GP_3_11_FN, GPSR3_11,
1711 GP_3_10_FN, GPSR3_10,
1712 GP_3_9_FN, GPSR3_9,
1713 GP_3_8_FN, GPSR3_8,
1714 GP_3_7_FN, GPSR3_7,
1715 GP_3_6_FN, GPSR3_6,
1716 GP_3_5_FN, GPSR3_5,
1717 GP_3_4_FN, GPSR3_4,
1718 GP_3_3_FN, GPSR3_3,
1719 GP_3_2_FN, GPSR3_2,
1720 GP_3_1_FN, GPSR3_1,
1721 GP_3_0_FN, GPSR3_0, }
1722 },
1723 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
1724 0, 0,
1725 0, 0,
1726 0, 0,
1727 0, 0,
1728 0, 0,
1729 0, 0,
1730 0, 0,
1731 0, 0,
1732 0, 0,
1733 0, 0,
1734 0, 0,
1735 0, 0,
1736 0, 0,
1737 0, 0,
1738 GP_4_17_FN, GPSR4_17,
1739 GP_4_16_FN, GPSR4_16,
1740 GP_4_15_FN, GPSR4_15,
1741 GP_4_14_FN, GPSR4_14,
1742 GP_4_13_FN, GPSR4_13,
1743 GP_4_12_FN, GPSR4_12,
1744 GP_4_11_FN, GPSR4_11,
1745 GP_4_10_FN, GPSR4_10,
1746 GP_4_9_FN, GPSR4_9,
1747 GP_4_8_FN, GPSR4_8,
1748 GP_4_7_FN, GPSR4_7,
1749 GP_4_6_FN, GPSR4_6,
1750 GP_4_5_FN, GPSR4_5,
1751 GP_4_4_FN, GPSR4_4,
1752 GP_4_3_FN, GPSR4_3,
1753 GP_4_2_FN, GPSR4_2,
1754 GP_4_1_FN, GPSR4_1,
1755 GP_4_0_FN, GPSR4_0, }
1756 },
1757 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
1758 0, 0,
1759 0, 0,
1760 0, 0,
1761 0, 0,
1762 0, 0,
1763 0, 0,
1764 GP_5_25_FN, GPSR5_25,
1765 GP_5_24_FN, GPSR5_24,
1766 GP_5_23_FN, GPSR5_23,
1767 GP_5_22_FN, GPSR5_22,
1768 GP_5_21_FN, GPSR5_21,
1769 GP_5_20_FN, GPSR5_20,
1770 GP_5_19_FN, GPSR5_19,
1771 GP_5_18_FN, GPSR5_18,
1772 GP_5_17_FN, GPSR5_17,
1773 GP_5_16_FN, GPSR5_16,
1774 GP_5_15_FN, GPSR5_15,
1775 GP_5_14_FN, GPSR5_14,
1776 GP_5_13_FN, GPSR5_13,
1777 GP_5_12_FN, GPSR5_12,
1778 GP_5_11_FN, GPSR5_11,
1779 GP_5_10_FN, GPSR5_10,
1780 GP_5_9_FN, GPSR5_9,
1781 GP_5_8_FN, GPSR5_8,
1782 GP_5_7_FN, GPSR5_7,
1783 GP_5_6_FN, GPSR5_6,
1784 GP_5_5_FN, GPSR5_5,
1785 GP_5_4_FN, GPSR5_4,
1786 GP_5_3_FN, GPSR5_3,
1787 GP_5_2_FN, GPSR5_2,
1788 GP_5_1_FN, GPSR5_1,
1789 GP_5_0_FN, GPSR5_0, }
1790 },
1791 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
1792 GP_6_31_FN, GPSR6_31,
1793 GP_6_30_FN, GPSR6_30,
1794 GP_6_29_FN, GPSR6_29,
1795 GP_6_28_FN, GPSR6_28,
1796 GP_6_27_FN, GPSR6_27,
1797 GP_6_26_FN, GPSR6_26,
1798 GP_6_25_FN, GPSR6_25,
1799 GP_6_24_FN, GPSR6_24,
1800 GP_6_23_FN, GPSR6_23,
1801 GP_6_22_FN, GPSR6_22,
1802 GP_6_21_FN, GPSR6_21,
1803 GP_6_20_FN, GPSR6_20,
1804 GP_6_19_FN, GPSR6_19,
1805 GP_6_18_FN, GPSR6_18,
1806 GP_6_17_FN, GPSR6_17,
1807 GP_6_16_FN, GPSR6_16,
1808 GP_6_15_FN, GPSR6_15,
1809 GP_6_14_FN, GPSR6_14,
1810 GP_6_13_FN, GPSR6_13,
1811 GP_6_12_FN, GPSR6_12,
1812 GP_6_11_FN, GPSR6_11,
1813 GP_6_10_FN, GPSR6_10,
1814 GP_6_9_FN, GPSR6_9,
1815 GP_6_8_FN, GPSR6_8,
1816 GP_6_7_FN, GPSR6_7,
1817 GP_6_6_FN, GPSR6_6,
1818 GP_6_5_FN, GPSR6_5,
1819 GP_6_4_FN, GPSR6_4,
1820 GP_6_3_FN, GPSR6_3,
1821 GP_6_2_FN, GPSR6_2,
1822 GP_6_1_FN, GPSR6_1,
1823 GP_6_0_FN, GPSR6_0, }
1824 },
1825 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
1826 0, 0,
1827 0, 0,
1828 0, 0,
1829 0, 0,
1830 0, 0,
1831 0, 0,
1832 0, 0,
1833 0, 0,
1834 0, 0,
1835 0, 0,
1836 0, 0,
1837 0, 0,
1838 0, 0,
1839 0, 0,
1840 0, 0,
1841 0, 0,
1842 0, 0,
1843 0, 0,
1844 0, 0,
1845 0, 0,
1846 0, 0,
1847 0, 0,
1848 0, 0,
1849 0, 0,
1850 0, 0,
1851 0, 0,
1852 0, 0,
1853 0, 0,
1854 GP_7_3_FN, GPSR7_3,
1855 GP_7_2_FN, GPSR7_2,
1856 GP_7_1_FN, GPSR7_1,
1857 GP_7_0_FN, GPSR7_0, }
1858 },
1859#undef F_
1860#undef FM
1861
1862#define F_(x, y) x,
1863#define FM(x) FN_##x,
1864 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
1865 IP0_31_28
1866 IP0_27_24
1867 IP0_23_20
1868 IP0_19_16
1869 IP0_15_12
1870 IP0_11_8
1871 IP0_7_4
1872 IP0_3_0 }
1873 },
1874 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
1875 IP1_31_28
1876 IP1_27_24
1877 IP1_23_20
1878 IP1_19_16
1879 IP1_15_12
1880 IP1_11_8
1881 IP1_7_4
1882 IP1_3_0 }
1883 },
1884 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
1885 IP2_31_28
1886 IP2_27_24
1887 IP2_23_20
1888 IP2_19_16
1889 IP2_15_12
1890 IP2_11_8
1891 IP2_7_4
1892 IP2_3_0 }
1893 },
1894 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
1895 IP3_31_28
1896 IP3_27_24
1897 IP3_23_20
1898 IP3_19_16
1899 IP3_15_12
1900 IP3_11_8
1901 IP3_7_4
1902 IP3_3_0 }
1903 },
1904 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
1905 IP4_31_28
1906 IP4_27_24
1907 IP4_23_20
1908 IP4_19_16
1909 IP4_15_12
1910 IP4_11_8
1911 IP4_7_4
1912 IP4_3_0 }
1913 },
1914 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
1915 IP5_31_28
1916 IP5_27_24
1917 IP5_23_20
1918 IP5_19_16
1919 IP5_15_12
1920 IP5_11_8
1921 IP5_7_4
1922 IP5_3_0 }
1923 },
1924 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
1925 IP6_31_28
1926 IP6_27_24
1927 IP6_23_20
1928 IP6_19_16
1929 IP6_15_12
1930 IP6_11_8
1931 IP6_7_4
1932 IP6_3_0 }
1933 },
1934 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
1935 IP7_31_28
1936 IP7_27_24
1937 IP7_23_20
1938 IP7_19_16
1939 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1940 IP7_11_8
1941 IP7_7_4
1942 IP7_3_0 }
1943 },
1944 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
1945 IP8_31_28
1946 IP8_27_24
1947 IP8_23_20
1948 IP8_19_16
1949 IP8_15_12
1950 IP8_11_8
1951 IP8_7_4
1952 IP8_3_0 }
1953 },
1954 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
1955 IP9_31_28
1956 IP9_27_24
1957 IP9_23_20
1958 IP9_19_16
1959 IP9_15_12
1960 IP9_11_8
1961 IP9_7_4
1962 IP9_3_0 }
1963 },
1964 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
1965 IP10_31_28
1966 IP10_27_24
1967 IP10_23_20
1968 IP10_19_16
1969 IP10_15_12
1970 IP10_11_8
1971 IP10_7_4
1972 IP10_3_0 }
1973 },
1974 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
1975 IP11_31_28
1976 IP11_27_24
1977 IP11_23_20
1978 IP11_19_16
1979 IP11_15_12
1980 IP11_11_8
1981 IP11_7_4
1982 IP11_3_0 }
1983 },
1984 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
1985 IP12_31_28
1986 IP12_27_24
1987 IP12_23_20
1988 IP12_19_16
1989 IP12_15_12
1990 IP12_11_8
1991 IP12_7_4
1992 IP12_3_0 }
1993 },
1994 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
1995 IP13_31_28
1996 IP13_27_24
1997 IP13_23_20
1998 IP13_19_16
1999 IP13_15_12
2000 IP13_11_8
2001 IP13_7_4
2002 IP13_3_0 }
2003 },
2004 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2005 IP14_31_28
2006 IP14_27_24
2007 IP14_23_20
2008 IP14_19_16
2009 IP14_15_12
2010 IP14_11_8
2011 IP14_7_4
2012 IP14_3_0 }
2013 },
2014 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2015 IP15_31_28
2016 IP15_27_24
2017 IP15_23_20
2018 IP15_19_16
2019 IP15_15_12
2020 IP15_11_8
2021 IP15_7_4
2022 IP15_3_0 }
2023 },
2024 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2025 IP16_31_28
2026 IP16_27_24
2027 IP16_23_20
2028 IP16_19_16
2029 IP16_15_12
2030 IP16_11_8
2031 IP16_7_4
2032 IP16_3_0 }
2033 },
2034 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
2035 IP17_31_28
2036 IP17_27_24
2037 IP17_23_20
2038 IP17_19_16
2039 IP17_15_12
2040 IP17_11_8
2041 IP17_7_4
2042 IP17_3_0 }
2043 },
2044 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2045 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2046 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2047 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2048 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2049 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2050 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2051 IP18_7_4
2052 IP18_3_0 }
2053 },
2054#undef F_
2055#undef FM
2056
2057#define F_(x, y) x,
2058#define FM(x) FN_##x,
2059 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2060 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2061 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2062 MOD_SEL0_31_30_29
2063 MOD_SEL0_28_27
2064 MOD_SEL0_26_25_24
2065 MOD_SEL0_23
2066 MOD_SEL0_22
2067 MOD_SEL0_21
2068 MOD_SEL0_20
2069 MOD_SEL0_19
2070 MOD_SEL0_18_17
2071 MOD_SEL0_16
2072 0, 0, /* RESERVED 15 */
2073 MOD_SEL0_14_13
2074 MOD_SEL0_12
2075 MOD_SEL0_11
2076 MOD_SEL0_10
2077 MOD_SEL0_9_8
2078 MOD_SEL0_7_6
2079 MOD_SEL0_5
2080 MOD_SEL0_4_3
2081 /* RESERVED 2, 1, 0 */
2082 0, 0, 0, 0, 0, 0, 0, 0 }
2083 },
2084 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2085 2, 3, 1, 2, 3, 1, 1, 2, 1,
2086 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2087 MOD_SEL1_31_30
2088 MOD_SEL1_29_28_27
2089 MOD_SEL1_26
2090 MOD_SEL1_25_24
2091 MOD_SEL1_23_22_21
2092 MOD_SEL1_20
2093 MOD_SEL1_19
2094 MOD_SEL1_18_17
2095 MOD_SEL1_16
2096 MOD_SEL1_15_14
2097 MOD_SEL1_13
2098 MOD_SEL1_12
2099 MOD_SEL1_11
2100 MOD_SEL1_10
2101 MOD_SEL1_9
2102 0, 0, 0, 0, /* RESERVED 8, 7 */
2103 MOD_SEL1_6
2104 MOD_SEL1_5
2105 MOD_SEL1_4
2106 MOD_SEL1_3
2107 MOD_SEL1_2
2108 MOD_SEL1_1
2109 MOD_SEL1_0 }
2110 },
2111 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
2112 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2113 4, 4, 4, 3, 1) {
2114 MOD_SEL2_31
2115 MOD_SEL2_30
2116 MOD_SEL2_29
2117 MOD_SEL2_28_27
2118 MOD_SEL2_26
2119 MOD_SEL2_25_24_23
2120 MOD_SEL2_22
2121 MOD_SEL2_21
2122 MOD_SEL2_20
2123 MOD_SEL2_19
2124 MOD_SEL2_18
2125 MOD_SEL2_17
2126 /* RESERVED 16 */
2127 0, 0,
2128 /* RESERVED 15, 14, 13, 12 */
2129 0, 0, 0, 0, 0, 0, 0, 0,
2130 0, 0, 0, 0, 0, 0, 0, 0,
2131 /* RESERVED 11, 10, 9, 8 */
2132 0, 0, 0, 0, 0, 0, 0, 0,
2133 0, 0, 0, 0, 0, 0, 0, 0,
2134 /* RESERVED 7, 6, 5, 4 */
2135 0, 0, 0, 0, 0, 0, 0, 0,
2136 0, 0, 0, 0, 0, 0, 0, 0,
2137 /* RESERVED 3, 2, 1 */
2138 0, 0, 0, 0, 0, 0, 0, 0,
2139 MOD_SEL2_0 }
2140 },
2141 { },
2142};
2143
2144static const struct pinmux_drive_reg pinmux_drive_regs[] = {
2145 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
2146 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
2147 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
2148 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
2149 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
2150 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
2151 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
2152 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
2153 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
2154 } },
2155 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
2156 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
2157 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
2158 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
2159 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
2160 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
2161 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
2162 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
2163 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
2164 } },
2165 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
2166 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
2167 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
2168 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
2169 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
2170 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
2171 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
2172 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
2173 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
2174 } },
2175 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
2176 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
2177 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
2178 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
2179 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
2180 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
2181 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
2182 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
2183 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
2184 } },
2185 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
2186 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
2187 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
2188 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
2189 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
2190 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
2191 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
2192 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
2193 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
2194 } },
2195 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
2196 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
2197 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
2198 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
2199 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
2200 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
2201 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
2202 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
2203 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
2204 } },
2205 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
2206 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
2207 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
2208 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
2209 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
2210 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
2211 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
2212 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
2213 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
2214 } },
2215 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
2216 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
2217 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
2218 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
2219 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
2220 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
2221 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
2222 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
2223 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
2224 } },
2225 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
2226 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
2227 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
2228 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
2229 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
2230 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
2231 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
2232 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
2233 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
2234 } },
2235 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
2236 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
2237 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
2238 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
2239 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
2240 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
2241 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
2242 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
2243 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
2244 } },
2245 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
2246 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
2247 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
2248 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
2249 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
2250 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
2251 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
2252 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
2253 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
2254 } },
2255 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
2256 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
2257 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
2258 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
2259 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
2260 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
2261 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
2262 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
2263 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
2264 } },
2265 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
2266 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
2267 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
2268 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
2269 } },
2270 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
2271 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
2272 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
2273 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
2274 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
2275 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
2276 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
2277 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
2278 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
2279 } },
2280 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
2281 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
2282 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
2283 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
2284 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
2285 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
2286 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
2287 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
2288 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
2289 } },
2290 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
2291 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
2292 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
2293 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
2294 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
2295 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
2296 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
2297 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
2298 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
2299 } },
2300 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
2301 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
2302 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
2303 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
2304 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
2305 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
2306 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
2307 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
2308 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
2309 } },
2310 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
2311 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
2312 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
2313 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
2314 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
2315 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
2316 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
2317 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
2318 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
2319 } },
2320 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
2321 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
2322 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
2323 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
2324 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
2325 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
2326 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
2327 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
2328 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
2329 } },
2330 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
2331 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
2332 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
2333 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
2334 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
2335 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
2336 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
2337 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
2338 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
2339 } },
2340 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
2341 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
2342 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
2343 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
2344 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
2345 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
2346 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
2347 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
2348 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
2349 } },
2350 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
2351 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
2352 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
2353 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
2354 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
2355 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
2356 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
2357 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
2358 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
2359 } },
2360 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
2361 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
2362 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
2363 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
2364 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
2365 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
2366 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
2367 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
2368 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
2369 } },
2370 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
2371 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
2372 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
2373 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
2374 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
2375 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
2376 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
2377 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
2378 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
2379 } },
2380 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
2381 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
2382 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
2383 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
2384 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
2385 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
2386 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
2387 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
2388 } },
2389 { },
2390};
2391
2392enum ioctrl_regs {
2393 POCCTRL,
2394};
2395
2396static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2397 [POCCTRL] = { 0xe6060380, },
2398 { /* sentinel */ },
2399};
2400
2401static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2402{
2403 int bit = -EINVAL;
2404
2405 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
2406
2407 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
2408 bit = pin & 0x1f;
2409
2410 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
2411 bit = (pin & 0x1f) + 12;
2412
2413 return bit;
2414}
2415
2416static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2417 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2418 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
2419 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
2420 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
2421 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
2422 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
2423 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
2424 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
2425 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
2426 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
2427 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
2428 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
2429 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
2430 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
2431 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
2432 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
2433 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
2434 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
2435 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
2436 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
2437 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
2438 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
2439 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
2440 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
2441 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
2442 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
2443 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
2444 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
2445 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
2446 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
2447 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
2448 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
2449 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
2450 } },
2451 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2452 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
2453 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
2454 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
2455 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
2456 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
2457 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
2458 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
2459 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
2460 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
2461 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
2462 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
2463 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
2464 [12] = RCAR_GP_PIN(1, 0), /* A0 */
2465 [13] = RCAR_GP_PIN(1, 1), /* A1 */
2466 [14] = RCAR_GP_PIN(1, 2), /* A2 */
2467 [15] = RCAR_GP_PIN(1, 3), /* A3 */
2468 [16] = RCAR_GP_PIN(1, 4), /* A4 */
2469 [17] = RCAR_GP_PIN(1, 5), /* A5 */
2470 [18] = RCAR_GP_PIN(1, 6), /* A6 */
2471 [19] = RCAR_GP_PIN(1, 7), /* A7 */
2472 [20] = RCAR_GP_PIN(1, 8), /* A8 */
2473 [21] = RCAR_GP_PIN(1, 9), /* A9 */
2474 [22] = RCAR_GP_PIN(1, 10), /* A10 */
2475 [23] = RCAR_GP_PIN(1, 11), /* A11 */
2476 [24] = RCAR_GP_PIN(1, 12), /* A12 */
2477 [25] = RCAR_GP_PIN(1, 13), /* A13 */
2478 [26] = RCAR_GP_PIN(1, 14), /* A14 */
2479 [27] = RCAR_GP_PIN(1, 15), /* A15 */
2480 [28] = RCAR_GP_PIN(1, 16), /* A16 */
2481 [29] = RCAR_GP_PIN(1, 17), /* A17 */
2482 [30] = RCAR_GP_PIN(1, 18), /* A18 */
2483 [31] = RCAR_GP_PIN(1, 19), /* A19 */
2484 } },
2485 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2486 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
2487 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
2488 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
2489 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
2490 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
2491 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
2492 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
2493 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
2494 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
2495 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
2496 [10] = RCAR_GP_PIN(0, 0), /* D0 */
2497 [11] = RCAR_GP_PIN(0, 1), /* D1 */
2498 [12] = RCAR_GP_PIN(0, 2), /* D2 */
2499 [13] = RCAR_GP_PIN(0, 3), /* D3 */
2500 [14] = RCAR_GP_PIN(0, 4), /* D4 */
2501 [15] = RCAR_GP_PIN(0, 5), /* D5 */
2502 [16] = RCAR_GP_PIN(0, 6), /* D6 */
2503 [17] = RCAR_GP_PIN(0, 7), /* D7 */
2504 [18] = RCAR_GP_PIN(0, 8), /* D8 */
2505 [19] = RCAR_GP_PIN(0, 9), /* D9 */
2506 [20] = RCAR_GP_PIN(0, 10), /* D10 */
2507 [21] = RCAR_GP_PIN(0, 11), /* D11 */
2508 [22] = RCAR_GP_PIN(0, 12), /* D12 */
2509 [23] = RCAR_GP_PIN(0, 13), /* D13 */
2510 [24] = RCAR_GP_PIN(0, 14), /* D14 */
2511 [25] = RCAR_GP_PIN(0, 15), /* D15 */
2512 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
2513 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
2514 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
2515 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
2516 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
2517 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
2518 } },
2519 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2520 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
2521 [ 1] = PIN_NONE,
2522 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
2523 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
2524 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
2525 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
2526 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
2527 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
2528 [ 8] = PIN_NONE,
2529 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
2530 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
2531 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
2532 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
2533 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
2534 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
2535 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
2536 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
2537 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
2538 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
2539 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
2540 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
2541 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
2542 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
2543 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
2544 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
2545 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
2546 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
2547 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
2548 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
2549 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
2550 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
2551 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
2552 } },
2553 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
2554 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
2555 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
2556 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
2557 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
2558 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
2559 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
2560 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
2561 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
2562 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
2563 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
2564 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
2565 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
2566 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
2567 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
2568 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
2569 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
2570 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
2571 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
2572 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
2573 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
2574 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
2575 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
2576 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
2577 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
2578 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
2579 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
2580 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
2581 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
2582 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
2583 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
2584 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
2585 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
2586 } },
2587 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
2588 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
2589 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
2590 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
2591 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
2592 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
2593 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
2594 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
2595 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
2596 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
2597 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
2598 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
2599 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
2600 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
2601 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
2602 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
2603 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
2604 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
2605 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
2606 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
2607 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
2608 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
2609 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
2610 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
2611 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
2612 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
2613 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
2614 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
2615 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
2616 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
2617 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
2618 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
2619 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
2620 } },
2621 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
2622 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
2623 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
2624 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
2625 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
2626 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
2627 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
2628 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
2629 [ 7] = PIN_NONE,
2630 [ 8] = PIN_NONE,
2631 [ 9] = PIN_NONE,
2632 [10] = PIN_NONE,
2633 [11] = PIN_NONE,
2634 [12] = PIN_NONE,
2635 [13] = PIN_NONE,
2636 [14] = PIN_NONE,
2637 [15] = PIN_NONE,
2638 [16] = PIN_NONE,
2639 [17] = PIN_NONE,
2640 [18] = PIN_NONE,
2641 [19] = PIN_NONE,
2642 [20] = PIN_NONE,
2643 [21] = PIN_NONE,
2644 [22] = PIN_NONE,
2645 [23] = PIN_NONE,
2646 [24] = PIN_NONE,
2647 [25] = PIN_NONE,
2648 [26] = PIN_NONE,
2649 [27] = PIN_NONE,
2650 [28] = PIN_NONE,
2651 [29] = PIN_NONE,
2652 [30] = PIN_NONE,
2653 [31] = PIN_NONE,
2654 } },
2655 { /* sentinel */ },
2656};
2657
2658static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
2659 unsigned int pin)
2660{
2661 const struct pinmux_bias_reg *reg;
2662 unsigned int bit;
2663
2664 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
2665 if (!reg)
2666 return PIN_CONFIG_BIAS_DISABLE;
2667
2668 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
2669 return PIN_CONFIG_BIAS_DISABLE;
2670 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
2671 return PIN_CONFIG_BIAS_PULL_UP;
2672 else
2673 return PIN_CONFIG_BIAS_PULL_DOWN;
2674}
2675
2676static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2677 unsigned int bias)
2678{
2679 const struct pinmux_bias_reg *reg;
2680 u32 enable, updown;
2681 unsigned int bit;
2682
2683 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
2684 if (!reg)
2685 return;
2686
2687 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
2688 if (bias != PIN_CONFIG_BIAS_DISABLE)
2689 enable |= BIT(bit);
2690
2691 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
2692 if (bias == PIN_CONFIG_BIAS_PULL_UP)
2693 updown |= BIT(bit);
2694
2695 sh_pfc_write(pfc, reg->pud, updown);
2696 sh_pfc_write(pfc, reg->puen, enable);
2697}
2698
2699static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
2700 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
2701 .get_bias = r8a77965_pinmux_get_bias,
2702 .set_bias = r8a77965_pinmux_set_bias,
2703};
2704
2705const struct sh_pfc_soc_info r8a77965_pinmux_info = {
2706 .name = "r8a77965_pfc",
2707 .ops = &r8a77965_pinmux_ops,
2708 .unlock_reg = 0xe6060000, /* PMMR */
2709
2710 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2711
2712 .pins = pinmux_pins,
2713 .nr_pins = ARRAY_SIZE(pinmux_pins),
2714 .groups = pinmux_groups,
2715 .nr_groups = ARRAY_SIZE(pinmux_groups),
2716 .functions = pinmux_functions,
2717 .nr_functions = ARRAY_SIZE(pinmux_functions),
2718
2719 .cfg_regs = pinmux_config_regs,
2720 .drive_regs = pinmux_drive_regs,
2721 .bias_regs = pinmux_bias_regs,
2722 .ioctrl_regs = pinmux_ioctrl_regs,
2723
2724 .pinmux_data = pinmux_data,
2725 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2726};