blob: 8402efef10ad30e712a729aa929ecd52dad5f819 [file] [log] [blame]
qipeng.zha0a8b8352015-06-27 00:32:15 +08001#ifndef _ASM_X86_INTEL_PMC_IPC_H_
2#define _ASM_X86_INTEL_PMC_IPC_H_
3
4/* Commands */
5#define PMC_IPC_PMIC_ACCESS 0xFF
6#define PMC_IPC_PMIC_ACCESS_READ 0x0
7#define PMC_IPC_PMIC_ACCESS_WRITE 0x1
8#define PMC_IPC_USB_PWR_CTRL 0xF0
9#define PMC_IPC_PMIC_BLACKLIST_SEL 0xEF
10#define PMC_IPC_PHY_CONFIG 0xEE
11#define PMC_IPC_NORTHPEAK_CTRL 0xED
12#define PMC_IPC_PM_DEBUG 0xEC
13#define PMC_IPC_PMC_TELEMTRY 0xEB
14#define PMC_IPC_PMC_FW_MSG_CTRL 0xEA
15
16/* IPC return code */
17#define IPC_ERR_NONE 0
18#define IPC_ERR_CMD_NOT_SUPPORTED 1
19#define IPC_ERR_CMD_NOT_SERVICED 2
20#define IPC_ERR_UNABLE_TO_SERVICE 3
21#define IPC_ERR_CMD_INVALID 4
22#define IPC_ERR_CMD_FAILED 5
23#define IPC_ERR_EMSECURITY 6
24#define IPC_ERR_UNSIGNEDKERNEL 7
25
Kuppuswamy Sathyanarayanan49670202017-04-09 15:00:17 -070026/* GCR reg offsets from gcr base*/
27#define PMC_GCR_PMC_CFG_REG 0x08
28
qipeng.zha0a8b8352015-06-27 00:32:15 +080029#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
30
qipeng.zha0a8b8352015-06-27 00:32:15 +080031int intel_pmc_ipc_simple_command(int cmd, int sub);
qipeng.zha0a8b8352015-06-27 00:32:15 +080032int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
33 u32 *out, u32 outlen, u32 dptr, u32 sptr);
qipeng.zha0a8b8352015-06-27 00:32:15 +080034int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
35 u32 *out, u32 outlen);
Shanth Murthy76062b42017-02-13 04:02:52 -080036int intel_pmc_s0ix_counter_read(u64 *data);
Kuppuswamy Sathyanarayanan49670202017-04-09 15:00:17 -070037int intel_pmc_gcr_read(u32 offset, u32 *data);
38int intel_pmc_gcr_write(u32 offset, u32 data);
39int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val);
qipeng.zha0a8b8352015-06-27 00:32:15 +080040
41#else
42
43static inline int intel_pmc_ipc_simple_command(int cmd, int sub)
44{
45 return -EINVAL;
46}
47
48static inline int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen,
49 u32 *out, u32 outlen, u32 dptr, u32 sptr)
50{
51 return -EINVAL;
52}
53
54static inline int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
55 u32 *out, u32 outlen)
56{
57 return -EINVAL;
58}
59
Shanth Murthy76062b42017-02-13 04:02:52 -080060static inline int intel_pmc_s0ix_counter_read(u64 *data)
61{
62 return -EINVAL;
63}
64
Kuppuswamy Sathyanarayanan49670202017-04-09 15:00:17 -070065static inline int intel_pmc_gcr_read(u32 offset, u32 *data)
66{
67 return -EINVAL;
68}
69
70static inline int intel_pmc_gcr_write(u32 offset, u32 data)
71{
72 return -EINVAL;
73}
74
75static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
76{
77 return -EINVAL;
78}
79
qipeng.zha0a8b8352015-06-27 00:32:15 +080080#endif /*CONFIG_INTEL_PMC_IPC*/
81
82#endif