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gerrit-public.fairphone.software / kernel / msm-5.4 / 16a15a30f8a09af6ce2dc4fd6eec9b454c1fe488 / . / arch / powerpc / boot / dts / mpc8272ads.dts
blob: 1934b800278e06d42d47d21ce94fd2490483f2f6 [file] [log] [blame]
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]1/*
2 * MPC8272 ADS Device Tree Source
3 *
4 * Copyright 2005 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8272ADS";
14 compatible = "MPC8260ADS";
15 #address-cells = <1>;
16 #size-cells = <1>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]17
18 cpus {
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]19 #address-cells = <1>;
20 #size-cells = <0>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]21
22 PowerPC,8272@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <4000>; // L1, 16K
28 i-cache-size = <4000>; // L1, 16K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 32-bit;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]33 };
34 };
35
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]36 pci_pic: interrupt-controller@f8200000 {
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]37 #address-cells = <0>;
38 #interrupt-cells = <2>;
39 interrupt-controller;
40 reg = <f8200000 f8200004>;
41 built-in;
42 device_type = "pci-pic";
43 };
44 memory {
45 device_type = "memory";
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]46 reg = <00000000 4000000 f4500000 00000020>;
47 };
48
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]49 chosen {
50 name = "chosen";
51 linux,platform = <0>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]52 interrupt-controller = <&Cpm_pic>;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]53 };
54
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]55 soc8272@f0000000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 #interrupt-cells = <2>;
59 device_type = "soc";
Vitaly Bordug54278282007-01-31 02:09:00 +0300[diff] [blame]60 ranges = <00000000 f0000000 00053000>;
61 reg = <f0000000 10000>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]62
63 mdio@0 {
64 device_type = "mdio";
65 compatible = "fs_enet";
66 reg = <0 0>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]67 #address-cells = <1>;
68 #size-cells = <0>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]69 phy0:ethernet-phy@0 {
70 interrupt-parent = <&Cpm_pic>;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]71 interrupts = <17 4>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]72 reg = <0>;
73 bitbang = [ 12 12 13 02 02 01 ];
74 device_type = "ethernet-phy";
75 };
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]76 phy1:ethernet-phy@1 {
77 interrupt-parent = <&Cpm_pic>;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]78 interrupts = <17 4>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]79 bitbang = [ 12 12 13 02 02 01 ];
80 reg = <3>;
81 device_type = "ethernet-phy";
82 };
83 };
84
85 ethernet@24000 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 device_type = "network";
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]89 device-id = <1>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]90 compatible = "fs_enet";
91 model = "FCC";
92 reg = <11300 20 8400 100 11380 30>;
93 mac-address = [ 00 11 2F 99 43 54 ];
94 interrupts = <20 2>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]95 interrupt-parent = <&Cpm_pic>;
96 phy-handle = <&Phy0>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]97 rx-clock = <13>;
98 tx-clock = <12>;
99 };
100
101 ethernet@25000 {
102 device_type = "network";
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]103 device-id = <2>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]104 compatible = "fs_enet";
105 model = "FCC";
106 reg = <11320 20 8500 100 113b0 30>;
107 mac-address = [ 00 11 2F 99 44 54 ];
108 interrupts = <21 2>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]109 interrupt-parent = <&Cpm_pic>;
110 phy-handle = <&Phy1>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]111 rx-clock = <17>;
112 tx-clock = <18>;
113 };
114
115 cpm@f0000000 {
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]116 #address-cells = <1>;
117 #size-cells = <1>;
118 #interrupt-cells = <2>;
119 device_type = "cpm";
120 model = "CPM2";
Vitaly Bordug54278282007-01-31 02:09:00 +0300[diff] [blame]121 ranges = <00000000 00000000 20000>;
122 reg = <0 20000>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]123 command-proc = <119c0>;
124 brg-frequency = <17D7840>;
125 cpm_clk = <BEBC200>;
126
127 scc@11a00 {
128 device_type = "serial";
129 compatible = "cpm_uart";
130 model = "SCC";
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]131 device-id = <1>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]132 reg = <11a00 20 8000 100>;
133 current-speed = <1c200>;
134 interrupts = <28 2>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]135 interrupt-parent = <&Cpm_pic>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]136 clock-setup = <0 00ffffff>;
137 rx-clock = <1>;
138 tx-clock = <1>;
139 };
140
141 scc@11a60 {
142 device_type = "serial";
143 compatible = "cpm_uart";
144 model = "SCC";
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]145 device-id = <4>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]146 reg = <11a60 20 8300 100>;
147 current-speed = <1c200>;
148 interrupts = <2b 2>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]149 interrupt-parent = <&Cpm_pic>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]150 clock-setup = <1b ffffff00>;
151 rx-clock = <4>;
152 tx-clock = <4>;
153 };
154
155 };
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]156 cpm_pic:interrupt-controller@10c00 {
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]157 #address-cells = <0>;
158 #interrupt-cells = <2>;
159 interrupt-controller;
160 reg = <10c00 80>;
161 built-in;
162 device_type = "cpm-pic";
163 compatible = "CPM2";
164 };
165 pci@0500 {
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]166 #interrupt-cells = <1>;
167 #size-cells = <2>;
168 #address-cells = <3>;
169 compatible = "8272";
170 device_type = "pci";
171 reg = <10430 4dc>;
172 clock-frequency = <3f940aa>;
173 interrupt-map-mask = <f800 0 0 7>;
174 interrupt-map = <
175
176 /* IDSEL 0x16 */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]177 b000 0 0 1 f8200000 40 8
178 b000 0 0 2 f8200000 41 8
179 b000 0 0 3 f8200000 42 8
180 b000 0 0 4 f8200000 43 8
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]181
182 /* IDSEL 0x17 */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]183 b800 0 0 1 f8200000 43 8
184 b800 0 0 2 f8200000 40 8
185 b800 0 0 3 f8200000 41 8
186 b800 0 0 4 f8200000 42 8
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]187
188 /* IDSEL 0x18 */
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]189 c000 0 0 1 f8200000 42 8
190 c000 0 0 2 f8200000 43 8
191 c000 0 0 3 f8200000 40 8
192 c000 0 0 4 f8200000 41 8>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]193 interrupt-parent = <&Cpm_pic>;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]194 interrupts = <14 8>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]195 bus-range = <0 0>;
196 ranges = <02000000 0 80000000 80000000 0 40000000
197 01000000 0 00000000 f6000000 0 02000000>;
198 };
199
200/* May need to remove if on a part without crypto engine */
201 crypto@30000 {
202 device_type = "crypto";
203 model = "SEC2";
204 compatible = "talitos";
205 reg = <30000 10000>;
Vitaly Bordug73844ec2007-01-31 02:08:54 +0300[diff] [blame]206 interrupts = <b 2>;
Vitaly Bordugb8ce2272007-07-09 11:37:36 -0700[diff] [blame]207 interrupt-parent = <&Cpm_pic>;
Vitaly Borduge02f73e2006-10-02 22:22:36 +0400[diff] [blame]208 num-channels = <4>;
209 channel-fifo-len = <18>;
210 exec-units-mask = <0000007e>;
211/* desc mask is for rev1.x, we need runtime fixup for >=2.x */
212 descriptor-types-mask = <01010ebf>;
213 };
214
215 };
216};