Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef _M68KNOMMU_CACHEFLUSH_H |
| 2 | #define _M68KNOMMU_CACHEFLUSH_H |
| 3 | |
| 4 | /* |
Greg Ungerer | 8ce877a | 2010-11-09 13:35:55 +1000 | [diff] [blame] | 5 | * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | */ |
| 7 | #include <linux/mm.h> |
Greg Ungerer | 3d46140 | 2010-11-09 10:40:44 +1000 | [diff] [blame] | 8 | #include <asm/mcfsim.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | |
| 10 | #define flush_cache_all() __flush_cache_all() |
| 11 | #define flush_cache_mm(mm) do { } while (0) |
Ralf Baechle | ec8c044 | 2006-12-12 17:14:57 +0000 | [diff] [blame] | 12 | #define flush_cache_dup_mm(mm) do { } while (0) |
Greg Ungerer | 8ce877a | 2010-11-09 13:35:55 +1000 | [diff] [blame] | 13 | #define flush_cache_range(vma, start, end) do { } while (0) |
Greg Ungerer | 962d69e | 2005-09-13 11:14:08 +1000 | [diff] [blame] | 14 | #define flush_cache_page(vma, vmaddr) do { } while (0) |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 15 | #define flush_dcache_range(start, len) __flush_dcache_all() |
Ilya Loginov | 2d4dc89 | 2009-11-26 09:16:19 +0100 | [diff] [blame] | 16 | #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #define flush_dcache_page(page) do { } while (0) |
| 18 | #define flush_dcache_mmap_lock(mapping) do { } while (0) |
| 19 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 20 | #define flush_icache_range(start, len) __flush_icache_all() |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #define flush_icache_page(vma,pg) do { } while (0) |
| 22 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) |
Greg Ungerer | 962d69e | 2005-09-13 11:14:08 +1000 | [diff] [blame] | 23 | #define flush_cache_vmap(start, end) do { } while (0) |
| 24 | #define flush_cache_vunmap(start, end) do { } while (0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
| 26 | #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ |
| 27 | memcpy(dst, src, len) |
| 28 | #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ |
| 29 | memcpy(dst, src, len) |
| 30 | |
Greg Ungerer | d475e3e4 | 2010-11-09 14:27:50 +1000 | [diff] [blame] | 31 | void mcf_cache_push(void); |
| 32 | |
Greg Ungerer | 1744bd9 | 2012-05-02 17:02:21 +1000 | [diff] [blame] | 33 | static inline void __clear_cache_all(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | { |
Greg Ungerer | 8ce877a | 2010-11-09 13:35:55 +1000 | [diff] [blame] | 35 | #ifdef CACHE_INVALIDATE |
Greg Ungerer | a1a9bcb | 2009-01-13 10:17:30 +1000 | [diff] [blame] | 36 | __asm__ __volatile__ ( |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 37 | "movec %0, %%CACR\n\t" |
Greg Ungerer | a1a9bcb | 2009-01-13 10:17:30 +1000 | [diff] [blame] | 38 | "nop\n\t" |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 39 | : : "r" (CACHE_INVALIDATE) ); |
Greg Ungerer | 8ce877a | 2010-11-09 13:35:55 +1000 | [diff] [blame] | 40 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
Greg Ungerer | 1744bd9 | 2012-05-02 17:02:21 +1000 | [diff] [blame] | 43 | static inline void __flush_cache_all(void) |
| 44 | { |
| 45 | #ifdef CACHE_PUSH |
| 46 | mcf_cache_push(); |
| 47 | #endif |
| 48 | __clear_cache_all(); |
| 49 | } |
| 50 | |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 51 | /* |
| 52 | * Some ColdFire parts implement separate instruction and data caches, |
| 53 | * on those we should just flush the appropriate cache. If we don't need |
| 54 | * to do any specific flushing then this will be optimized away. |
| 55 | */ |
| 56 | static inline void __flush_icache_all(void) |
| 57 | { |
| 58 | #ifdef CACHE_INVALIDATEI |
| 59 | __asm__ __volatile__ ( |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 60 | "movec %0, %%CACR\n\t" |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 61 | "nop\n\t" |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 62 | : : "r" (CACHE_INVALIDATEI) ); |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 63 | #endif |
| 64 | } |
| 65 | |
| 66 | static inline void __flush_dcache_all(void) |
| 67 | { |
| 68 | #ifdef CACHE_PUSH |
| 69 | mcf_cache_push(); |
| 70 | #endif |
| 71 | #ifdef CACHE_INVALIDATED |
| 72 | __asm__ __volatile__ ( |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 73 | "movec %0, %%CACR\n\t" |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 74 | "nop\n\t" |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 75 | : : "r" (CACHE_INVALIDATED) ); |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 76 | #else |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 77 | /* Flush the write buffer */ |
Greg Ungerer | 07ffee5 | 2010-11-10 15:22:19 +1000 | [diff] [blame] | 78 | __asm__ __volatile__ ( "nop" ); |
| 79 | #endif |
| 80 | } |
Greg Ungerer | 1744bd9 | 2012-05-02 17:02:21 +1000 | [diff] [blame] | 81 | |
| 82 | /* |
| 83 | * Push cache entries at supplied address. We want to write back any dirty |
Philippe De Muyter | 300b9ff | 2012-09-09 17:56:35 +0200 | [diff] [blame] | 84 | * data and then invalidate the cache lines associated with this address. |
Greg Ungerer | 1744bd9 | 2012-05-02 17:02:21 +1000 | [diff] [blame] | 85 | */ |
| 86 | static inline void cache_push(unsigned long paddr, int len) |
| 87 | { |
| 88 | __flush_cache_all(); |
| 89 | } |
| 90 | |
| 91 | /* |
| 92 | * Clear cache entries at supplied address (that is don't write back any |
| 93 | * dirty data). |
| 94 | */ |
| 95 | static inline void cache_clear(unsigned long paddr, int len) |
| 96 | { |
| 97 | __clear_cache_all(); |
| 98 | } |
| 99 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | #endif /* _M68KNOMMU_CACHEFLUSH_H */ |