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gerrit-public.fairphone.software / kernel / msm-5.4 / 4c9c0d09741deab0aac76b83961cfe95b24f3e6f / . / drivers / gpu / drm / i915 / i915_oa_glk.c
blob: 2f356d51bff8cdc65f2f33e4b6d20a70130375fd [file] [log] [blame]
Lionel Landwerlin28c7ef92017-06-13 12:23:09 +0100[diff] [blame]1/*
2 * Autogenerated file by GPU Top : https://github.com/rib/gputop
3 * DO NOT EDIT manually!
4 *
5 *
6 * Copyright (c) 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 *
27 */
28
29#include <linux/sysfs.h>
30
31#include "i915_drv.h"
32#include "i915_oa_glk.h"
33
34enum metric_set_id {
35 METRIC_SET_ID_RENDER_BASIC = 1,
36 METRIC_SET_ID_COMPUTE_BASIC,
37 METRIC_SET_ID_RENDER_PIPE_PROFILE,
38 METRIC_SET_ID_MEMORY_READS,
39 METRIC_SET_ID_MEMORY_WRITES,
40 METRIC_SET_ID_COMPUTE_EXTENDED,
41 METRIC_SET_ID_COMPUTE_L3_CACHE,
42 METRIC_SET_ID_HDC_AND_SF,
43 METRIC_SET_ID_L3_1,
44 METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
45 METRIC_SET_ID_SAMPLER,
46 METRIC_SET_ID_TDL_1,
47 METRIC_SET_ID_TDL_2,
48 METRIC_SET_ID_COMPUTE_EXTRA,
49 METRIC_SET_ID_TEST_OA,
50};
51
52int i915_oa_n_builtin_metric_sets_glk = 15;
53
54static const struct i915_oa_reg b_counter_config_render_basic[] = {
55 { _MMIO(0x2710), 0x00000000 },
56 { _MMIO(0x2714), 0x00800000 },
57 { _MMIO(0x2720), 0x00000000 },
58 { _MMIO(0x2724), 0x00800000 },
59 { _MMIO(0x2740), 0x00000000 },
60};
61
62static const struct i915_oa_reg flex_eu_config_render_basic[] = {
63 { _MMIO(0xe458), 0x00005004 },
64 { _MMIO(0xe558), 0x00010003 },
65 { _MMIO(0xe658), 0x00012011 },
66 { _MMIO(0xe758), 0x00015014 },
67 { _MMIO(0xe45c), 0x00051050 },
68 { _MMIO(0xe55c), 0x00053052 },
69 { _MMIO(0xe65c), 0x00055054 },
70};
71
72static const struct i915_oa_reg mux_config_render_basic[] = {
73 { _MMIO(0x9888), 0x166c00f0 },
74 { _MMIO(0x9888), 0x12120280 },
75 { _MMIO(0x9888), 0x12320280 },
76 { _MMIO(0x9888), 0x11930317 },
77 { _MMIO(0x9888), 0x159303df },
78 { _MMIO(0x9888), 0x3f900c00 },
79 { _MMIO(0x9888), 0x419000a0 },
80 { _MMIO(0x9888), 0x002d1000 },
81 { _MMIO(0x9888), 0x062d4000 },
82 { _MMIO(0x9888), 0x082d5000 },
83 { _MMIO(0x9888), 0x0a2d1000 },
84 { _MMIO(0x9888), 0x0c2e0800 },
85 { _MMIO(0x9888), 0x0e2e5900 },
86 { _MMIO(0x9888), 0x0a4c8000 },
87 { _MMIO(0x9888), 0x0c4c8000 },
88 { _MMIO(0x9888), 0x0e4c4000 },
89 { _MMIO(0x9888), 0x064e8000 },
90 { _MMIO(0x9888), 0x084e8000 },
91 { _MMIO(0x9888), 0x0a4e2000 },
92 { _MMIO(0x9888), 0x1c4f0010 },
93 { _MMIO(0x9888), 0x0a6c0053 },
94 { _MMIO(0x9888), 0x106c0000 },
95 { _MMIO(0x9888), 0x1c6c0000 },
96 { _MMIO(0x9888), 0x1a0fcc00 },
97 { _MMIO(0x9888), 0x1c0f0002 },
98 { _MMIO(0x9888), 0x1c2c0040 },
99 { _MMIO(0x9888), 0x00101000 },
100 { _MMIO(0x9888), 0x04101000 },
101 { _MMIO(0x9888), 0x00114000 },
102 { _MMIO(0x9888), 0x08114000 },
103 { _MMIO(0x9888), 0x00120020 },
104 { _MMIO(0x9888), 0x08120021 },
105 { _MMIO(0x9888), 0x00141000 },
106 { _MMIO(0x9888), 0x08141000 },
107 { _MMIO(0x9888), 0x02308000 },
108 { _MMIO(0x9888), 0x04302000 },
109 { _MMIO(0x9888), 0x06318000 },
110 { _MMIO(0x9888), 0x08318000 },
111 { _MMIO(0x9888), 0x06320800 },
112 { _MMIO(0x9888), 0x08320840 },
113 { _MMIO(0x9888), 0x00320000 },
114 { _MMIO(0x9888), 0x06344000 },
115 { _MMIO(0x9888), 0x08344000 },
116 { _MMIO(0x9888), 0x0d931831 },
117 { _MMIO(0x9888), 0x0f939f3f },
118 { _MMIO(0x9888), 0x01939e80 },
119 { _MMIO(0x9888), 0x039303bc },
120 { _MMIO(0x9888), 0x0593000e },
121 { _MMIO(0x9888), 0x1993002a },
122 { _MMIO(0x9888), 0x07930000 },
123 { _MMIO(0x9888), 0x09930000 },
124 { _MMIO(0x9888), 0x1d900177 },
125 { _MMIO(0x9888), 0x1f900187 },
126 { _MMIO(0x9888), 0x35900000 },
127 { _MMIO(0x9888), 0x13904000 },
128 { _MMIO(0x9888), 0x21904000 },
129 { _MMIO(0x9888), 0x23904000 },
130 { _MMIO(0x9888), 0x25904000 },
131 { _MMIO(0x9888), 0x27904000 },
132 { _MMIO(0x9888), 0x2b904000 },
133 { _MMIO(0x9888), 0x2d904000 },
134 { _MMIO(0x9888), 0x2f904000 },
135 { _MMIO(0x9888), 0x31904000 },
136 { _MMIO(0x9888), 0x15904000 },
137 { _MMIO(0x9888), 0x17904000 },
138 { _MMIO(0x9888), 0x19904000 },
139 { _MMIO(0x9888), 0x1b904000 },
140 { _MMIO(0x9888), 0x53901110 },
141 { _MMIO(0x9888), 0x43900423 },
142 { _MMIO(0x9888), 0x55900111 },
143 { _MMIO(0x9888), 0x47900c02 },
144 { _MMIO(0x9888), 0x57900000 },
145 { _MMIO(0x9888), 0x49900020 },
146 { _MMIO(0x9888), 0x59901111 },
147 { _MMIO(0x9888), 0x4b900421 },
148 { _MMIO(0x9888), 0x37900000 },
149 { _MMIO(0x9888), 0x33900000 },
150 { _MMIO(0x9888), 0x4d900001 },
151 { _MMIO(0x9888), 0x45900821 },
152};
153
154static int
155get_render_basic_mux_config(struct drm_i915_private *dev_priv,
156 const struct i915_oa_reg **regs,
157 int *lens)
158{
159 int n = 0;
160
161 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
162 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
163
164 regs[n] = mux_config_render_basic;
165 lens[n] = ARRAY_SIZE(mux_config_render_basic);
166 n++;
167
168 return n;
169}
170
171static const struct i915_oa_reg b_counter_config_compute_basic[] = {
172 { _MMIO(0x2710), 0x00000000 },
173 { _MMIO(0x2714), 0x00800000 },
174 { _MMIO(0x2720), 0x00000000 },
175 { _MMIO(0x2724), 0x00800000 },
176 { _MMIO(0x2740), 0x00000000 },
177};
178
179static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
180 { _MMIO(0xe458), 0x00005004 },
181 { _MMIO(0xe558), 0x00000003 },
182 { _MMIO(0xe658), 0x00002001 },
183 { _MMIO(0xe758), 0x00778008 },
184 { _MMIO(0xe45c), 0x00088078 },
185 { _MMIO(0xe55c), 0x00808708 },
186 { _MMIO(0xe65c), 0x00a08908 },
187};
188
189static const struct i915_oa_reg mux_config_compute_basic[] = {
190 { _MMIO(0x9888), 0x104f00e0 },
191 { _MMIO(0x9888), 0x124f1c00 },
192 { _MMIO(0x9888), 0x39900340 },
193 { _MMIO(0x9888), 0x3f900c00 },
194 { _MMIO(0x9888), 0x41900000 },
195 { _MMIO(0x9888), 0x002d5000 },
196 { _MMIO(0x9888), 0x062d4000 },
197 { _MMIO(0x9888), 0x082d4000 },
198 { _MMIO(0x9888), 0x0a2d1000 },
199 { _MMIO(0x9888), 0x0c2d5000 },
200 { _MMIO(0x9888), 0x0e2d4000 },
201 { _MMIO(0x9888), 0x0c2e1400 },
202 { _MMIO(0x9888), 0x0e2e5100 },
203 { _MMIO(0x9888), 0x102e0114 },
204 { _MMIO(0x9888), 0x044cc000 },
205 { _MMIO(0x9888), 0x0a4c8000 },
206 { _MMIO(0x9888), 0x0c4c8000 },
207 { _MMIO(0x9888), 0x0e4c4000 },
208 { _MMIO(0x9888), 0x104c8000 },
209 { _MMIO(0x9888), 0x124c8000 },
210 { _MMIO(0x9888), 0x164c2000 },
211 { _MMIO(0x9888), 0x004ea000 },
212 { _MMIO(0x9888), 0x064e8000 },
213 { _MMIO(0x9888), 0x084e8000 },
214 { _MMIO(0x9888), 0x0a4e2000 },
215 { _MMIO(0x9888), 0x0c4ea000 },
216 { _MMIO(0x9888), 0x0e4e8000 },
217 { _MMIO(0x9888), 0x004f6b42 },
218 { _MMIO(0x9888), 0x064f6200 },
219 { _MMIO(0x9888), 0x084f4100 },
220 { _MMIO(0x9888), 0x0a4f0061 },
221 { _MMIO(0x9888), 0x0c4f6c4c },
222 { _MMIO(0x9888), 0x0e4f4b00 },
223 { _MMIO(0x9888), 0x1a4f0000 },
224 { _MMIO(0x9888), 0x1c4f0000 },
225 { _MMIO(0x9888), 0x180f5000 },
226 { _MMIO(0x9888), 0x1a0f8800 },
227 { _MMIO(0x9888), 0x1c0f08a2 },
228 { _MMIO(0x9888), 0x182c4000 },
229 { _MMIO(0x9888), 0x1c2c1451 },
230 { _MMIO(0x9888), 0x1e2c0001 },
231 { _MMIO(0x9888), 0x1a2c0010 },
232 { _MMIO(0x9888), 0x01938000 },
233 { _MMIO(0x9888), 0x0f938000 },
234 { _MMIO(0x9888), 0x19938a28 },
235 { _MMIO(0x9888), 0x03938000 },
236 { _MMIO(0x9888), 0x19900177 },
237 { _MMIO(0x9888), 0x1b900178 },
238 { _MMIO(0x9888), 0x1d900125 },
239 { _MMIO(0x9888), 0x1f900123 },
240 { _MMIO(0x9888), 0x35900000 },
241 { _MMIO(0x9888), 0x13904000 },
242 { _MMIO(0x9888), 0x21904000 },
243 { _MMIO(0x9888), 0x25904000 },
244 { _MMIO(0x9888), 0x27904000 },
245 { _MMIO(0x9888), 0x2b904000 },
246 { _MMIO(0x9888), 0x2d904000 },
247 { _MMIO(0x9888), 0x31904000 },
248 { _MMIO(0x9888), 0x15904000 },
249 { _MMIO(0x9888), 0x53901000 },
250 { _MMIO(0x9888), 0x43900000 },
251 { _MMIO(0x9888), 0x55900111 },
252 { _MMIO(0x9888), 0x47900000 },
253 { _MMIO(0x9888), 0x57900000 },
254 { _MMIO(0x9888), 0x49900000 },
255 { _MMIO(0x9888), 0x59900000 },
256 { _MMIO(0x9888), 0x4b900000 },
257 { _MMIO(0x9888), 0x37900000 },
258 { _MMIO(0x9888), 0x33900000 },
259 { _MMIO(0x9888), 0x4d900000 },
260 { _MMIO(0x9888), 0x45900000 },
261};
262
263static int
264get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
265 const struct i915_oa_reg **regs,
266 int *lens)
267{
268 int n = 0;
269
270 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
271 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
272
273 regs[n] = mux_config_compute_basic;
274 lens[n] = ARRAY_SIZE(mux_config_compute_basic);
275 n++;
276
277 return n;
278}
279
280static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
281 { _MMIO(0x2724), 0xf0800000 },
282 { _MMIO(0x2720), 0x00000000 },
283 { _MMIO(0x2714), 0xf0800000 },
284 { _MMIO(0x2710), 0x00000000 },
285 { _MMIO(0x2740), 0x00000000 },
286 { _MMIO(0x2770), 0x0007ffea },
287 { _MMIO(0x2774), 0x00007ffc },
288 { _MMIO(0x2778), 0x0007affa },
289 { _MMIO(0x277c), 0x0000f5fd },
290 { _MMIO(0x2780), 0x00079ffa },
291 { _MMIO(0x2784), 0x0000f3fb },
292 { _MMIO(0x2788), 0x0007bf7a },
293 { _MMIO(0x278c), 0x0000f7e7 },
294 { _MMIO(0x2790), 0x0007fefa },
295 { _MMIO(0x2794), 0x0000f7cf },
296 { _MMIO(0x2798), 0x00077ffa },
297 { _MMIO(0x279c), 0x0000efdf },
298 { _MMIO(0x27a0), 0x0006fffa },
299 { _MMIO(0x27a4), 0x0000cfbf },
300 { _MMIO(0x27a8), 0x0003fffa },
301 { _MMIO(0x27ac), 0x00005f7f },
302};
303
304static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
305 { _MMIO(0xe458), 0x00005004 },
306 { _MMIO(0xe558), 0x00015014 },
307 { _MMIO(0xe658), 0x00025024 },
308 { _MMIO(0xe758), 0x00035034 },
309 { _MMIO(0xe45c), 0x00045044 },
310 { _MMIO(0xe55c), 0x00055054 },
311 { _MMIO(0xe65c), 0x00065064 },
312};
313
314static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
315 { _MMIO(0x9888), 0x0c2e001f },
316 { _MMIO(0x9888), 0x0a2f0000 },
317 { _MMIO(0x9888), 0x10186800 },
318 { _MMIO(0x9888), 0x11810019 },
319 { _MMIO(0x9888), 0x15810013 },
320 { _MMIO(0x9888), 0x13820020 },
321 { _MMIO(0x9888), 0x11830020 },
322 { _MMIO(0x9888), 0x17840000 },
323 { _MMIO(0x9888), 0x11860007 },
324 { _MMIO(0x9888), 0x21860000 },
325 { _MMIO(0x9888), 0x178703e0 },
326 { _MMIO(0x9888), 0x0c2d8000 },
327 { _MMIO(0x9888), 0x042d4000 },
328 { _MMIO(0x9888), 0x062d1000 },
329 { _MMIO(0x9888), 0x022e5400 },
330 { _MMIO(0x9888), 0x002e0000 },
331 { _MMIO(0x9888), 0x0e2e0080 },
332 { _MMIO(0x9888), 0x082f0040 },
333 { _MMIO(0x9888), 0x002f0000 },
334 { _MMIO(0x9888), 0x06143000 },
335 { _MMIO(0x9888), 0x06174000 },
336 { _MMIO(0x9888), 0x06180012 },
337 { _MMIO(0x9888), 0x00180000 },
338 { _MMIO(0x9888), 0x0d804000 },
339 { _MMIO(0x9888), 0x0f804000 },
340 { _MMIO(0x9888), 0x05804000 },
341 { _MMIO(0x9888), 0x09810200 },
342 { _MMIO(0x9888), 0x0b810030 },
343 { _MMIO(0x9888), 0x03810003 },
344 { _MMIO(0x9888), 0x21819140 },
345 { _MMIO(0x9888), 0x23819050 },
346 { _MMIO(0x9888), 0x25810018 },
347 { _MMIO(0x9888), 0x0b820980 },
348 { _MMIO(0x9888), 0x03820d80 },
349 { _MMIO(0x9888), 0x11820000 },
350 { _MMIO(0x9888), 0x0182c000 },
351 { _MMIO(0x9888), 0x07828000 },
352 { _MMIO(0x9888), 0x09824000 },
353 { _MMIO(0x9888), 0x0f828000 },
354 { _MMIO(0x9888), 0x0d830004 },
355 { _MMIO(0x9888), 0x0583000c },
356 { _MMIO(0x9888), 0x0f831000 },
357 { _MMIO(0x9888), 0x01848072 },
358 { _MMIO(0x9888), 0x11840000 },
359 { _MMIO(0x9888), 0x07848000 },
360 { _MMIO(0x9888), 0x09844000 },
361 { _MMIO(0x9888), 0x0f848000 },
362 { _MMIO(0x9888), 0x07860000 },
363 { _MMIO(0x9888), 0x09860092 },
364 { _MMIO(0x9888), 0x0f860400 },
365 { _MMIO(0x9888), 0x01869100 },
366 { _MMIO(0x9888), 0x0f870065 },
367 { _MMIO(0x9888), 0x01870000 },
368 { _MMIO(0x9888), 0x19930800 },
369 { _MMIO(0x9888), 0x0b938000 },
370 { _MMIO(0x9888), 0x0d938000 },
371 { _MMIO(0x9888), 0x1b952000 },
372 { _MMIO(0x9888), 0x1d955055 },
373 { _MMIO(0x9888), 0x1f951455 },
374 { _MMIO(0x9888), 0x0992a000 },
375 { _MMIO(0x9888), 0x0f928000 },
376 { _MMIO(0x9888), 0x1192a800 },
377 { _MMIO(0x9888), 0x1392028a },
378 { _MMIO(0x9888), 0x0b92a000 },
379 { _MMIO(0x9888), 0x0d922000 },
380 { _MMIO(0x9888), 0x13908000 },
381 { _MMIO(0x9888), 0x21908000 },
382 { _MMIO(0x9888), 0x23908000 },
383 { _MMIO(0x9888), 0x25908000 },
384 { _MMIO(0x9888), 0x27908000 },
385 { _MMIO(0x9888), 0x29908000 },
386 { _MMIO(0x9888), 0x2b908000 },
387 { _MMIO(0x9888), 0x2d904000 },
388 { _MMIO(0x9888), 0x2f908000 },
389 { _MMIO(0x9888), 0x31908000 },
390 { _MMIO(0x9888), 0x15908000 },
391 { _MMIO(0x9888), 0x17908000 },
392 { _MMIO(0x9888), 0x19908000 },
393 { _MMIO(0x9888), 0x1b908000 },
394 { _MMIO(0x9888), 0x1d904000 },
395 { _MMIO(0x9888), 0x1f904000 },
396 { _MMIO(0x9888), 0x53900000 },
397 { _MMIO(0x9888), 0x43900c01 },
398 { _MMIO(0x9888), 0x55900000 },
399 { _MMIO(0x9888), 0x47900000 },
400 { _MMIO(0x9888), 0x57900000 },
401 { _MMIO(0x9888), 0x49900863 },
402 { _MMIO(0x9888), 0x59900000 },
403 { _MMIO(0x9888), 0x4b900061 },
404 { _MMIO(0x9888), 0x37900000 },
405 { _MMIO(0x9888), 0x33900000 },
406 { _MMIO(0x9888), 0x4d900000 },
407 { _MMIO(0x9888), 0x45900c22 },
408};
409
410static int
411get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
412 const struct i915_oa_reg **regs,
413 int *lens)
414{
415 int n = 0;
416
417 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
418 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
419
420 regs[n] = mux_config_render_pipe_profile;
421 lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
422 n++;
423
424 return n;
425}
426
427static const struct i915_oa_reg b_counter_config_memory_reads[] = {
428 { _MMIO(0x272c), 0xffffffff },
429 { _MMIO(0x2728), 0xffffffff },
430 { _MMIO(0x2724), 0xf0800000 },
431 { _MMIO(0x2720), 0x00000000 },
432 { _MMIO(0x271c), 0xffffffff },
433 { _MMIO(0x2718), 0xffffffff },
434 { _MMIO(0x2714), 0xf0800000 },
435 { _MMIO(0x2710), 0x00000000 },
436 { _MMIO(0x274c), 0x86543210 },
437 { _MMIO(0x2748), 0x86543210 },
438 { _MMIO(0x2744), 0x00006667 },
439 { _MMIO(0x2740), 0x00000000 },
440 { _MMIO(0x275c), 0x86543210 },
441 { _MMIO(0x2758), 0x86543210 },
442 { _MMIO(0x2754), 0x00006465 },
443 { _MMIO(0x2750), 0x00000000 },
444 { _MMIO(0x2770), 0x0007f81a },
445 { _MMIO(0x2774), 0x0000fe00 },
446 { _MMIO(0x2778), 0x0007f82a },
447 { _MMIO(0x277c), 0x0000fe00 },
448 { _MMIO(0x2780), 0x0007f872 },
449 { _MMIO(0x2784), 0x0000fe00 },
450 { _MMIO(0x2788), 0x0007f8ba },
451 { _MMIO(0x278c), 0x0000fe00 },
452 { _MMIO(0x2790), 0x0007f87a },
453 { _MMIO(0x2794), 0x0000fe00 },
454 { _MMIO(0x2798), 0x0007f8ea },
455 { _MMIO(0x279c), 0x0000fe00 },
456 { _MMIO(0x27a0), 0x0007f8e2 },
457 { _MMIO(0x27a4), 0x0000fe00 },
458 { _MMIO(0x27a8), 0x0007f8f2 },
459 { _MMIO(0x27ac), 0x0000fe00 },
460};
461
462static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
463 { _MMIO(0xe458), 0x00005004 },
464 { _MMIO(0xe558), 0x00015014 },
465 { _MMIO(0xe658), 0x00025024 },
466 { _MMIO(0xe758), 0x00035034 },
467 { _MMIO(0xe45c), 0x00045044 },
468 { _MMIO(0xe55c), 0x00055054 },
469 { _MMIO(0xe65c), 0x00065064 },
470};
471
472static const struct i915_oa_reg mux_config_memory_reads[] = {
473 { _MMIO(0x9888), 0x19800343 },
474 { _MMIO(0x9888), 0x39900340 },
475 { _MMIO(0x9888), 0x3f901000 },
476 { _MMIO(0x9888), 0x41900003 },
477 { _MMIO(0x9888), 0x03803180 },
478 { _MMIO(0x9888), 0x058035e2 },
479 { _MMIO(0x9888), 0x0780006a },
480 { _MMIO(0x9888), 0x11800000 },
481 { _MMIO(0x9888), 0x2181a000 },
482 { _MMIO(0x9888), 0x2381000a },
483 { _MMIO(0x9888), 0x1d950550 },
484 { _MMIO(0x9888), 0x0b928000 },
485 { _MMIO(0x9888), 0x0d92a000 },
486 { _MMIO(0x9888), 0x0f922000 },
487 { _MMIO(0x9888), 0x13900170 },
488 { _MMIO(0x9888), 0x21900171 },
489 { _MMIO(0x9888), 0x23900172 },
490 { _MMIO(0x9888), 0x25900173 },
491 { _MMIO(0x9888), 0x27900174 },
492 { _MMIO(0x9888), 0x29900175 },
493 { _MMIO(0x9888), 0x2b900176 },
494 { _MMIO(0x9888), 0x2d900177 },
495 { _MMIO(0x9888), 0x2f90017f },
496 { _MMIO(0x9888), 0x31900125 },
497 { _MMIO(0x9888), 0x15900123 },
498 { _MMIO(0x9888), 0x17900121 },
499 { _MMIO(0x9888), 0x35900000 },
500 { _MMIO(0x9888), 0x19908000 },
501 { _MMIO(0x9888), 0x1b908000 },
502 { _MMIO(0x9888), 0x1d908000 },
503 { _MMIO(0x9888), 0x1f908000 },
504 { _MMIO(0x9888), 0x53900000 },
505 { _MMIO(0x9888), 0x43901084 },
506 { _MMIO(0x9888), 0x55900000 },
507 { _MMIO(0x9888), 0x47901080 },
508 { _MMIO(0x9888), 0x57900000 },
509 { _MMIO(0x9888), 0x49901084 },
510 { _MMIO(0x9888), 0x59900000 },
511 { _MMIO(0x9888), 0x4b901084 },
512 { _MMIO(0x9888), 0x37900000 },
513 { _MMIO(0x9888), 0x33900000 },
514 { _MMIO(0x9888), 0x4d900004 },
515 { _MMIO(0x9888), 0x45900000 },
516};
517
518static int
519get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
520 const struct i915_oa_reg **regs,
521 int *lens)
522{
523 int n = 0;
524
525 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
526 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
527
528 regs[n] = mux_config_memory_reads;
529 lens[n] = ARRAY_SIZE(mux_config_memory_reads);
530 n++;
531
532 return n;
533}
534
535static const struct i915_oa_reg b_counter_config_memory_writes[] = {
536 { _MMIO(0x272c), 0xffffffff },
537 { _MMIO(0x2728), 0xffffffff },
538 { _MMIO(0x2724), 0xf0800000 },
539 { _MMIO(0x2720), 0x00000000 },
540 { _MMIO(0x271c), 0xffffffff },
541 { _MMIO(0x2718), 0xffffffff },
542 { _MMIO(0x2714), 0xf0800000 },
543 { _MMIO(0x2710), 0x00000000 },
544 { _MMIO(0x274c), 0x86543210 },
545 { _MMIO(0x2748), 0x86543210 },
546 { _MMIO(0x2744), 0x00006667 },
547 { _MMIO(0x2740), 0x00000000 },
548 { _MMIO(0x275c), 0x86543210 },
549 { _MMIO(0x2758), 0x86543210 },
550 { _MMIO(0x2754), 0x00006465 },
551 { _MMIO(0x2750), 0x00000000 },
552 { _MMIO(0x2770), 0x0007f81a },
553 { _MMIO(0x2774), 0x0000fe00 },
554 { _MMIO(0x2778), 0x0007f82a },
555 { _MMIO(0x277c), 0x0000fe00 },
556 { _MMIO(0x2780), 0x0007f822 },
557 { _MMIO(0x2784), 0x0000fe00 },
558 { _MMIO(0x2788), 0x0007f8ba },
559 { _MMIO(0x278c), 0x0000fe00 },
560 { _MMIO(0x2790), 0x0007f87a },
561 { _MMIO(0x2794), 0x0000fe00 },
562 { _MMIO(0x2798), 0x0007f8ea },
563 { _MMIO(0x279c), 0x0000fe00 },
564 { _MMIO(0x27a0), 0x0007f8e2 },
565 { _MMIO(0x27a4), 0x0000fe00 },
566 { _MMIO(0x27a8), 0x0007f8f2 },
567 { _MMIO(0x27ac), 0x0000fe00 },
568};
569
570static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
571 { _MMIO(0xe458), 0x00005004 },
572 { _MMIO(0xe558), 0x00015014 },
573 { _MMIO(0xe658), 0x00025024 },
574 { _MMIO(0xe758), 0x00035034 },
575 { _MMIO(0xe45c), 0x00045044 },
576 { _MMIO(0xe55c), 0x00055054 },
577 { _MMIO(0xe65c), 0x00065064 },
578};
579
580static const struct i915_oa_reg mux_config_memory_writes[] = {
581 { _MMIO(0x9888), 0x19800343 },
582 { _MMIO(0x9888), 0x39900340 },
583 { _MMIO(0x9888), 0x3f900000 },
584 { _MMIO(0x9888), 0x41900080 },
585 { _MMIO(0x9888), 0x03803180 },
586 { _MMIO(0x9888), 0x058035e2 },
587 { _MMIO(0x9888), 0x0780006a },
588 { _MMIO(0x9888), 0x11800000 },
589 { _MMIO(0x9888), 0x2181a000 },
590 { _MMIO(0x9888), 0x2381000a },
591 { _MMIO(0x9888), 0x1d950550 },
592 { _MMIO(0x9888), 0x0b928000 },
593 { _MMIO(0x9888), 0x0d92a000 },
594 { _MMIO(0x9888), 0x0f922000 },
595 { _MMIO(0x9888), 0x13900180 },
596 { _MMIO(0x9888), 0x21900181 },
597 { _MMIO(0x9888), 0x23900182 },
598 { _MMIO(0x9888), 0x25900183 },
599 { _MMIO(0x9888), 0x27900184 },
600 { _MMIO(0x9888), 0x29900185 },
601 { _MMIO(0x9888), 0x2b900186 },
602 { _MMIO(0x9888), 0x2d900187 },
603 { _MMIO(0x9888), 0x2f900170 },
604 { _MMIO(0x9888), 0x31900125 },
605 { _MMIO(0x9888), 0x15900123 },
606 { _MMIO(0x9888), 0x17900121 },
607 { _MMIO(0x9888), 0x35900000 },
608 { _MMIO(0x9888), 0x19908000 },
609 { _MMIO(0x9888), 0x1b908000 },
610 { _MMIO(0x9888), 0x1d908000 },
611 { _MMIO(0x9888), 0x1f908000 },
612 { _MMIO(0x9888), 0x53900000 },
613 { _MMIO(0x9888), 0x43901084 },
614 { _MMIO(0x9888), 0x55900000 },
615 { _MMIO(0x9888), 0x47901080 },
616 { _MMIO(0x9888), 0x57900000 },
617 { _MMIO(0x9888), 0x49901084 },
618 { _MMIO(0x9888), 0x59900000 },
619 { _MMIO(0x9888), 0x4b901084 },
620 { _MMIO(0x9888), 0x37900000 },
621 { _MMIO(0x9888), 0x33900000 },
622 { _MMIO(0x9888), 0x4d900004 },
623 { _MMIO(0x9888), 0x45900000 },
624};
625
626static int
627get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
628 const struct i915_oa_reg **regs,
629 int *lens)
630{
631 int n = 0;
632
633 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
634 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
635
636 regs[n] = mux_config_memory_writes;
637 lens[n] = ARRAY_SIZE(mux_config_memory_writes);
638 n++;
639
640 return n;
641}
642
643static const struct i915_oa_reg b_counter_config_compute_extended[] = {
644 { _MMIO(0x2724), 0xf0800000 },
645 { _MMIO(0x2720), 0x00000000 },
646 { _MMIO(0x2714), 0xf0800000 },
647 { _MMIO(0x2710), 0x00000000 },
648 { _MMIO(0x2740), 0x00000000 },
649 { _MMIO(0x2770), 0x0007fc2a },
650 { _MMIO(0x2774), 0x0000bf00 },
651 { _MMIO(0x2778), 0x0007fc6a },
652 { _MMIO(0x277c), 0x0000bf00 },
653 { _MMIO(0x2780), 0x0007fc92 },
654 { _MMIO(0x2784), 0x0000bf00 },
655 { _MMIO(0x2788), 0x0007fca2 },
656 { _MMIO(0x278c), 0x0000bf00 },
657 { _MMIO(0x2790), 0x0007fc32 },
658 { _MMIO(0x2794), 0x0000bf00 },
659 { _MMIO(0x2798), 0x0007fc9a },
660 { _MMIO(0x279c), 0x0000bf00 },
661 { _MMIO(0x27a0), 0x0007fe6a },
662 { _MMIO(0x27a4), 0x0000bf00 },
663 { _MMIO(0x27a8), 0x0007fe7a },
664 { _MMIO(0x27ac), 0x0000bf00 },
665};
666
667static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
668 { _MMIO(0xe458), 0x00005004 },
669 { _MMIO(0xe558), 0x00000003 },
670 { _MMIO(0xe658), 0x00002001 },
671 { _MMIO(0xe758), 0x00778008 },
672 { _MMIO(0xe45c), 0x00088078 },
673 { _MMIO(0xe55c), 0x00808708 },
674 { _MMIO(0xe65c), 0x00a08908 },
675};
676
677static const struct i915_oa_reg mux_config_compute_extended[] = {
678 { _MMIO(0x9888), 0x104f00e0 },
679 { _MMIO(0x9888), 0x141c0160 },
680 { _MMIO(0x9888), 0x161c0015 },
681 { _MMIO(0x9888), 0x181c0120 },
682 { _MMIO(0x9888), 0x002d5000 },
683 { _MMIO(0x9888), 0x062d4000 },
684 { _MMIO(0x9888), 0x082d5000 },
685 { _MMIO(0x9888), 0x0a2d5000 },
686 { _MMIO(0x9888), 0x0c2d5000 },
687 { _MMIO(0x9888), 0x0e2d5000 },
688 { _MMIO(0x9888), 0x022d5000 },
689 { _MMIO(0x9888), 0x042d5000 },
690 { _MMIO(0x9888), 0x0c2e5400 },
691 { _MMIO(0x9888), 0x0e2e5515 },
692 { _MMIO(0x9888), 0x102e0155 },
693 { _MMIO(0x9888), 0x044cc000 },
694 { _MMIO(0x9888), 0x0a4c8000 },
695 { _MMIO(0x9888), 0x0c4cc000 },
696 { _MMIO(0x9888), 0x0e4cc000 },
697 { _MMIO(0x9888), 0x104c8000 },
698 { _MMIO(0x9888), 0x124c8000 },
699 { _MMIO(0x9888), 0x144c8000 },
700 { _MMIO(0x9888), 0x164c2000 },
701 { _MMIO(0x9888), 0x064cc000 },
702 { _MMIO(0x9888), 0x084cc000 },
703 { _MMIO(0x9888), 0x004ea000 },
704 { _MMIO(0x9888), 0x064e8000 },
705 { _MMIO(0x9888), 0x084ea000 },
706 { _MMIO(0x9888), 0x0a4ea000 },
707 { _MMIO(0x9888), 0x0c4ea000 },
708 { _MMIO(0x9888), 0x0e4ea000 },
709 { _MMIO(0x9888), 0x024ea000 },
710 { _MMIO(0x9888), 0x044ea000 },
711 { _MMIO(0x9888), 0x0e4f4b41 },
712 { _MMIO(0x9888), 0x004f4200 },
713 { _MMIO(0x9888), 0x024f404c },
714 { _MMIO(0x9888), 0x1c4f0000 },
715 { _MMIO(0x9888), 0x1a4f0000 },
716 { _MMIO(0x9888), 0x001b4000 },
717 { _MMIO(0x9888), 0x061b8000 },
718 { _MMIO(0x9888), 0x081bc000 },
719 { _MMIO(0x9888), 0x0a1bc000 },
720 { _MMIO(0x9888), 0x0c1bc000 },
721 { _MMIO(0x9888), 0x041bc000 },
722 { _MMIO(0x9888), 0x001c0031 },
723 { _MMIO(0x9888), 0x061c1900 },
724 { _MMIO(0x9888), 0x081c1a33 },
725 { _MMIO(0x9888), 0x0a1c1b35 },
726 { _MMIO(0x9888), 0x0c1c3337 },
727 { _MMIO(0x9888), 0x041c31c7 },
728 { _MMIO(0x9888), 0x180f5000 },
729 { _MMIO(0x9888), 0x1a0fa8aa },
730 { _MMIO(0x9888), 0x1c0f0aaa },
731 { _MMIO(0x9888), 0x182c8000 },
732 { _MMIO(0x9888), 0x1c2c6aaa },
733 { _MMIO(0x9888), 0x1e2c0001 },
734 { _MMIO(0x9888), 0x1a2c2950 },
735 { _MMIO(0x9888), 0x01938000 },
736 { _MMIO(0x9888), 0x0f938000 },
737 { _MMIO(0x9888), 0x1993aaaa },
738 { _MMIO(0x9888), 0x03938000 },
739 { _MMIO(0x9888), 0x05938000 },
740 { _MMIO(0x9888), 0x07938000 },
741 { _MMIO(0x9888), 0x09938000 },
742 { _MMIO(0x9888), 0x0b938000 },
743 { _MMIO(0x9888), 0x13904000 },
744 { _MMIO(0x9888), 0x21904000 },
745 { _MMIO(0x9888), 0x23904000 },
746 { _MMIO(0x9888), 0x25904000 },
747 { _MMIO(0x9888), 0x27904000 },
748 { _MMIO(0x9888), 0x29904000 },
749 { _MMIO(0x9888), 0x2b904000 },
750 { _MMIO(0x9888), 0x2d904000 },
751 { _MMIO(0x9888), 0x2f904000 },
752 { _MMIO(0x9888), 0x31904000 },
753 { _MMIO(0x9888), 0x15904000 },
754 { _MMIO(0x9888), 0x17904000 },
755 { _MMIO(0x9888), 0x19904000 },
756 { _MMIO(0x9888), 0x1b904000 },
757 { _MMIO(0x9888), 0x1d904000 },
758 { _MMIO(0x9888), 0x53900000 },
759 { _MMIO(0x9888), 0x43900420 },
760 { _MMIO(0x9888), 0x55900000 },
761 { _MMIO(0x9888), 0x47900000 },
762 { _MMIO(0x9888), 0x57900000 },
763 { _MMIO(0x9888), 0x49900000 },
764 { _MMIO(0x9888), 0x59900000 },
765 { _MMIO(0x9888), 0x4b900400 },
766 { _MMIO(0x9888), 0x37900000 },
767 { _MMIO(0x9888), 0x33900000 },
768 { _MMIO(0x9888), 0x4d900001 },
769 { _MMIO(0x9888), 0x45900001 },
770};
771
772static int
773get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
774 const struct i915_oa_reg **regs,
775 int *lens)
776{
777 int n = 0;
778
779 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
780 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
781
782 regs[n] = mux_config_compute_extended;
783 lens[n] = ARRAY_SIZE(mux_config_compute_extended);
784 n++;
785
786 return n;
787}
788
789static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
790 { _MMIO(0x2710), 0x00000000 },
791 { _MMIO(0x2714), 0x30800000 },
792 { _MMIO(0x2720), 0x00000000 },
793 { _MMIO(0x2724), 0x30800000 },
794 { _MMIO(0x2740), 0x00000000 },
795 { _MMIO(0x2770), 0x0007fffa },
796 { _MMIO(0x2774), 0x0000fefe },
797 { _MMIO(0x2778), 0x0007fffa },
798 { _MMIO(0x277c), 0x0000fefd },
799 { _MMIO(0x2790), 0x0007fffa },
800 { _MMIO(0x2794), 0x0000fbef },
801 { _MMIO(0x2798), 0x0007fffa },
802 { _MMIO(0x279c), 0x0000fbdf },
803};
804
805static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
806 { _MMIO(0xe458), 0x00005004 },
807 { _MMIO(0xe558), 0x00000003 },
808 { _MMIO(0xe658), 0x00002001 },
809 { _MMIO(0xe758), 0x00101100 },
810 { _MMIO(0xe45c), 0x00201200 },
811 { _MMIO(0xe55c), 0x00301300 },
812 { _MMIO(0xe65c), 0x00401400 },
813};
814
815static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
816 { _MMIO(0x9888), 0x166c03b0 },
817 { _MMIO(0x9888), 0x1593001e },
818 { _MMIO(0x9888), 0x3f900c00 },
819 { _MMIO(0x9888), 0x41900000 },
820 { _MMIO(0x9888), 0x002d1000 },
821 { _MMIO(0x9888), 0x062d4000 },
822 { _MMIO(0x9888), 0x082d5000 },
823 { _MMIO(0x9888), 0x0e2d5000 },
824 { _MMIO(0x9888), 0x0c2e0400 },
825 { _MMIO(0x9888), 0x0e2e1500 },
826 { _MMIO(0x9888), 0x102e0140 },
827 { _MMIO(0x9888), 0x044c4000 },
828 { _MMIO(0x9888), 0x0a4c8000 },
829 { _MMIO(0x9888), 0x0c4cc000 },
830 { _MMIO(0x9888), 0x144c8000 },
831 { _MMIO(0x9888), 0x164c2000 },
832 { _MMIO(0x9888), 0x004e2000 },
833 { _MMIO(0x9888), 0x064e8000 },
834 { _MMIO(0x9888), 0x084ea000 },
835 { _MMIO(0x9888), 0x0e4ea000 },
836 { _MMIO(0x9888), 0x1a4f4001 },
837 { _MMIO(0x9888), 0x1c4f5005 },
838 { _MMIO(0x9888), 0x006c0051 },
839 { _MMIO(0x9888), 0x066c5000 },
840 { _MMIO(0x9888), 0x086c5c5d },
841 { _MMIO(0x9888), 0x0e6c5e5f },
842 { _MMIO(0x9888), 0x106c0000 },
843 { _MMIO(0x9888), 0x146c0000 },
844 { _MMIO(0x9888), 0x1a6c0000 },
845 { _MMIO(0x9888), 0x1c6c0000 },
846 { _MMIO(0x9888), 0x180f1000 },
847 { _MMIO(0x9888), 0x1a0fa800 },
848 { _MMIO(0x9888), 0x1c0f0a00 },
849 { _MMIO(0x9888), 0x182c4000 },
850 { _MMIO(0x9888), 0x1c2c4015 },
851 { _MMIO(0x9888), 0x1e2c0001 },
852 { _MMIO(0x9888), 0x03931980 },
853 { _MMIO(0x9888), 0x05930032 },
854 { _MMIO(0x9888), 0x11930000 },
855 { _MMIO(0x9888), 0x01938000 },
856 { _MMIO(0x9888), 0x0f938000 },
857 { _MMIO(0x9888), 0x1993a00a },
858 { _MMIO(0x9888), 0x07930000 },
859 { _MMIO(0x9888), 0x09930000 },
860 { _MMIO(0x9888), 0x1d900177 },
861 { _MMIO(0x9888), 0x1f900178 },
862 { _MMIO(0x9888), 0x35900000 },
863 { _MMIO(0x9888), 0x13904000 },
864 { _MMIO(0x9888), 0x21904000 },
865 { _MMIO(0x9888), 0x23904000 },
866 { _MMIO(0x9888), 0x25904000 },
867 { _MMIO(0x9888), 0x2f904000 },
868 { _MMIO(0x9888), 0x31904000 },
869 { _MMIO(0x9888), 0x19904000 },
870 { _MMIO(0x9888), 0x1b904000 },
871 { _MMIO(0x9888), 0x53901000 },
872 { _MMIO(0x9888), 0x43900000 },
873 { _MMIO(0x9888), 0x55900111 },
874 { _MMIO(0x9888), 0x47900001 },
875 { _MMIO(0x9888), 0x57900000 },
876 { _MMIO(0x9888), 0x49900000 },
877 { _MMIO(0x9888), 0x37900000 },
878 { _MMIO(0x9888), 0x33900000 },
879 { _MMIO(0x9888), 0x59900000 },
880 { _MMIO(0x9888), 0x4b900000 },
881 { _MMIO(0x9888), 0x4d900000 },
882 { _MMIO(0x9888), 0x45900400 },
883};
884
885static int
886get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
887 const struct i915_oa_reg **regs,
888 int *lens)
889{
890 int n = 0;
891
892 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
893 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
894
895 regs[n] = mux_config_compute_l3_cache;
896 lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
897 n++;
898
899 return n;
900}
901
902static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
903 { _MMIO(0x2740), 0x00000000 },
904 { _MMIO(0x2744), 0x00800000 },
905 { _MMIO(0x2710), 0x00000000 },
906 { _MMIO(0x2714), 0x10800000 },
907 { _MMIO(0x2720), 0x00000000 },
908 { _MMIO(0x2724), 0x00800000 },
909 { _MMIO(0x2770), 0x00000002 },
910 { _MMIO(0x2774), 0x0000fdff },
911};
912
913static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
914 { _MMIO(0xe458), 0x00005004 },
915 { _MMIO(0xe558), 0x00010003 },
916 { _MMIO(0xe658), 0x00012011 },
917 { _MMIO(0xe758), 0x00015014 },
918 { _MMIO(0xe45c), 0x00051050 },
919 { _MMIO(0xe55c), 0x00053052 },
920 { _MMIO(0xe65c), 0x00055054 },
921};
922
923static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
924 { _MMIO(0x9888), 0x104f0232 },
925 { _MMIO(0x9888), 0x124f4640 },
926 { _MMIO(0x9888), 0x11834400 },
927 { _MMIO(0x9888), 0x022d4000 },
928 { _MMIO(0x9888), 0x042d5000 },
929 { _MMIO(0x9888), 0x062d1000 },
930 { _MMIO(0x9888), 0x0e2e0055 },
931 { _MMIO(0x9888), 0x064c8000 },
932 { _MMIO(0x9888), 0x084cc000 },
933 { _MMIO(0x9888), 0x0a4c4000 },
934 { _MMIO(0x9888), 0x024e8000 },
935 { _MMIO(0x9888), 0x044ea000 },
936 { _MMIO(0x9888), 0x064e2000 },
937 { _MMIO(0x9888), 0x024f6100 },
938 { _MMIO(0x9888), 0x044f416b },
939 { _MMIO(0x9888), 0x064f004b },
940 { _MMIO(0x9888), 0x1a4f0000 },
941 { _MMIO(0x9888), 0x1a0f02a8 },
942 { _MMIO(0x9888), 0x1a2c5500 },
943 { _MMIO(0x9888), 0x0f808000 },
944 { _MMIO(0x9888), 0x25810020 },
945 { _MMIO(0x9888), 0x0f8305c0 },
946 { _MMIO(0x9888), 0x07938000 },
947 { _MMIO(0x9888), 0x09938000 },
948 { _MMIO(0x9888), 0x0b938000 },
949 { _MMIO(0x9888), 0x0d938000 },
950 { _MMIO(0x9888), 0x1f951000 },
951 { _MMIO(0x9888), 0x13920200 },
952 { _MMIO(0x9888), 0x31908000 },
953 { _MMIO(0x9888), 0x19904000 },
954 { _MMIO(0x9888), 0x1b904000 },
955 { _MMIO(0x9888), 0x1d904000 },
956 { _MMIO(0x9888), 0x1f904000 },
957 { _MMIO(0x9888), 0x37900000 },
958 { _MMIO(0x9888), 0x59900000 },
959 { _MMIO(0x9888), 0x4d900003 },
960 { _MMIO(0x9888), 0x53900000 },
961 { _MMIO(0x9888), 0x45900000 },
962 { _MMIO(0x9888), 0x55900000 },
963 { _MMIO(0x9888), 0x47900000 },
964 { _MMIO(0x9888), 0x33900000 },
965};
966
967static int
968get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
969 const struct i915_oa_reg **regs,
970 int *lens)
971{
972 int n = 0;
973
974 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
975 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
976
977 regs[n] = mux_config_hdc_and_sf;
978 lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
979 n++;
980
981 return n;
982}
983
984static const struct i915_oa_reg b_counter_config_l3_1[] = {
985 { _MMIO(0x2740), 0x00000000 },
986 { _MMIO(0x2744), 0x00800000 },
987 { _MMIO(0x2710), 0x00000000 },
988 { _MMIO(0x2714), 0xf0800000 },
989 { _MMIO(0x2720), 0x00000000 },
990 { _MMIO(0x2724), 0xf0800000 },
991 { _MMIO(0x2770), 0x00100070 },
992 { _MMIO(0x2774), 0x0000fff1 },
993 { _MMIO(0x2778), 0x00014002 },
994 { _MMIO(0x277c), 0x0000c3ff },
995 { _MMIO(0x2780), 0x00010002 },
996 { _MMIO(0x2784), 0x0000c7ff },
997 { _MMIO(0x2788), 0x00004002 },
998 { _MMIO(0x278c), 0x0000d3ff },
999 { _MMIO(0x2790), 0x00100700 },
1000 { _MMIO(0x2794), 0x0000ff1f },
1001 { _MMIO(0x2798), 0x00001402 },
1002 { _MMIO(0x279c), 0x0000fc3f },
1003 { _MMIO(0x27a0), 0x00001002 },
1004 { _MMIO(0x27a4), 0x0000fc7f },
1005 { _MMIO(0x27a8), 0x00000402 },
1006 { _MMIO(0x27ac), 0x0000fd3f },
1007};
1008
1009static const struct i915_oa_reg flex_eu_config_l3_1[] = {
1010 { _MMIO(0xe458), 0x00005004 },
1011 { _MMIO(0xe558), 0x00010003 },
1012 { _MMIO(0xe658), 0x00012011 },
1013 { _MMIO(0xe758), 0x00015014 },
1014 { _MMIO(0xe45c), 0x00051050 },
1015 { _MMIO(0xe55c), 0x00053052 },
1016 { _MMIO(0xe65c), 0x00055054 },
1017};
1018
1019static const struct i915_oa_reg mux_config_l3_1[] = {
1020 { _MMIO(0x9888), 0x12643400 },
1021 { _MMIO(0x9888), 0x12653400 },
1022 { _MMIO(0x9888), 0x106c6800 },
1023 { _MMIO(0x9888), 0x126c001e },
1024 { _MMIO(0x9888), 0x166c0010 },
1025 { _MMIO(0x9888), 0x0c2d5000 },
1026 { _MMIO(0x9888), 0x0e2d5000 },
1027 { _MMIO(0x9888), 0x002d4000 },
1028 { _MMIO(0x9888), 0x022d5000 },
1029 { _MMIO(0x9888), 0x042d5000 },
1030 { _MMIO(0x9888), 0x062d1000 },
1031 { _MMIO(0x9888), 0x102e0154 },
1032 { _MMIO(0x9888), 0x0c2e5000 },
1033 { _MMIO(0x9888), 0x0e2e0055 },
1034 { _MMIO(0x9888), 0x104c8000 },
1035 { _MMIO(0x9888), 0x124c8000 },
1036 { _MMIO(0x9888), 0x144c8000 },
1037 { _MMIO(0x9888), 0x164c2000 },
1038 { _MMIO(0x9888), 0x044c8000 },
1039 { _MMIO(0x9888), 0x064cc000 },
1040 { _MMIO(0x9888), 0x084cc000 },
1041 { _MMIO(0x9888), 0x0a4c4000 },
1042 { _MMIO(0x9888), 0x0c4ea000 },
1043 { _MMIO(0x9888), 0x0e4ea000 },
1044 { _MMIO(0x9888), 0x004e8000 },
1045 { _MMIO(0x9888), 0x024ea000 },
1046 { _MMIO(0x9888), 0x044ea000 },
1047 { _MMIO(0x9888), 0x064e2000 },
1048 { _MMIO(0x9888), 0x1c4f5500 },
1049 { _MMIO(0x9888), 0x1a4f1554 },
1050 { _MMIO(0x9888), 0x0a640024 },
1051 { _MMIO(0x9888), 0x10640000 },
1052 { _MMIO(0x9888), 0x04640000 },
1053 { _MMIO(0x9888), 0x0c650024 },
1054 { _MMIO(0x9888), 0x10650000 },
1055 { _MMIO(0x9888), 0x06650000 },
1056 { _MMIO(0x9888), 0x0c6c5327 },
1057 { _MMIO(0x9888), 0x0e6c5425 },
1058 { _MMIO(0x9888), 0x006c2a00 },
1059 { _MMIO(0x9888), 0x026c285b },
1060 { _MMIO(0x9888), 0x046c005c },
1061 { _MMIO(0x9888), 0x1c6c0000 },
1062 { _MMIO(0x9888), 0x1a6c0900 },
1063 { _MMIO(0x9888), 0x1c0f0aa0 },
1064 { _MMIO(0x9888), 0x180f4000 },
1065 { _MMIO(0x9888), 0x1a0f02aa },
1066 { _MMIO(0x9888), 0x1c2c5400 },
1067 { _MMIO(0x9888), 0x1e2c0001 },
1068 { _MMIO(0x9888), 0x1a2c5550 },
1069 { _MMIO(0x9888), 0x1993aa00 },
1070 { _MMIO(0x9888), 0x03938000 },
1071 { _MMIO(0x9888), 0x05938000 },
1072 { _MMIO(0x9888), 0x07938000 },
1073 { _MMIO(0x9888), 0x09938000 },
1074 { _MMIO(0x9888), 0x0b938000 },
1075 { _MMIO(0x9888), 0x0d938000 },
1076 { _MMIO(0x9888), 0x2b904000 },
1077 { _MMIO(0x9888), 0x2d904000 },
1078 { _MMIO(0x9888), 0x2f904000 },
1079 { _MMIO(0x9888), 0x31904000 },
1080 { _MMIO(0x9888), 0x15904000 },
1081 { _MMIO(0x9888), 0x17904000 },
1082 { _MMIO(0x9888), 0x19904000 },
1083 { _MMIO(0x9888), 0x1b904000 },
1084 { _MMIO(0x9888), 0x1d904000 },
1085 { _MMIO(0x9888), 0x1f904000 },
1086 { _MMIO(0x9888), 0x59900000 },
1087 { _MMIO(0x9888), 0x4b900421 },
1088 { _MMIO(0x9888), 0x37900000 },
1089 { _MMIO(0x9888), 0x33900000 },
1090 { _MMIO(0x9888), 0x4d900001 },
1091 { _MMIO(0x9888), 0x53900000 },
1092 { _MMIO(0x9888), 0x43900420 },
1093 { _MMIO(0x9888), 0x45900021 },
1094 { _MMIO(0x9888), 0x55900000 },
1095 { _MMIO(0x9888), 0x47900000 },
1096};
1097
1098static int
1099get_l3_1_mux_config(struct drm_i915_private *dev_priv,
1100 const struct i915_oa_reg **regs,
1101 int *lens)
1102{
1103 int n = 0;
1104
1105 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1106 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1107
1108 regs[n] = mux_config_l3_1;
1109 lens[n] = ARRAY_SIZE(mux_config_l3_1);
1110 n++;
1111
1112 return n;
1113}
1114
1115static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
1116 { _MMIO(0x2740), 0x00000000 },
1117 { _MMIO(0x2744), 0x00800000 },
1118 { _MMIO(0x2710), 0x00000000 },
1119 { _MMIO(0x2714), 0x30800000 },
1120 { _MMIO(0x2720), 0x00000000 },
1121 { _MMIO(0x2724), 0x00800000 },
1122 { _MMIO(0x2770), 0x00000002 },
1123 { _MMIO(0x2774), 0x0000efff },
1124 { _MMIO(0x2778), 0x00006000 },
1125 { _MMIO(0x277c), 0x0000f3ff },
1126};
1127
1128static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
1129 { _MMIO(0xe458), 0x00005004 },
1130 { _MMIO(0xe558), 0x00010003 },
1131 { _MMIO(0xe658), 0x00012011 },
1132 { _MMIO(0xe758), 0x00015014 },
1133 { _MMIO(0xe45c), 0x00051050 },
1134 { _MMIO(0xe55c), 0x00053052 },
1135 { _MMIO(0xe65c), 0x00055054 },
1136};
1137
1138static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
1139 { _MMIO(0x9888), 0x102d7800 },
1140 { _MMIO(0x9888), 0x122d79e0 },
1141 { _MMIO(0x9888), 0x0c2f0004 },
1142 { _MMIO(0x9888), 0x100e3800 },
1143 { _MMIO(0x9888), 0x180f0005 },
1144 { _MMIO(0x9888), 0x002d0940 },
1145 { _MMIO(0x9888), 0x022d802f },
1146 { _MMIO(0x9888), 0x042d4013 },
1147 { _MMIO(0x9888), 0x062d1000 },
1148 { _MMIO(0x9888), 0x0e2e0050 },
1149 { _MMIO(0x9888), 0x022f0010 },
1150 { _MMIO(0x9888), 0x002f0000 },
1151 { _MMIO(0x9888), 0x084c8000 },
1152 { _MMIO(0x9888), 0x0a4c4000 },
1153 { _MMIO(0x9888), 0x044e8000 },
1154 { _MMIO(0x9888), 0x064e2000 },
1155 { _MMIO(0x9888), 0x040e0480 },
1156 { _MMIO(0x9888), 0x000e0000 },
1157 { _MMIO(0x9888), 0x060f0027 },
1158 { _MMIO(0x9888), 0x100f0000 },
1159 { _MMIO(0x9888), 0x1a0f0040 },
1160 { _MMIO(0x9888), 0x03938000 },
1161 { _MMIO(0x9888), 0x05938000 },
1162 { _MMIO(0x9888), 0x07938000 },
1163 { _MMIO(0x9888), 0x09938000 },
1164 { _MMIO(0x9888), 0x0b938000 },
1165 { _MMIO(0x9888), 0x0d938000 },
1166 { _MMIO(0x9888), 0x15904000 },
1167 { _MMIO(0x9888), 0x17904000 },
1168 { _MMIO(0x9888), 0x19904000 },
1169 { _MMIO(0x9888), 0x1b904000 },
1170 { _MMIO(0x9888), 0x1d904000 },
1171 { _MMIO(0x9888), 0x1f904000 },
1172 { _MMIO(0x9888), 0x37900000 },
1173 { _MMIO(0x9888), 0x53900000 },
1174 { _MMIO(0x9888), 0x439014a0 },
1175 { _MMIO(0x9888), 0x459000a4 },
1176 { _MMIO(0x9888), 0x55900000 },
1177 { _MMIO(0x9888), 0x47900001 },
1178 { _MMIO(0x9888), 0x33900000 },
1179};
1180
1181static int
1182get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
1183 const struct i915_oa_reg **regs,
1184 int *lens)
1185{
1186 int n = 0;
1187
1188 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1189 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1190
1191 regs[n] = mux_config_rasterizer_and_pixel_backend;
1192 lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
1193 n++;
1194
1195 return n;
1196}
1197
1198static const struct i915_oa_reg b_counter_config_sampler[] = {
1199 { _MMIO(0x2740), 0x00000000 },
1200 { _MMIO(0x2744), 0x00800000 },
1201 { _MMIO(0x2710), 0x00000000 },
1202 { _MMIO(0x2714), 0x70800000 },
1203 { _MMIO(0x2720), 0x00000000 },
1204 { _MMIO(0x2724), 0x00800000 },
1205 { _MMIO(0x2770), 0x0000c000 },
1206 { _MMIO(0x2774), 0x0000e7ff },
1207 { _MMIO(0x2778), 0x00003000 },
1208 { _MMIO(0x277c), 0x0000f9ff },
1209 { _MMIO(0x2780), 0x00000c00 },
1210 { _MMIO(0x2784), 0x0000fe7f },
1211};
1212
1213static const struct i915_oa_reg flex_eu_config_sampler[] = {
1214 { _MMIO(0xe458), 0x00005004 },
1215 { _MMIO(0xe558), 0x00010003 },
1216 { _MMIO(0xe658), 0x00012011 },
1217 { _MMIO(0xe758), 0x00015014 },
1218 { _MMIO(0xe45c), 0x00051050 },
1219 { _MMIO(0xe55c), 0x00053052 },
1220 { _MMIO(0xe65c), 0x00055054 },
1221};
1222
1223static const struct i915_oa_reg mux_config_sampler[] = {
1224 { _MMIO(0x9888), 0x121300a0 },
1225 { _MMIO(0x9888), 0x141600ab },
1226 { _MMIO(0x9888), 0x123300a0 },
1227 { _MMIO(0x9888), 0x143600ab },
1228 { _MMIO(0x9888), 0x125300a0 },
1229 { _MMIO(0x9888), 0x145600ab },
1230 { _MMIO(0x9888), 0x0c2d4000 },
1231 { _MMIO(0x9888), 0x0e2d5000 },
1232 { _MMIO(0x9888), 0x002d4000 },
1233 { _MMIO(0x9888), 0x022d5000 },
1234 { _MMIO(0x9888), 0x042d5000 },
1235 { _MMIO(0x9888), 0x062d1000 },
1236 { _MMIO(0x9888), 0x102e01a0 },
1237 { _MMIO(0x9888), 0x0c2e5000 },
1238 { _MMIO(0x9888), 0x0e2e0065 },
1239 { _MMIO(0x9888), 0x164c2000 },
1240 { _MMIO(0x9888), 0x044c8000 },
1241 { _MMIO(0x9888), 0x064cc000 },
1242 { _MMIO(0x9888), 0x084c4000 },
1243 { _MMIO(0x9888), 0x0a4c4000 },
1244 { _MMIO(0x9888), 0x0e4e8000 },
1245 { _MMIO(0x9888), 0x004e8000 },
1246 { _MMIO(0x9888), 0x024ea000 },
1247 { _MMIO(0x9888), 0x044e2000 },
1248 { _MMIO(0x9888), 0x064e2000 },
1249 { _MMIO(0x9888), 0x1c0f0800 },
1250 { _MMIO(0x9888), 0x180f4000 },
1251 { _MMIO(0x9888), 0x1a0f023f },
1252 { _MMIO(0x9888), 0x1e2c0003 },
1253 { _MMIO(0x9888), 0x1a2cc030 },
1254 { _MMIO(0x9888), 0x04132180 },
1255 { _MMIO(0x9888), 0x02130000 },
1256 { _MMIO(0x9888), 0x0c148000 },
1257 { _MMIO(0x9888), 0x0e142000 },
1258 { _MMIO(0x9888), 0x04148000 },
1259 { _MMIO(0x9888), 0x1e150140 },
1260 { _MMIO(0x9888), 0x1c150040 },
1261 { _MMIO(0x9888), 0x0c163000 },
1262 { _MMIO(0x9888), 0x0e160068 },
1263 { _MMIO(0x9888), 0x10160000 },
1264 { _MMIO(0x9888), 0x18160000 },
1265 { _MMIO(0x9888), 0x0a164000 },
1266 { _MMIO(0x9888), 0x04330043 },
1267 { _MMIO(0x9888), 0x02330000 },
1268 { _MMIO(0x9888), 0x0234a000 },
1269 { _MMIO(0x9888), 0x04342000 },
1270 { _MMIO(0x9888), 0x1c350015 },
1271 { _MMIO(0x9888), 0x02363460 },
1272 { _MMIO(0x9888), 0x10360000 },
1273 { _MMIO(0x9888), 0x04360000 },
1274 { _MMIO(0x9888), 0x06360000 },
1275 { _MMIO(0x9888), 0x08364000 },
1276 { _MMIO(0x9888), 0x06530043 },
1277 { _MMIO(0x9888), 0x02530000 },
1278 { _MMIO(0x9888), 0x0e548000 },
1279 { _MMIO(0x9888), 0x00548000 },
1280 { _MMIO(0x9888), 0x06542000 },
1281 { _MMIO(0x9888), 0x1e550400 },
1282 { _MMIO(0x9888), 0x1a552000 },
1283 { _MMIO(0x9888), 0x1c550100 },
1284 { _MMIO(0x9888), 0x0e563000 },
1285 { _MMIO(0x9888), 0x00563400 },
1286 { _MMIO(0x9888), 0x10560000 },
1287 { _MMIO(0x9888), 0x18560000 },
1288 { _MMIO(0x9888), 0x02560000 },
1289 { _MMIO(0x9888), 0x0c564000 },
1290 { _MMIO(0x9888), 0x1993a800 },
1291 { _MMIO(0x9888), 0x03938000 },
1292 { _MMIO(0x9888), 0x05938000 },
1293 { _MMIO(0x9888), 0x07938000 },
1294 { _MMIO(0x9888), 0x09938000 },
1295 { _MMIO(0x9888), 0x0b938000 },
1296 { _MMIO(0x9888), 0x0d938000 },
1297 { _MMIO(0x9888), 0x2d904000 },
1298 { _MMIO(0x9888), 0x2f904000 },
1299 { _MMIO(0x9888), 0x31904000 },
1300 { _MMIO(0x9888), 0x15904000 },
1301 { _MMIO(0x9888), 0x17904000 },
1302 { _MMIO(0x9888), 0x19904000 },
1303 { _MMIO(0x9888), 0x1b904000 },
1304 { _MMIO(0x9888), 0x1d904000 },
1305 { _MMIO(0x9888), 0x1f904000 },
1306 { _MMIO(0x9888), 0x59900000 },
1307 { _MMIO(0x9888), 0x4b9014a0 },
1308 { _MMIO(0x9888), 0x37900000 },
1309 { _MMIO(0x9888), 0x33900000 },
1310 { _MMIO(0x9888), 0x4d900001 },
1311 { _MMIO(0x9888), 0x53900000 },
1312 { _MMIO(0x9888), 0x43900820 },
1313 { _MMIO(0x9888), 0x45901022 },
1314 { _MMIO(0x9888), 0x55900000 },
1315 { _MMIO(0x9888), 0x47900000 },
1316};
1317
1318static int
1319get_sampler_mux_config(struct drm_i915_private *dev_priv,
1320 const struct i915_oa_reg **regs,
1321 int *lens)
1322{
1323 int n = 0;
1324
1325 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1326 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1327
1328 regs[n] = mux_config_sampler;
1329 lens[n] = ARRAY_SIZE(mux_config_sampler);
1330 n++;
1331
1332 return n;
1333}
1334
1335static const struct i915_oa_reg b_counter_config_tdl_1[] = {
1336 { _MMIO(0x2740), 0x00000000 },
1337 { _MMIO(0x2744), 0x00800000 },
1338 { _MMIO(0x2710), 0x00000000 },
1339 { _MMIO(0x2714), 0xf0800000 },
1340 { _MMIO(0x2720), 0x00000000 },
1341 { _MMIO(0x2724), 0x30800000 },
1342 { _MMIO(0x2770), 0x00000002 },
1343 { _MMIO(0x2774), 0x00007fff },
1344 { _MMIO(0x2778), 0x00000000 },
1345 { _MMIO(0x277c), 0x00009fff },
1346 { _MMIO(0x2780), 0x00000002 },
1347 { _MMIO(0x2784), 0x0000efff },
1348 { _MMIO(0x2788), 0x00000000 },
1349 { _MMIO(0x278c), 0x0000f3ff },
1350 { _MMIO(0x2790), 0x00000002 },
1351 { _MMIO(0x2794), 0x0000fdff },
1352 { _MMIO(0x2798), 0x00000000 },
1353 { _MMIO(0x279c), 0x0000fe7f },
1354};
1355
1356static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
1357 { _MMIO(0xe458), 0x00005004 },
1358 { _MMIO(0xe558), 0x00010003 },
1359 { _MMIO(0xe658), 0x00012011 },
1360 { _MMIO(0xe758), 0x00015014 },
1361 { _MMIO(0xe45c), 0x00051050 },
1362 { _MMIO(0xe55c), 0x00053052 },
1363 { _MMIO(0xe65c), 0x00055054 },
1364};
1365
1366static const struct i915_oa_reg mux_config_tdl_1[] = {
1367 { _MMIO(0x9888), 0x141a0000 },
1368 { _MMIO(0x9888), 0x143a0000 },
1369 { _MMIO(0x9888), 0x145a0000 },
1370 { _MMIO(0x9888), 0x0c2d4000 },
1371 { _MMIO(0x9888), 0x0e2d5000 },
1372 { _MMIO(0x9888), 0x002d4000 },
1373 { _MMIO(0x9888), 0x022d5000 },
1374 { _MMIO(0x9888), 0x042d5000 },
1375 { _MMIO(0x9888), 0x062d1000 },
1376 { _MMIO(0x9888), 0x102e0150 },
1377 { _MMIO(0x9888), 0x0c2e5000 },
1378 { _MMIO(0x9888), 0x0e2e006a },
1379 { _MMIO(0x9888), 0x124c8000 },
1380 { _MMIO(0x9888), 0x144c8000 },
1381 { _MMIO(0x9888), 0x164c2000 },
1382 { _MMIO(0x9888), 0x044c8000 },
1383 { _MMIO(0x9888), 0x064c4000 },
1384 { _MMIO(0x9888), 0x0a4c4000 },
1385 { _MMIO(0x9888), 0x0c4e8000 },
1386 { _MMIO(0x9888), 0x0e4ea000 },
1387 { _MMIO(0x9888), 0x004e8000 },
1388 { _MMIO(0x9888), 0x024e2000 },
1389 { _MMIO(0x9888), 0x064e2000 },
1390 { _MMIO(0x9888), 0x1c0f0bc0 },
1391 { _MMIO(0x9888), 0x180f4000 },
1392 { _MMIO(0x9888), 0x1a0f0302 },
1393 { _MMIO(0x9888), 0x1e2c0003 },
1394 { _MMIO(0x9888), 0x1a2c00f0 },
1395 { _MMIO(0x9888), 0x021a3080 },
1396 { _MMIO(0x9888), 0x041a31e5 },
1397 { _MMIO(0x9888), 0x02148000 },
1398 { _MMIO(0x9888), 0x0414a000 },
1399 { _MMIO(0x9888), 0x1c150054 },
1400 { _MMIO(0x9888), 0x06168000 },
1401 { _MMIO(0x9888), 0x08168000 },
1402 { _MMIO(0x9888), 0x0a168000 },
1403 { _MMIO(0x9888), 0x0c3a3280 },
1404 { _MMIO(0x9888), 0x0e3a0063 },
1405 { _MMIO(0x9888), 0x063a0061 },
1406 { _MMIO(0x9888), 0x023a0000 },
1407 { _MMIO(0x9888), 0x0c348000 },
1408 { _MMIO(0x9888), 0x0e342000 },
1409 { _MMIO(0x9888), 0x06342000 },
1410 { _MMIO(0x9888), 0x1e350140 },
1411 { _MMIO(0x9888), 0x1c350100 },
1412 { _MMIO(0x9888), 0x18360028 },
1413 { _MMIO(0x9888), 0x0c368000 },
1414 { _MMIO(0x9888), 0x0e5a3080 },
1415 { _MMIO(0x9888), 0x005a3280 },
1416 { _MMIO(0x9888), 0x025a0063 },
1417 { _MMIO(0x9888), 0x0e548000 },
1418 { _MMIO(0x9888), 0x00548000 },
1419 { _MMIO(0x9888), 0x02542000 },
1420 { _MMIO(0x9888), 0x1e550400 },
1421 { _MMIO(0x9888), 0x1a552000 },
1422 { _MMIO(0x9888), 0x1c550001 },
1423 { _MMIO(0x9888), 0x18560080 },
1424 { _MMIO(0x9888), 0x02568000 },
1425 { _MMIO(0x9888), 0x04568000 },
1426 { _MMIO(0x9888), 0x1993a800 },
1427 { _MMIO(0x9888), 0x03938000 },
1428 { _MMIO(0x9888), 0x05938000 },
1429 { _MMIO(0x9888), 0x07938000 },
1430 { _MMIO(0x9888), 0x09938000 },
1431 { _MMIO(0x9888), 0x0b938000 },
1432 { _MMIO(0x9888), 0x0d938000 },
1433 { _MMIO(0x9888), 0x2d904000 },
1434 { _MMIO(0x9888), 0x2f904000 },
1435 { _MMIO(0x9888), 0x31904000 },
1436 { _MMIO(0x9888), 0x15904000 },
1437 { _MMIO(0x9888), 0x17904000 },
1438 { _MMIO(0x9888), 0x19904000 },
1439 { _MMIO(0x9888), 0x1b904000 },
1440 { _MMIO(0x9888), 0x1d904000 },
1441 { _MMIO(0x9888), 0x1f904000 },
1442 { _MMIO(0x9888), 0x59900000 },
1443 { _MMIO(0x9888), 0x4b900420 },
1444 { _MMIO(0x9888), 0x37900000 },
1445 { _MMIO(0x9888), 0x33900000 },
1446 { _MMIO(0x9888), 0x4d900000 },
1447 { _MMIO(0x9888), 0x53900000 },
1448 { _MMIO(0x9888), 0x43900000 },
1449 { _MMIO(0x9888), 0x45901084 },
1450 { _MMIO(0x9888), 0x55900000 },
1451 { _MMIO(0x9888), 0x47900001 },
1452};
1453
1454static int
1455get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
1456 const struct i915_oa_reg **regs,
1457 int *lens)
1458{
1459 int n = 0;
1460
1461 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1462 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1463
1464 regs[n] = mux_config_tdl_1;
1465 lens[n] = ARRAY_SIZE(mux_config_tdl_1);
1466 n++;
1467
1468 return n;
1469}
1470
1471static const struct i915_oa_reg b_counter_config_tdl_2[] = {
1472 { _MMIO(0x2740), 0x00000000 },
1473 { _MMIO(0x2744), 0x00800000 },
1474 { _MMIO(0x2710), 0x00000000 },
1475 { _MMIO(0x2714), 0x00800000 },
1476 { _MMIO(0x2720), 0x00000000 },
1477 { _MMIO(0x2724), 0x00800000 },
1478};
1479
1480static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
1481 { _MMIO(0xe458), 0x00005004 },
1482 { _MMIO(0xe558), 0x00010003 },
1483 { _MMIO(0xe658), 0x00012011 },
1484 { _MMIO(0xe758), 0x00015014 },
1485 { _MMIO(0xe45c), 0x00051050 },
1486 { _MMIO(0xe55c), 0x00053052 },
1487 { _MMIO(0xe65c), 0x00055054 },
1488};
1489
1490static const struct i915_oa_reg mux_config_tdl_2[] = {
1491 { _MMIO(0x9888), 0x141a026b },
1492 { _MMIO(0x9888), 0x143a0173 },
1493 { _MMIO(0x9888), 0x145a026b },
1494 { _MMIO(0x9888), 0x002d4000 },
1495 { _MMIO(0x9888), 0x022d5000 },
1496 { _MMIO(0x9888), 0x042d5000 },
1497 { _MMIO(0x9888), 0x062d1000 },
1498 { _MMIO(0x9888), 0x0c2e5000 },
1499 { _MMIO(0x9888), 0x0e2e0069 },
1500 { _MMIO(0x9888), 0x044c8000 },
1501 { _MMIO(0x9888), 0x064cc000 },
1502 { _MMIO(0x9888), 0x0a4c4000 },
1503 { _MMIO(0x9888), 0x004e8000 },
1504 { _MMIO(0x9888), 0x024ea000 },
1505 { _MMIO(0x9888), 0x064e2000 },
1506 { _MMIO(0x9888), 0x180f6000 },
1507 { _MMIO(0x9888), 0x1a0f030a },
1508 { _MMIO(0x9888), 0x1a2c03c0 },
1509 { _MMIO(0x9888), 0x041a37e7 },
1510 { _MMIO(0x9888), 0x021a0000 },
1511 { _MMIO(0x9888), 0x0414a000 },
1512 { _MMIO(0x9888), 0x1c150050 },
1513 { _MMIO(0x9888), 0x08168000 },
1514 { _MMIO(0x9888), 0x0a168000 },
1515 { _MMIO(0x9888), 0x003a3380 },
1516 { _MMIO(0x9888), 0x063a006f },
1517 { _MMIO(0x9888), 0x023a0000 },
1518 { _MMIO(0x9888), 0x00348000 },
1519 { _MMIO(0x9888), 0x06342000 },
1520 { _MMIO(0x9888), 0x1a352000 },
1521 { _MMIO(0x9888), 0x1c350100 },
1522 { _MMIO(0x9888), 0x02368000 },
1523 { _MMIO(0x9888), 0x0c368000 },
1524 { _MMIO(0x9888), 0x025a37e7 },
1525 { _MMIO(0x9888), 0x0254a000 },
1526 { _MMIO(0x9888), 0x1c550005 },
1527 { _MMIO(0x9888), 0x04568000 },
1528 { _MMIO(0x9888), 0x06568000 },
1529 { _MMIO(0x9888), 0x03938000 },
1530 { _MMIO(0x9888), 0x05938000 },
1531 { _MMIO(0x9888), 0x07938000 },
1532 { _MMIO(0x9888), 0x09938000 },
1533 { _MMIO(0x9888), 0x0b938000 },
1534 { _MMIO(0x9888), 0x0d938000 },
1535 { _MMIO(0x9888), 0x15904000 },
1536 { _MMIO(0x9888), 0x17904000 },
1537 { _MMIO(0x9888), 0x19904000 },
1538 { _MMIO(0x9888), 0x1b904000 },
1539 { _MMIO(0x9888), 0x1d904000 },
1540 { _MMIO(0x9888), 0x1f904000 },
1541 { _MMIO(0x9888), 0x37900000 },
1542 { _MMIO(0x9888), 0x53900000 },
1543 { _MMIO(0x9888), 0x43900020 },
1544 { _MMIO(0x9888), 0x45901080 },
1545 { _MMIO(0x9888), 0x55900000 },
1546 { _MMIO(0x9888), 0x47900001 },
1547 { _MMIO(0x9888), 0x33900000 },
1548};
1549
1550static int
1551get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
1552 const struct i915_oa_reg **regs,
1553 int *lens)
1554{
1555 int n = 0;
1556
1557 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1558 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1559
1560 regs[n] = mux_config_tdl_2;
1561 lens[n] = ARRAY_SIZE(mux_config_tdl_2);
1562 n++;
1563
1564 return n;
1565}
1566
1567static const struct i915_oa_reg b_counter_config_compute_extra[] = {
1568 { _MMIO(0x2740), 0x00000000 },
1569 { _MMIO(0x2744), 0x00800000 },
1570 { _MMIO(0x2710), 0x00000000 },
1571 { _MMIO(0x2714), 0x00800000 },
1572 { _MMIO(0x2720), 0x00000000 },
1573 { _MMIO(0x2724), 0x00800000 },
1574};
1575
1576static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
1577 { _MMIO(0xe458), 0x00001000 },
1578 { _MMIO(0xe558), 0x00003002 },
1579 { _MMIO(0xe658), 0x00005004 },
1580 { _MMIO(0xe758), 0x00011010 },
1581 { _MMIO(0xe45c), 0x00050012 },
1582 { _MMIO(0xe55c), 0x00052051 },
1583 { _MMIO(0xe65c), 0x00000008 },
1584};
1585
1586static const struct i915_oa_reg mux_config_compute_extra[] = {
1587 { _MMIO(0x9888), 0x141a001f },
1588 { _MMIO(0x9888), 0x143a001f },
1589 { _MMIO(0x9888), 0x145a001f },
1590 { _MMIO(0x9888), 0x042d5000 },
1591 { _MMIO(0x9888), 0x062d1000 },
1592 { _MMIO(0x9888), 0x0e2e0094 },
1593 { _MMIO(0x9888), 0x084cc000 },
1594 { _MMIO(0x9888), 0x044ea000 },
1595 { _MMIO(0x9888), 0x1a0f00e0 },
1596 { _MMIO(0x9888), 0x1a2c0c00 },
1597 { _MMIO(0x9888), 0x061a0063 },
1598 { _MMIO(0x9888), 0x021a0000 },
1599 { _MMIO(0x9888), 0x06142000 },
1600 { _MMIO(0x9888), 0x1c150100 },
1601 { _MMIO(0x9888), 0x0c168000 },
1602 { _MMIO(0x9888), 0x043a3180 },
1603 { _MMIO(0x9888), 0x023a0000 },
1604 { _MMIO(0x9888), 0x04348000 },
1605 { _MMIO(0x9888), 0x1c350040 },
1606 { _MMIO(0x9888), 0x0a368000 },
1607 { _MMIO(0x9888), 0x045a0063 },
1608 { _MMIO(0x9888), 0x025a0000 },
1609 { _MMIO(0x9888), 0x04542000 },
1610 { _MMIO(0x9888), 0x1c550010 },
1611 { _MMIO(0x9888), 0x08568000 },
1612 { _MMIO(0x9888), 0x09938000 },
1613 { _MMIO(0x9888), 0x0b938000 },
1614 { _MMIO(0x9888), 0x0d938000 },
1615 { _MMIO(0x9888), 0x1b904000 },
1616 { _MMIO(0x9888), 0x1d904000 },
1617 { _MMIO(0x9888), 0x1f904000 },
1618 { _MMIO(0x9888), 0x37900000 },
1619 { _MMIO(0x9888), 0x55900000 },
1620 { _MMIO(0x9888), 0x45900400 },
1621 { _MMIO(0x9888), 0x47900004 },
1622 { _MMIO(0x9888), 0x33900000 },
1623};
1624
1625static int
1626get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
1627 const struct i915_oa_reg **regs,
1628 int *lens)
1629{
1630 int n = 0;
1631
1632 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1633 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1634
1635 regs[n] = mux_config_compute_extra;
1636 lens[n] = ARRAY_SIZE(mux_config_compute_extra);
1637 n++;
1638
1639 return n;
1640}
1641
1642static const struct i915_oa_reg b_counter_config_test_oa[] = {
1643 { _MMIO(0x2740), 0x00000000 },
1644 { _MMIO(0x2744), 0x00800000 },
1645 { _MMIO(0x2714), 0xf0800000 },
1646 { _MMIO(0x2710), 0x00000000 },
1647 { _MMIO(0x2724), 0xf0800000 },
1648 { _MMIO(0x2720), 0x00000000 },
1649 { _MMIO(0x2770), 0x00000004 },
1650 { _MMIO(0x2774), 0x00000000 },
1651 { _MMIO(0x2778), 0x00000003 },
1652 { _MMIO(0x277c), 0x00000000 },
1653 { _MMIO(0x2780), 0x00000007 },
1654 { _MMIO(0x2784), 0x00000000 },
1655 { _MMIO(0x2788), 0x00100002 },
1656 { _MMIO(0x278c), 0x0000fff7 },
1657 { _MMIO(0x2790), 0x00100002 },
1658 { _MMIO(0x2794), 0x0000ffcf },
1659 { _MMIO(0x2798), 0x00100082 },
1660 { _MMIO(0x279c), 0x0000ffef },
1661 { _MMIO(0x27a0), 0x001000c2 },
1662 { _MMIO(0x27a4), 0x0000ffe7 },
1663 { _MMIO(0x27a8), 0x00100001 },
1664 { _MMIO(0x27ac), 0x0000ffe7 },
1665};
1666
1667static const struct i915_oa_reg flex_eu_config_test_oa[] = {
1668};
1669
1670static const struct i915_oa_reg mux_config_test_oa[] = {
1671 { _MMIO(0x9888), 0x19800000 },
1672 { _MMIO(0x9888), 0x07800063 },
1673 { _MMIO(0x9888), 0x11800000 },
1674 { _MMIO(0x9888), 0x23810008 },
1675 { _MMIO(0x9888), 0x1d950400 },
1676 { _MMIO(0x9888), 0x0f922000 },
1677 { _MMIO(0x9888), 0x1f908000 },
1678 { _MMIO(0x9888), 0x37900000 },
1679 { _MMIO(0x9888), 0x55900000 },
1680 { _MMIO(0x9888), 0x47900000 },
1681 { _MMIO(0x9888), 0x33900000 },
1682};
1683
1684static int
1685get_test_oa_mux_config(struct drm_i915_private *dev_priv,
1686 const struct i915_oa_reg **regs,
1687 int *lens)
1688{
1689 int n = 0;
1690
1691 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
1692 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
1693
1694 regs[n] = mux_config_test_oa;
1695 lens[n] = ARRAY_SIZE(mux_config_test_oa);
1696 n++;
1697
1698 return n;
1699}
1700
1701int i915_oa_select_metric_set_glk(struct drm_i915_private *dev_priv)
1702{
1703 dev_priv->perf.oa.n_mux_configs = 0;
1704 dev_priv->perf.oa.b_counter_regs = NULL;
1705 dev_priv->perf.oa.b_counter_regs_len = 0;
1706 dev_priv->perf.oa.flex_regs = NULL;
1707 dev_priv->perf.oa.flex_regs_len = 0;
1708
1709 switch (dev_priv->perf.oa.metrics_set) {
1710 case METRIC_SET_ID_RENDER_BASIC:
1711 dev_priv->perf.oa.n_mux_configs =
1712 get_render_basic_mux_config(dev_priv,
1713 dev_priv->perf.oa.mux_regs,
1714 dev_priv->perf.oa.mux_regs_lens);
1715 if (dev_priv->perf.oa.n_mux_configs == 0) {
1716 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
1717
1718 /* EINVAL because *_register_sysfs already checked this
1719 * and so it wouldn't have been advertised to userspace and
1720 * so shouldn't have been requested
1721 */
1722 return -EINVAL;
1723 }
1724
1725 dev_priv->perf.oa.b_counter_regs =
1726 b_counter_config_render_basic;
1727 dev_priv->perf.oa.b_counter_regs_len =
1728 ARRAY_SIZE(b_counter_config_render_basic);
1729
1730 dev_priv->perf.oa.flex_regs =
1731 flex_eu_config_render_basic;
1732 dev_priv->perf.oa.flex_regs_len =
1733 ARRAY_SIZE(flex_eu_config_render_basic);
1734
1735 return 0;
1736 case METRIC_SET_ID_COMPUTE_BASIC:
1737 dev_priv->perf.oa.n_mux_configs =
1738 get_compute_basic_mux_config(dev_priv,
1739 dev_priv->perf.oa.mux_regs,
1740 dev_priv->perf.oa.mux_regs_lens);
1741 if (dev_priv->perf.oa.n_mux_configs == 0) {
1742 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
1743
1744 /* EINVAL because *_register_sysfs already checked this
1745 * and so it wouldn't have been advertised to userspace and
1746 * so shouldn't have been requested
1747 */
1748 return -EINVAL;
1749 }
1750
1751 dev_priv->perf.oa.b_counter_regs =
1752 b_counter_config_compute_basic;
1753 dev_priv->perf.oa.b_counter_regs_len =
1754 ARRAY_SIZE(b_counter_config_compute_basic);
1755
1756 dev_priv->perf.oa.flex_regs =
1757 flex_eu_config_compute_basic;
1758 dev_priv->perf.oa.flex_regs_len =
1759 ARRAY_SIZE(flex_eu_config_compute_basic);
1760
1761 return 0;
1762 case METRIC_SET_ID_RENDER_PIPE_PROFILE:
1763 dev_priv->perf.oa.n_mux_configs =
1764 get_render_pipe_profile_mux_config(dev_priv,
1765 dev_priv->perf.oa.mux_regs,
1766 dev_priv->perf.oa.mux_regs_lens);
1767 if (dev_priv->perf.oa.n_mux_configs == 0) {
1768 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
1769
1770 /* EINVAL because *_register_sysfs already checked this
1771 * and so it wouldn't have been advertised to userspace and
1772 * so shouldn't have been requested
1773 */
1774 return -EINVAL;
1775 }
1776
1777 dev_priv->perf.oa.b_counter_regs =
1778 b_counter_config_render_pipe_profile;
1779 dev_priv->perf.oa.b_counter_regs_len =
1780 ARRAY_SIZE(b_counter_config_render_pipe_profile);
1781
1782 dev_priv->perf.oa.flex_regs =
1783 flex_eu_config_render_pipe_profile;
1784 dev_priv->perf.oa.flex_regs_len =
1785 ARRAY_SIZE(flex_eu_config_render_pipe_profile);
1786
1787 return 0;
1788 case METRIC_SET_ID_MEMORY_READS:
1789 dev_priv->perf.oa.n_mux_configs =
1790 get_memory_reads_mux_config(dev_priv,
1791 dev_priv->perf.oa.mux_regs,
1792 dev_priv->perf.oa.mux_regs_lens);
1793 if (dev_priv->perf.oa.n_mux_configs == 0) {
1794 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
1795
1796 /* EINVAL because *_register_sysfs already checked this
1797 * and so it wouldn't have been advertised to userspace and
1798 * so shouldn't have been requested
1799 */
1800 return -EINVAL;
1801 }
1802
1803 dev_priv->perf.oa.b_counter_regs =
1804 b_counter_config_memory_reads;
1805 dev_priv->perf.oa.b_counter_regs_len =
1806 ARRAY_SIZE(b_counter_config_memory_reads);
1807
1808 dev_priv->perf.oa.flex_regs =
1809 flex_eu_config_memory_reads;
1810 dev_priv->perf.oa.flex_regs_len =
1811 ARRAY_SIZE(flex_eu_config_memory_reads);
1812
1813 return 0;
1814 case METRIC_SET_ID_MEMORY_WRITES:
1815 dev_priv->perf.oa.n_mux_configs =
1816 get_memory_writes_mux_config(dev_priv,
1817 dev_priv->perf.oa.mux_regs,
1818 dev_priv->perf.oa.mux_regs_lens);
1819 if (dev_priv->perf.oa.n_mux_configs == 0) {
1820 DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
1821
1822 /* EINVAL because *_register_sysfs already checked this
1823 * and so it wouldn't have been advertised to userspace and
1824 * so shouldn't have been requested
1825 */
1826 return -EINVAL;
1827 }
1828
1829 dev_priv->perf.oa.b_counter_regs =
1830 b_counter_config_memory_writes;
1831 dev_priv->perf.oa.b_counter_regs_len =
1832 ARRAY_SIZE(b_counter_config_memory_writes);
1833
1834 dev_priv->perf.oa.flex_regs =
1835 flex_eu_config_memory_writes;
1836 dev_priv->perf.oa.flex_regs_len =
1837 ARRAY_SIZE(flex_eu_config_memory_writes);
1838
1839 return 0;
1840 case METRIC_SET_ID_COMPUTE_EXTENDED:
1841 dev_priv->perf.oa.n_mux_configs =
1842 get_compute_extended_mux_config(dev_priv,
1843 dev_priv->perf.oa.mux_regs,
1844 dev_priv->perf.oa.mux_regs_lens);
1845 if (dev_priv->perf.oa.n_mux_configs == 0) {
1846 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
1847
1848 /* EINVAL because *_register_sysfs already checked this
1849 * and so it wouldn't have been advertised to userspace and
1850 * so shouldn't have been requested
1851 */
1852 return -EINVAL;
1853 }
1854
1855 dev_priv->perf.oa.b_counter_regs =
1856 b_counter_config_compute_extended;
1857 dev_priv->perf.oa.b_counter_regs_len =
1858 ARRAY_SIZE(b_counter_config_compute_extended);
1859
1860 dev_priv->perf.oa.flex_regs =
1861 flex_eu_config_compute_extended;
1862 dev_priv->perf.oa.flex_regs_len =
1863 ARRAY_SIZE(flex_eu_config_compute_extended);
1864
1865 return 0;
1866 case METRIC_SET_ID_COMPUTE_L3_CACHE:
1867 dev_priv->perf.oa.n_mux_configs =
1868 get_compute_l3_cache_mux_config(dev_priv,
1869 dev_priv->perf.oa.mux_regs,
1870 dev_priv->perf.oa.mux_regs_lens);
1871 if (dev_priv->perf.oa.n_mux_configs == 0) {
1872 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
1873
1874 /* EINVAL because *_register_sysfs already checked this
1875 * and so it wouldn't have been advertised to userspace and
1876 * so shouldn't have been requested
1877 */
1878 return -EINVAL;
1879 }
1880
1881 dev_priv->perf.oa.b_counter_regs =
1882 b_counter_config_compute_l3_cache;
1883 dev_priv->perf.oa.b_counter_regs_len =
1884 ARRAY_SIZE(b_counter_config_compute_l3_cache);
1885
1886 dev_priv->perf.oa.flex_regs =
1887 flex_eu_config_compute_l3_cache;
1888 dev_priv->perf.oa.flex_regs_len =
1889 ARRAY_SIZE(flex_eu_config_compute_l3_cache);
1890
1891 return 0;
1892 case METRIC_SET_ID_HDC_AND_SF:
1893 dev_priv->perf.oa.n_mux_configs =
1894 get_hdc_and_sf_mux_config(dev_priv,
1895 dev_priv->perf.oa.mux_regs,
1896 dev_priv->perf.oa.mux_regs_lens);
1897 if (dev_priv->perf.oa.n_mux_configs == 0) {
1898 DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
1899
1900 /* EINVAL because *_register_sysfs already checked this
1901 * and so it wouldn't have been advertised to userspace and
1902 * so shouldn't have been requested
1903 */
1904 return -EINVAL;
1905 }
1906
1907 dev_priv->perf.oa.b_counter_regs =
1908 b_counter_config_hdc_and_sf;
1909 dev_priv->perf.oa.b_counter_regs_len =
1910 ARRAY_SIZE(b_counter_config_hdc_and_sf);
1911
1912 dev_priv->perf.oa.flex_regs =
1913 flex_eu_config_hdc_and_sf;
1914 dev_priv->perf.oa.flex_regs_len =
1915 ARRAY_SIZE(flex_eu_config_hdc_and_sf);
1916
1917 return 0;
1918 case METRIC_SET_ID_L3_1:
1919 dev_priv->perf.oa.n_mux_configs =
1920 get_l3_1_mux_config(dev_priv,
1921 dev_priv->perf.oa.mux_regs,
1922 dev_priv->perf.oa.mux_regs_lens);
1923 if (dev_priv->perf.oa.n_mux_configs == 0) {
1924 DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
1925
1926 /* EINVAL because *_register_sysfs already checked this
1927 * and so it wouldn't have been advertised to userspace and
1928 * so shouldn't have been requested
1929 */
1930 return -EINVAL;
1931 }
1932
1933 dev_priv->perf.oa.b_counter_regs =
1934 b_counter_config_l3_1;
1935 dev_priv->perf.oa.b_counter_regs_len =
1936 ARRAY_SIZE(b_counter_config_l3_1);
1937
1938 dev_priv->perf.oa.flex_regs =
1939 flex_eu_config_l3_1;
1940 dev_priv->perf.oa.flex_regs_len =
1941 ARRAY_SIZE(flex_eu_config_l3_1);
1942
1943 return 0;
1944 case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
1945 dev_priv->perf.oa.n_mux_configs =
1946 get_rasterizer_and_pixel_backend_mux_config(dev_priv,
1947 dev_priv->perf.oa.mux_regs,
1948 dev_priv->perf.oa.mux_regs_lens);
1949 if (dev_priv->perf.oa.n_mux_configs == 0) {
1950 DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
1951
1952 /* EINVAL because *_register_sysfs already checked this
1953 * and so it wouldn't have been advertised to userspace and
1954 * so shouldn't have been requested
1955 */
1956 return -EINVAL;
1957 }
1958
1959 dev_priv->perf.oa.b_counter_regs =
1960 b_counter_config_rasterizer_and_pixel_backend;
1961 dev_priv->perf.oa.b_counter_regs_len =
1962 ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
1963
1964 dev_priv->perf.oa.flex_regs =
1965 flex_eu_config_rasterizer_and_pixel_backend;
1966 dev_priv->perf.oa.flex_regs_len =
1967 ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
1968
1969 return 0;
1970 case METRIC_SET_ID_SAMPLER:
1971 dev_priv->perf.oa.n_mux_configs =
1972 get_sampler_mux_config(dev_priv,
1973 dev_priv->perf.oa.mux_regs,
1974 dev_priv->perf.oa.mux_regs_lens);
1975 if (dev_priv->perf.oa.n_mux_configs == 0) {
1976 DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
1977
1978 /* EINVAL because *_register_sysfs already checked this
1979 * and so it wouldn't have been advertised to userspace and
1980 * so shouldn't have been requested
1981 */
1982 return -EINVAL;
1983 }
1984
1985 dev_priv->perf.oa.b_counter_regs =
1986 b_counter_config_sampler;
1987 dev_priv->perf.oa.b_counter_regs_len =
1988 ARRAY_SIZE(b_counter_config_sampler);
1989
1990 dev_priv->perf.oa.flex_regs =
1991 flex_eu_config_sampler;
1992 dev_priv->perf.oa.flex_regs_len =
1993 ARRAY_SIZE(flex_eu_config_sampler);
1994
1995 return 0;
1996 case METRIC_SET_ID_TDL_1:
1997 dev_priv->perf.oa.n_mux_configs =
1998 get_tdl_1_mux_config(dev_priv,
1999 dev_priv->perf.oa.mux_regs,
2000 dev_priv->perf.oa.mux_regs_lens);
2001 if (dev_priv->perf.oa.n_mux_configs == 0) {
2002 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
2003
2004 /* EINVAL because *_register_sysfs already checked this
2005 * and so it wouldn't have been advertised to userspace and
2006 * so shouldn't have been requested
2007 */
2008 return -EINVAL;
2009 }
2010
2011 dev_priv->perf.oa.b_counter_regs =
2012 b_counter_config_tdl_1;
2013 dev_priv->perf.oa.b_counter_regs_len =
2014 ARRAY_SIZE(b_counter_config_tdl_1);
2015
2016 dev_priv->perf.oa.flex_regs =
2017 flex_eu_config_tdl_1;
2018 dev_priv->perf.oa.flex_regs_len =
2019 ARRAY_SIZE(flex_eu_config_tdl_1);
2020
2021 return 0;
2022 case METRIC_SET_ID_TDL_2:
2023 dev_priv->perf.oa.n_mux_configs =
2024 get_tdl_2_mux_config(dev_priv,
2025 dev_priv->perf.oa.mux_regs,
2026 dev_priv->perf.oa.mux_regs_lens);
2027 if (dev_priv->perf.oa.n_mux_configs == 0) {
2028 DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
2029
2030 /* EINVAL because *_register_sysfs already checked this
2031 * and so it wouldn't have been advertised to userspace and
2032 * so shouldn't have been requested
2033 */
2034 return -EINVAL;
2035 }
2036
2037 dev_priv->perf.oa.b_counter_regs =
2038 b_counter_config_tdl_2;
2039 dev_priv->perf.oa.b_counter_regs_len =
2040 ARRAY_SIZE(b_counter_config_tdl_2);
2041
2042 dev_priv->perf.oa.flex_regs =
2043 flex_eu_config_tdl_2;
2044 dev_priv->perf.oa.flex_regs_len =
2045 ARRAY_SIZE(flex_eu_config_tdl_2);
2046
2047 return 0;
2048 case METRIC_SET_ID_COMPUTE_EXTRA:
2049 dev_priv->perf.oa.n_mux_configs =
2050 get_compute_extra_mux_config(dev_priv,
2051 dev_priv->perf.oa.mux_regs,
2052 dev_priv->perf.oa.mux_regs_lens);
2053 if (dev_priv->perf.oa.n_mux_configs == 0) {
2054 DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
2055
2056 /* EINVAL because *_register_sysfs already checked this
2057 * and so it wouldn't have been advertised to userspace and
2058 * so shouldn't have been requested
2059 */
2060 return -EINVAL;
2061 }
2062
2063 dev_priv->perf.oa.b_counter_regs =
2064 b_counter_config_compute_extra;
2065 dev_priv->perf.oa.b_counter_regs_len =
2066 ARRAY_SIZE(b_counter_config_compute_extra);
2067
2068 dev_priv->perf.oa.flex_regs =
2069 flex_eu_config_compute_extra;
2070 dev_priv->perf.oa.flex_regs_len =
2071 ARRAY_SIZE(flex_eu_config_compute_extra);
2072
2073 return 0;
2074 case METRIC_SET_ID_TEST_OA:
2075 dev_priv->perf.oa.n_mux_configs =
2076 get_test_oa_mux_config(dev_priv,
2077 dev_priv->perf.oa.mux_regs,
2078 dev_priv->perf.oa.mux_regs_lens);
2079 if (dev_priv->perf.oa.n_mux_configs == 0) {
2080 DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
2081
2082 /* EINVAL because *_register_sysfs already checked this
2083 * and so it wouldn't have been advertised to userspace and
2084 * so shouldn't have been requested
2085 */
2086 return -EINVAL;
2087 }
2088
2089 dev_priv->perf.oa.b_counter_regs =
2090 b_counter_config_test_oa;
2091 dev_priv->perf.oa.b_counter_regs_len =
2092 ARRAY_SIZE(b_counter_config_test_oa);
2093
2094 dev_priv->perf.oa.flex_regs =
2095 flex_eu_config_test_oa;
2096 dev_priv->perf.oa.flex_regs_len =
2097 ARRAY_SIZE(flex_eu_config_test_oa);
2098
2099 return 0;
2100 default:
2101 return -ENODEV;
2102 }
2103}
2104
2105static ssize_t
2106show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2107{
2108 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
2109}
2110
2111static struct device_attribute dev_attr_render_basic_id = {
2112 .attr = { .name = "id", .mode = 0444 },
2113 .show = show_render_basic_id,
2114 .store = NULL,
2115};
2116
2117static struct attribute *attrs_render_basic[] = {
2118 &dev_attr_render_basic_id.attr,
2119 NULL,
2120};
2121
2122static struct attribute_group group_render_basic = {
2123 .name = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68",
2124 .attrs = attrs_render_basic,
2125};
2126
2127static ssize_t
2128show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
2129{
2130 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
2131}
2132
2133static struct device_attribute dev_attr_compute_basic_id = {
2134 .attr = { .name = "id", .mode = 0444 },
2135 .show = show_compute_basic_id,
2136 .store = NULL,
2137};
2138
2139static struct attribute *attrs_compute_basic[] = {
2140 &dev_attr_compute_basic_id.attr,
2141 NULL,
2142};
2143
2144static struct attribute_group group_compute_basic = {
2145 .name = "814285f6-354d-41d2-ba49-e24e622714a0",
2146 .attrs = attrs_compute_basic,
2147};
2148
2149static ssize_t
2150show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
2151{
2152 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
2153}
2154
2155static struct device_attribute dev_attr_render_pipe_profile_id = {
2156 .attr = { .name = "id", .mode = 0444 },
2157 .show = show_render_pipe_profile_id,
2158 .store = NULL,
2159};
2160
2161static struct attribute *attrs_render_pipe_profile[] = {
2162 &dev_attr_render_pipe_profile_id.attr,
2163 NULL,
2164};
2165
2166static struct attribute_group group_render_pipe_profile = {
2167 .name = "07d397a6-b3e6-49f6-9433-a4f293d55978",
2168 .attrs = attrs_render_pipe_profile,
2169};
2170
2171static ssize_t
2172show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
2173{
2174 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
2175}
2176
2177static struct device_attribute dev_attr_memory_reads_id = {
2178 .attr = { .name = "id", .mode = 0444 },
2179 .show = show_memory_reads_id,
2180 .store = NULL,
2181};
2182
2183static struct attribute *attrs_memory_reads[] = {
2184 &dev_attr_memory_reads_id.attr,
2185 NULL,
2186};
2187
2188static struct attribute_group group_memory_reads = {
2189 .name = "1a356946-5428-450b-a2f0-89f8783a302d",
2190 .attrs = attrs_memory_reads,
2191};
2192
2193static ssize_t
2194show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
2195{
2196 return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
2197}
2198
2199static struct device_attribute dev_attr_memory_writes_id = {
2200 .attr = { .name = "id", .mode = 0444 },
2201 .show = show_memory_writes_id,
2202 .store = NULL,
2203};
2204
2205static struct attribute *attrs_memory_writes[] = {
2206 &dev_attr_memory_writes_id.attr,
2207 NULL,
2208};
2209
2210static struct attribute_group group_memory_writes = {
2211 .name = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9",
2212 .attrs = attrs_memory_writes,
2213};
2214
2215static ssize_t
2216show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
2217{
2218 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
2219}
2220
2221static struct device_attribute dev_attr_compute_extended_id = {
2222 .attr = { .name = "id", .mode = 0444 },
2223 .show = show_compute_extended_id,
2224 .store = NULL,
2225};
2226
2227static struct attribute *attrs_compute_extended[] = {
2228 &dev_attr_compute_extended_id.attr,
2229 NULL,
2230};
2231
2232static struct attribute_group group_compute_extended = {
2233 .name = "bc9bcff2-459a-4cbc-986d-a84b077153f3",
2234 .attrs = attrs_compute_extended,
2235};
2236
2237static ssize_t
2238show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
2239{
2240 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
2241}
2242
2243static struct device_attribute dev_attr_compute_l3_cache_id = {
2244 .attr = { .name = "id", .mode = 0444 },
2245 .show = show_compute_l3_cache_id,
2246 .store = NULL,
2247};
2248
2249static struct attribute *attrs_compute_l3_cache[] = {
2250 &dev_attr_compute_l3_cache_id.attr,
2251 NULL,
2252};
2253
2254static struct attribute_group group_compute_l3_cache = {
2255 .name = "88ec931f-5b4a-453a-9db6-a61232b6143d",
2256 .attrs = attrs_compute_l3_cache,
2257};
2258
2259static ssize_t
2260show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
2261{
2262 return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
2263}
2264
2265static struct device_attribute dev_attr_hdc_and_sf_id = {
2266 .attr = { .name = "id", .mode = 0444 },
2267 .show = show_hdc_and_sf_id,
2268 .store = NULL,
2269};
2270
2271static struct attribute *attrs_hdc_and_sf[] = {
2272 &dev_attr_hdc_and_sf_id.attr,
2273 NULL,
2274};
2275
2276static struct attribute_group group_hdc_and_sf = {
2277 .name = "530d176d-2a18-4014-adf8-1500c6c60835",
2278 .attrs = attrs_hdc_and_sf,
2279};
2280
2281static ssize_t
2282show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2283{
2284 return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
2285}
2286
2287static struct device_attribute dev_attr_l3_1_id = {
2288 .attr = { .name = "id", .mode = 0444 },
2289 .show = show_l3_1_id,
2290 .store = NULL,
2291};
2292
2293static struct attribute *attrs_l3_1[] = {
2294 &dev_attr_l3_1_id.attr,
2295 NULL,
2296};
2297
2298static struct attribute_group group_l3_1 = {
2299 .name = "fdee5a5a-f23c-43d1-aa73-f6257c71671d",
2300 .attrs = attrs_l3_1,
2301};
2302
2303static ssize_t
2304show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
2305{
2306 return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
2307}
2308
2309static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
2310 .attr = { .name = "id", .mode = 0444 },
2311 .show = show_rasterizer_and_pixel_backend_id,
2312 .store = NULL,
2313};
2314
2315static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
2316 &dev_attr_rasterizer_and_pixel_backend_id.attr,
2317 NULL,
2318};
2319
2320static struct attribute_group group_rasterizer_and_pixel_backend = {
2321 .name = "6617623e-ca73-4791-b2b7-ddedd0846a0c",
2322 .attrs = attrs_rasterizer_and_pixel_backend,
2323};
2324
2325static ssize_t
2326show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
2327{
2328 return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
2329}
2330
2331static struct device_attribute dev_attr_sampler_id = {
2332 .attr = { .name = "id", .mode = 0444 },
2333 .show = show_sampler_id,
2334 .store = NULL,
2335};
2336
2337static struct attribute *attrs_sampler[] = {
2338 &dev_attr_sampler_id.attr,
2339 NULL,
2340};
2341
2342static struct attribute_group group_sampler = {
2343 .name = "f3b2ea63-e82e-4234-b418-44dd20dd34d0",
2344 .attrs = attrs_sampler,
2345};
2346
2347static ssize_t
2348show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
2349{
2350 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
2351}
2352
2353static struct device_attribute dev_attr_tdl_1_id = {
2354 .attr = { .name = "id", .mode = 0444 },
2355 .show = show_tdl_1_id,
2356 .store = NULL,
2357};
2358
2359static struct attribute *attrs_tdl_1[] = {
2360 &dev_attr_tdl_1_id.attr,
2361 NULL,
2362};
2363
2364static struct attribute_group group_tdl_1 = {
2365 .name = "14411d35-cbf6-4f5e-b68b-190faf9a1a83",
2366 .attrs = attrs_tdl_1,
2367};
2368
2369static ssize_t
2370show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
2371{
2372 return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
2373}
2374
2375static struct device_attribute dev_attr_tdl_2_id = {
2376 .attr = { .name = "id", .mode = 0444 },
2377 .show = show_tdl_2_id,
2378 .store = NULL,
2379};
2380
2381static struct attribute *attrs_tdl_2[] = {
2382 &dev_attr_tdl_2_id.attr,
2383 NULL,
2384};
2385
2386static struct attribute_group group_tdl_2 = {
2387 .name = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d",
2388 .attrs = attrs_tdl_2,
2389};
2390
2391static ssize_t
2392show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
2393{
2394 return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
2395}
2396
2397static struct device_attribute dev_attr_compute_extra_id = {
2398 .attr = { .name = "id", .mode = 0444 },
2399 .show = show_compute_extra_id,
2400 .store = NULL,
2401};
2402
2403static struct attribute *attrs_compute_extra[] = {
2404 &dev_attr_compute_extra_id.attr,
2405 NULL,
2406};
2407
2408static struct attribute_group group_compute_extra = {
2409 .name = "15274c82-27d2-4819-876a-7cb1a2c59ba4",
2410 .attrs = attrs_compute_extra,
2411};
2412
2413static ssize_t
2414show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
2415{
2416 return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
2417}
2418
2419static struct device_attribute dev_attr_test_oa_id = {
2420 .attr = { .name = "id", .mode = 0444 },
2421 .show = show_test_oa_id,
2422 .store = NULL,
2423};
2424
2425static struct attribute *attrs_test_oa[] = {
2426 &dev_attr_test_oa_id.attr,
2427 NULL,
2428};
2429
2430static struct attribute_group group_test_oa = {
2431 .name = "dd3fd789-e783-4204-8cd0-b671bbccb0cf",
2432 .attrs = attrs_test_oa,
2433};
2434
2435int
2436i915_perf_register_sysfs_glk(struct drm_i915_private *dev_priv)
2437{
2438 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2439 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2440 int ret = 0;
2441
2442 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2443 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2444 if (ret)
2445 goto error_render_basic;
2446 }
2447 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
2448 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2449 if (ret)
2450 goto error_compute_basic;
2451 }
2452 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
2453 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2454 if (ret)
2455 goto error_render_pipe_profile;
2456 }
2457 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
2458 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2459 if (ret)
2460 goto error_memory_reads;
2461 }
2462 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
2463 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2464 if (ret)
2465 goto error_memory_writes;
2466 }
2467 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
2468 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2469 if (ret)
2470 goto error_compute_extended;
2471 }
2472 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
2473 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2474 if (ret)
2475 goto error_compute_l3_cache;
2476 }
2477 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
2478 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2479 if (ret)
2480 goto error_hdc_and_sf;
2481 }
2482 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2483 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2484 if (ret)
2485 goto error_l3_1;
2486 }
2487 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
2488 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2489 if (ret)
2490 goto error_rasterizer_and_pixel_backend;
2491 }
2492 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
2493 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
2494 if (ret)
2495 goto error_sampler;
2496 }
2497 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
2498 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2499 if (ret)
2500 goto error_tdl_1;
2501 }
2502 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
2503 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2504 if (ret)
2505 goto error_tdl_2;
2506 }
2507 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
2508 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2509 if (ret)
2510 goto error_compute_extra;
2511 }
2512 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
2513 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2514 if (ret)
2515 goto error_test_oa;
2516 }
2517
2518 return 0;
2519
2520error_test_oa:
2521 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2522 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2523error_compute_extra:
2524 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2525 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2526error_tdl_2:
2527 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2528 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2529error_tdl_1:
2530 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2531 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2532error_sampler:
2533 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2534 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2535error_rasterizer_and_pixel_backend:
2536 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2537 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2538error_l3_1:
2539 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2540 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2541error_hdc_and_sf:
2542 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2543 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2544error_compute_l3_cache:
2545 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2546 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2547error_compute_extended:
2548 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2549 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2550error_memory_writes:
2551 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2552 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2553error_memory_reads:
2554 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2555 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2556error_render_pipe_profile:
2557 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2558 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2559error_compute_basic:
2560 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2561 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2562error_render_basic:
2563 return ret;
2564}
2565
2566void
2567i915_perf_unregister_sysfs_glk(struct drm_i915_private *dev_priv)
2568{
2569 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
2570 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
2571
2572 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
2573 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
2574 if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
2575 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
2576 if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
2577 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
2578 if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
2579 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
2580 if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
2581 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
2582 if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
2583 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
2584 if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
2585 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
2586 if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
2587 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
2588 if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
2589 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
2590 if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
2591 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
2592 if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
2593 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
2594 if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
2595 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
2596 if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
2597 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
2598 if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
2599 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
2600 if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
2601 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
2602}