| Chris Metcalf | cd6f32a | 2012-03-29 15:25:59 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation, version 2. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, but |
| 9 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 11 | * NON INFRINGEMENT. See the GNU General Public License for |
| 12 | * more details. |
| 13 | */ |
| 14 | |
| 15 | #ifndef _ASM_TILE_CACHECTL_H |
| 16 | #define _ASM_TILE_CACHECTL_H |
| 17 | |
| 18 | /* |
| 19 | * Options for cacheflush system call. |
| 20 | * |
| 21 | * The ICACHE flush is performed on all cores currently running the |
| 22 | * current process's address space. The intent is for user |
| 23 | * applications to be able to modify code, invoke the system call, |
| 24 | * then allow arbitrary other threads in the same address space to see |
| 25 | * the newly-modified code. Passing a length of CHIP_L1I_CACHE_SIZE() |
| 26 | * or more invalidates the entire icache on all cores in the address |
| 27 | * spaces. (Note: currently this option invalidates the entire icache |
| 28 | * regardless of the requested address and length, but we may choose |
| 29 | * to honor the arguments at some point.) |
| 30 | * |
| 31 | * Flush and invalidation of memory can normally be performed with the |
| 32 | * __insn_flush(), __insn_inv(), and __insn_finv() instructions from |
| 33 | * userspace. The DCACHE option to the system call allows userspace |
| 34 | * to flush the entire L1+L2 data cache from the core. In this case, |
| 35 | * the address and length arguments are not used. The DCACHE flush is |
| 36 | * restricted to the current core, not all cores in the address space. |
| 37 | */ |
| 38 | #define ICACHE (1<<0) /* invalidate L1 instruction cache */ |
| 39 | #define DCACHE (1<<1) /* flush and invalidate data cache */ |
| 40 | #define BCACHE (ICACHE|DCACHE) /* flush both caches */ |
| 41 | |
| 42 | #endif /* _ASM_TILE_CACHECTL_H */ |