blob: 217459d02b2f85b6d5730e1c0d77e4fac7a108eb [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/mtd/nand/au1550nd.c
3 *
4 * Copyright (C) 2004 Embedded Edge, LLC
5 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/slab.h>
Manuel Laussb7f720d2011-05-08 10:42:20 +020013#include <linux/gpio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
15#include <linux/module.h>
Sergei Shtylyov35af68b2006-05-16 20:52:06 +040016#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/mtd/mtd.h>
18#include <linux/mtd/nand.h>
19#include <linux/mtd/partitions.h>
Manuel Laussb67a1a02011-12-08 10:42:10 +000020#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <asm/io.h>
Manuel Laussb67a1a02011-12-08 10:42:10 +000022#include <asm/mach-au1x00/au1000.h>
23#include <asm/mach-au1x00/au1550nd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
Manuel Laussb67a1a02011-12-08 10:42:10 +000026struct au1550nd_ctx {
27 struct mtd_info info;
28 struct nand_chip chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Manuel Laussb67a1a02011-12-08 10:42:10 +000030 int cs;
31 void __iomem *base;
32 void (*write_byte)(struct mtd_info *, u_char);
Linus Torvalds1da177e2005-04-16 15:20:36 -070033};
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
35/**
36 * au_read_byte - read one byte from the chip
37 * @mtd: MTD device structure
38 *
Brian Norris7854d3f2011-06-23 14:12:08 -070039 * read function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -070040 */
41static u_char au_read_byte(struct mtd_info *mtd)
42{
43 struct nand_chip *this = mtd->priv;
44 u_char ret = readb(this->IO_ADDR_R);
45 au_sync();
46 return ret;
47}
48
49/**
50 * au_write_byte - write one byte to the chip
51 * @mtd: MTD device structure
52 * @byte: pointer to data byte to write
53 *
Brian Norris7854d3f2011-06-23 14:12:08 -070054 * write function for 8it buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 */
56static void au_write_byte(struct mtd_info *mtd, u_char byte)
57{
58 struct nand_chip *this = mtd->priv;
59 writeb(byte, this->IO_ADDR_W);
60 au_sync();
61}
62
63/**
Brian Norris7854d3f2011-06-23 14:12:08 -070064 * au_read_byte16 - read one byte endianness aware from the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 * @mtd: MTD device structure
66 *
Brian Norris7854d3f2011-06-23 14:12:08 -070067 * read function for 16bit buswidth with endianness conversion
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 */
69static u_char au_read_byte16(struct mtd_info *mtd)
70{
71 struct nand_chip *this = mtd->priv;
72 u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
73 au_sync();
74 return ret;
75}
76
77/**
Brian Norris7854d3f2011-06-23 14:12:08 -070078 * au_write_byte16 - write one byte endianness aware to the chip
Linus Torvalds1da177e2005-04-16 15:20:36 -070079 * @mtd: MTD device structure
80 * @byte: pointer to data byte to write
81 *
Brian Norris7854d3f2011-06-23 14:12:08 -070082 * write function for 16bit buswidth with endianness conversion
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 */
84static void au_write_byte16(struct mtd_info *mtd, u_char byte)
85{
86 struct nand_chip *this = mtd->priv;
87 writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
88 au_sync();
89}
90
91/**
92 * au_read_word - read one word from the chip
93 * @mtd: MTD device structure
94 *
Brian Norris7854d3f2011-06-23 14:12:08 -070095 * read function for 16bit buswidth without endianness conversion
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 */
97static u16 au_read_word(struct mtd_info *mtd)
98{
99 struct nand_chip *this = mtd->priv;
100 u16 ret = readw(this->IO_ADDR_R);
101 au_sync();
102 return ret;
103}
104
105/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106 * au_write_buf - write buffer to chip
107 * @mtd: MTD device structure
108 * @buf: data buffer
109 * @len: number of bytes to write
110 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700111 * write function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112 */
113static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
114{
115 int i;
116 struct nand_chip *this = mtd->priv;
117
David Woodhousee0c7d762006-05-13 18:07:53 +0100118 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 writeb(buf[i], this->IO_ADDR_W);
120 au_sync();
121 }
122}
123
124/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000125 * au_read_buf - read chip data into buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 * @mtd: MTD device structure
127 * @buf: buffer to store date
128 * @len: number of bytes to read
129 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700130 * read function for 8bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 */
132static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
133{
134 int i;
135 struct nand_chip *this = mtd->priv;
136
David Woodhousee0c7d762006-05-13 18:07:53 +0100137 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 buf[i] = readb(this->IO_ADDR_R);
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000139 au_sync();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 }
141}
142
143/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 * au_write_buf16 - write buffer to chip
145 * @mtd: MTD device structure
146 * @buf: data buffer
147 * @len: number of bytes to write
148 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700149 * write function for 16bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 */
151static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
152{
153 int i;
154 struct nand_chip *this = mtd->priv;
155 u16 *p = (u16 *) buf;
156 len >>= 1;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000157
David Woodhousee0c7d762006-05-13 18:07:53 +0100158 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159 writew(p[i], this->IO_ADDR_W);
160 au_sync();
161 }
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000162
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163}
164
165/**
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000166 * au_read_buf16 - read chip data into buffer
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 * @mtd: MTD device structure
168 * @buf: buffer to store date
169 * @len: number of bytes to read
170 *
Brian Norris7854d3f2011-06-23 14:12:08 -0700171 * read function for 16bit buswidth
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 */
173static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
174{
175 int i;
176 struct nand_chip *this = mtd->priv;
177 u16 *p = (u16 *) buf;
178 len >>= 1;
179
David Woodhousee0c7d762006-05-13 18:07:53 +0100180 for (i = 0; i < len; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 p[i] = readw(this->IO_ADDR_R);
182 au_sync();
183 }
184}
185
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200186/* Select the chip by setting nCE to low */
187#define NAND_CTL_SETNCE 1
188/* Deselect the chip by setting nCE to high */
189#define NAND_CTL_CLRNCE 2
190/* Select the command latch by setting CLE to high */
191#define NAND_CTL_SETCLE 3
192/* Deselect the command latch by setting CLE to low */
193#define NAND_CTL_CLRCLE 4
194/* Select the address latch by setting ALE to high */
195#define NAND_CTL_SETALE 5
196/* Deselect the address latch by setting ALE to low */
197#define NAND_CTL_CLRALE 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198
199static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
200{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000201 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
202 struct nand_chip *this = mtd->priv;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
David Woodhousee0c7d762006-05-13 18:07:53 +0100204 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205
David Woodhousee0c7d762006-05-13 18:07:53 +0100206 case NAND_CTL_SETCLE:
Manuel Laussb67a1a02011-12-08 10:42:10 +0000207 this->IO_ADDR_W = ctx->base + MEM_STNAND_CMD;
David Woodhousee0c7d762006-05-13 18:07:53 +0100208 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
David Woodhousee0c7d762006-05-13 18:07:53 +0100210 case NAND_CTL_CLRCLE:
Manuel Laussb67a1a02011-12-08 10:42:10 +0000211 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
David Woodhousee0c7d762006-05-13 18:07:53 +0100212 break;
213
214 case NAND_CTL_SETALE:
Manuel Laussb67a1a02011-12-08 10:42:10 +0000215 this->IO_ADDR_W = ctx->base + MEM_STNAND_ADDR;
David Woodhousee0c7d762006-05-13 18:07:53 +0100216 break;
217
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000218 case NAND_CTL_CLRALE:
Manuel Laussb67a1a02011-12-08 10:42:10 +0000219 this->IO_ADDR_W = ctx->base + MEM_STNAND_DATA;
David Woodhousee0c7d762006-05-13 18:07:53 +0100220 /* FIXME: Nobody knows why this is necessary,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 * but it works only that way */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000222 udelay(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 break;
224
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000225 case NAND_CTL_SETNCE:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226 /* assert (force assert) chip enable */
Manuel Laussb67a1a02011-12-08 10:42:10 +0000227 au_writel((1 << (4 + ctx->cs)), MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 break;
229
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000230 case NAND_CTL_CLRNCE:
David Woodhousee0c7d762006-05-13 18:07:53 +0100231 /* deassert chip enable */
232 au_writel(0, MEM_STNDCTL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 break;
234 }
235
236 this->IO_ADDR_R = this->IO_ADDR_W;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000237
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 /* Drain the writebuffer */
239 au_sync();
240}
241
242int au1550_device_ready(struct mtd_info *mtd)
243{
244 int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
245 au_sync();
246 return ret;
247}
248
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400249/**
250 * au1550_select_chip - control -CE line
251 * Forbid driving -CE manually permitting the NAND controller to do this.
252 * Keeping -CE asserted during the whole sector reads interferes with the
253 * NOR flash and PCMCIA drivers as it causes contention on the static bus.
254 * We only have to hold -CE low for the NAND read commands since the flash
255 * chip needs it to be asserted during chip not ready time but the NAND
256 * controller keeps it released.
257 *
258 * @mtd: MTD device structure
259 * @chip: chipnumber to select, -1 for deselect
260 */
261static void au1550_select_chip(struct mtd_info *mtd, int chip)
262{
263}
264
265/**
266 * au1550_command - Send command to NAND device
267 * @mtd: MTD device structure
268 * @command: the command to be sent
269 * @column: the column address for this command, -1 if none
270 * @page_addr: the page address for this command, -1 if none
271 */
272static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
273{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000274 struct au1550nd_ctx *ctx = container_of(mtd, struct au1550nd_ctx, info);
275 struct nand_chip *this = mtd->priv;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400276 int ce_override = 0, i;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000277 unsigned long flags = 0;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400278
279 /* Begin command latch cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200280 au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400281 /*
282 * Write out the command to the device.
283 */
284 if (command == NAND_CMD_SEQIN) {
285 int readcmd;
286
Joern Engel28318772006-05-22 23:18:05 +0200287 if (column >= mtd->writesize) {
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400288 /* OOB area */
Joern Engel28318772006-05-22 23:18:05 +0200289 column -= mtd->writesize;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400290 readcmd = NAND_CMD_READOOB;
291 } else if (column < 256) {
292 /* First 256 bytes --> READ0 */
293 readcmd = NAND_CMD_READ0;
294 } else {
295 column -= 256;
296 readcmd = NAND_CMD_READ1;
297 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000298 ctx->write_byte(mtd, readcmd);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400299 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000300 ctx->write_byte(mtd, command);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400301
302 /* Set ALE and clear CLE to start address cycle */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200303 au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400304
305 if (column != -1 || page_addr != -1) {
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200306 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400307
308 /* Serially input address */
309 if (column != -1) {
310 /* Adjust columns for 16 bit buswidth */
311 if (this->options & NAND_BUSWIDTH_16)
312 column >>= 1;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000313 ctx->write_byte(mtd, column);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400314 }
315 if (page_addr != -1) {
Manuel Laussb67a1a02011-12-08 10:42:10 +0000316 ctx->write_byte(mtd, (u8)(page_addr & 0xff));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400317
318 if (command == NAND_CMD_READ0 ||
319 command == NAND_CMD_READ1 ||
320 command == NAND_CMD_READOOB) {
321 /*
322 * NAND controller will release -CE after
323 * the last address byte is written, so we'll
324 * have to forcibly assert it. No interrupts
325 * are allowed while we do this as we don't
326 * want the NOR flash or PCMCIA drivers to
327 * steal our precious bytes of data...
328 */
329 ce_override = 1;
330 local_irq_save(flags);
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200331 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400332 }
333
Manuel Laussb67a1a02011-12-08 10:42:10 +0000334 ctx->write_byte(mtd, (u8)(page_addr >> 8));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400335
336 /* One more address cycle for devices > 32MiB */
337 if (this->chipsize > (32 << 20))
Manuel Laussb67a1a02011-12-08 10:42:10 +0000338 ctx->write_byte(mtd,
339 ((page_addr >> 16) & 0x0f));
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400340 }
341 /* Latch in address */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200342 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400343 }
344
345 /*
346 * Program and erase have their own busy handlers.
347 * Status and sequential in need no delay.
348 */
349 switch (command) {
350
351 case NAND_CMD_PAGEPROG:
352 case NAND_CMD_ERASE1:
353 case NAND_CMD_ERASE2:
354 case NAND_CMD_SEQIN:
355 case NAND_CMD_STATUS:
356 return;
357
358 case NAND_CMD_RESET:
359 break;
360
361 case NAND_CMD_READ0:
362 case NAND_CMD_READ1:
363 case NAND_CMD_READOOB:
364 /* Check if we're really driving -CE low (just in case) */
365 if (unlikely(!ce_override))
366 break;
367
368 /* Apply a short delay always to ensure that we do wait tWB. */
369 ndelay(100);
370 /* Wait for a chip to become ready... */
371 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
372 udelay(1);
373
374 /* Release -CE and re-enable interrupts. */
Thomas Gleixner7abd3ef2006-05-23 23:25:53 +0200375 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400376 local_irq_restore(flags);
377 return;
378 }
379 /* Apply this short delay always to ensure that we do wait tWB. */
380 ndelay(100);
381
382 while(!this->dev_ready(mtd));
383}
384
Bill Pemberton06f25512012-11-19 13:23:07 -0500385static int find_nand_cs(unsigned long nand_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000387 void __iomem *base =
388 (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
389 unsigned long addr, staddr, start, mask, end;
390 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391
Manuel Laussb67a1a02011-12-08 10:42:10 +0000392 for (i = 0; i < 4; i++) {
393 addr = 0x1000 + (i * 0x10); /* CSx */
394 staddr = __raw_readl(base + addr + 0x08); /* STADDRx */
395 /* figure out the decoded range of this CS */
396 start = (staddr << 4) & 0xfffc0000;
397 mask = (staddr << 18) & 0xfffc0000;
398 end = (start | (start - 1)) & ~(start ^ mask);
399 if ((nand_base >= start) && (nand_base < end))
400 return i;
401 }
402
403 return -ENODEV;
404}
405
Bill Pemberton06f25512012-11-19 13:23:07 -0500406static int au1550nd_probe(struct platform_device *pdev)
Manuel Laussb67a1a02011-12-08 10:42:10 +0000407{
408 struct au1550nd_platdata *pd;
409 struct au1550nd_ctx *ctx;
410 struct nand_chip *this;
411 struct resource *r;
412 int ret, cs;
413
414 pd = pdev->dev.platform_data;
415 if (!pd) {
416 dev_err(&pdev->dev, "missing platform data\n");
417 return -ENODEV;
418 }
419
420 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
421 if (!ctx) {
422 dev_err(&pdev->dev, "no memory for NAND context\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700423 return -ENOMEM;
424 }
425
Manuel Laussb67a1a02011-12-08 10:42:10 +0000426 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
427 if (!r) {
428 dev_err(&pdev->dev, "no NAND memory resource\n");
429 ret = -ENODEV;
430 goto out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000432 if (request_mem_region(r->start, resource_size(r), "au1550-nand")) {
433 dev_err(&pdev->dev, "cannot claim NAND memory area\n");
434 ret = -ENOMEM;
435 goto out1;
Pete Popovef6f0d12005-09-23 02:44:58 +0100436 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000437
438 ctx->base = ioremap_nocache(r->start, 0x1000);
439 if (!ctx->base) {
440 dev_err(&pdev->dev, "cannot remap NAND memory area\n");
441 ret = -ENODEV;
442 goto out2;
Pete Popovef6f0d12005-09-23 02:44:58 +0100443 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000444
445 this = &ctx->chip;
446 ctx->info.priv = this;
447 ctx->info.owner = THIS_MODULE;
448
449 /* figure out which CS# r->start belongs to */
450 cs = find_nand_cs(r->start);
451 if (cs < 0) {
452 dev_err(&pdev->dev, "cannot detect NAND chipselect\n");
453 ret = -ENODEV;
454 goto out3;
Pete Popovef6f0d12005-09-23 02:44:58 +0100455 }
Manuel Laussb67a1a02011-12-08 10:42:10 +0000456 ctx->cs = cs;
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000457
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458 this->dev_ready = au1550_device_ready;
Sergei Shtylyov35af68b2006-05-16 20:52:06 +0400459 this->select_chip = au1550_select_chip;
460 this->cmdfunc = au1550_command;
461
Linus Torvalds1da177e2005-04-16 15:20:36 -0700462 /* 30 us command delay time */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000463 this->chip_delay = 30;
Thomas Gleixner6dfc6d22006-05-23 12:00:46 +0200464 this->ecc.mode = NAND_ECC_SOFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Manuel Laussb67a1a02011-12-08 10:42:10 +0000466 if (pd->devwidth)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 this->options |= NAND_BUSWIDTH_16;
468
Manuel Laussb67a1a02011-12-08 10:42:10 +0000469 this->read_byte = (pd->devwidth) ? au_read_byte16 : au_read_byte;
470 ctx->write_byte = (pd->devwidth) ? au_write_byte16 : au_write_byte;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471 this->read_word = au_read_word;
Manuel Laussb67a1a02011-12-08 10:42:10 +0000472 this->write_buf = (pd->devwidth) ? au_write_buf16 : au_write_buf;
473 this->read_buf = (pd->devwidth) ? au_read_buf16 : au_read_buf;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
Manuel Laussb67a1a02011-12-08 10:42:10 +0000475 ret = nand_scan(&ctx->info, 1);
476 if (ret) {
477 dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);
478 goto out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 }
480
Manuel Laussb67a1a02011-12-08 10:42:10 +0000481 mtd_device_register(&ctx->info, pd->parts, pd->num_parts);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482
483 return 0;
484
Manuel Laussb67a1a02011-12-08 10:42:10 +0000485out3:
486 iounmap(ctx->base);
487out2:
488 release_mem_region(r->start, resource_size(r));
489out1:
490 kfree(ctx);
491 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492}
493
Bill Pemberton810b7e02012-11-19 13:26:04 -0500494static int au1550nd_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495{
Manuel Laussb67a1a02011-12-08 10:42:10 +0000496 struct au1550nd_ctx *ctx = platform_get_drvdata(pdev);
497 struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498
Manuel Laussb67a1a02011-12-08 10:42:10 +0000499 nand_release(&ctx->info);
500 iounmap(ctx->base);
501 release_mem_region(r->start, 0x1000);
502 kfree(ctx);
503 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504}
David Woodhousee0c7d762006-05-13 18:07:53 +0100505
Manuel Laussb67a1a02011-12-08 10:42:10 +0000506static struct platform_driver au1550nd_driver = {
507 .driver = {
508 .name = "au1550-nand",
509 .owner = THIS_MODULE,
510 },
511 .probe = au1550nd_probe,
Bill Pemberton5153b882012-11-19 13:21:24 -0500512 .remove = au1550nd_remove,
Manuel Laussb67a1a02011-12-08 10:42:10 +0000513};
514
515module_platform_driver(au1550nd_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
517MODULE_LICENSE("GPL");
518MODULE_AUTHOR("Embedded Edge, LLC");
519MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");