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gerrit-public.fairphone.software / kernel / msm-5.4 / 4da1c67719f612af9f3ba2c804efa9d2452bae76 / . / arch / arm / boot / dts / am43xx-clocks.dtsi
blob: 3ad99a64dd167854c5c4a204d023c2077b8cc42b [file] [log] [blame]
Tero Kristo6a679202013-08-02 19:12:04 +0300[diff] [blame]1/*
2 * Device Tree Source for AM43xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scrm_clocks {
11 sys_clkin_ck: sys_clkin_ck {
12 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
15 ti,bit-shift = <22>;
16 reg = <0x0040>;
17 };
18
19 adc_tsc_fck: adc_tsc_fck {
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
22 clocks = <&sys_clkin_ck>;
23 clock-mult = <1>;
24 clock-div = <1>;
25 };
26
27 dcan0_fck: dcan0_fck {
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
30 clocks = <&sys_clkin_ck>;
31 clock-mult = <1>;
32 clock-div = <1>;
33 };
34
35 dcan1_fck: dcan1_fck {
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
39 clock-mult = <1>;
40 clock-div = <1>;
41 };
42
43 mcasp0_fck: mcasp0_fck {
44 #clock-cells = <0>;
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
47 clock-mult = <1>;
48 clock-div = <1>;
49 };
50
51 mcasp1_fck: mcasp1_fck {
52 #clock-cells = <0>;
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
55 clock-mult = <1>;
56 clock-div = <1>;
57 };
58
59 smartreflex0_fck: smartreflex0_fck {
60 #clock-cells = <0>;
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
63 clock-mult = <1>;
64 clock-div = <1>;
65 };
66
67 smartreflex1_fck: smartreflex1_fck {
68 #clock-cells = <0>;
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
71 clock-mult = <1>;
72 clock-div = <1>;
73 };
74
75 sha0_fck: sha0_fck {
76 #clock-cells = <0>;
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
79 clock-mult = <1>;
80 clock-div = <1>;
81 };
82
83 aes0_fck: aes0_fck {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
87 clock-mult = <1>;
88 clock-div = <1>;
89 };
Poddar, Sourav4da1c672014-04-29 19:45:46 +0530[diff] [blame^]90
91 ehrpwm0_tbclk: ehrpwm0_tbclk {
92 #clock-cells = <0>;
93 compatible = "ti,gate-clock";
94 clocks = <&dpll_per_m2_ck>;
95 ti,bit-shift = <0>;
96 reg = <0x0664>;
97 };
98
99 ehrpwm1_tbclk: ehrpwm1_tbclk {
100 #clock-cells = <0>;
101 compatible = "ti,gate-clock";
102 clocks = <&dpll_per_m2_ck>;
103 ti,bit-shift = <1>;
104 reg = <0x0664>;
105 };
106
107 ehrpwm2_tbclk: ehrpwm2_tbclk {
108 #clock-cells = <0>;
109 compatible = "ti,gate-clock";
110 clocks = <&dpll_per_m2_ck>;
111 ti,bit-shift = <2>;
112 reg = <0x0664>;
113 };
114
115 ehrpwm3_tbclk: ehrpwm3_tbclk {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clocks = <&dpll_per_m2_ck>;
119 ti,bit-shift = <4>;
120 reg = <0x0664>;
121 };
122
123 ehrpwm4_tbclk: ehrpwm4_tbclk {
124 #clock-cells = <0>;
125 compatible = "ti,gate-clock";
126 clocks = <&dpll_per_m2_ck>;
127 ti,bit-shift = <5>;
128 reg = <0x0664>;
129 };
130
131 ehrpwm5_tbclk: ehrpwm5_tbclk {
132 #clock-cells = <0>;
133 compatible = "ti,gate-clock";
134 clocks = <&dpll_per_m2_ck>;
135 ti,bit-shift = <6>;
136 reg = <0x0664>;
137 };
Tero Kristo6a679202013-08-02 19:12:04 +0300[diff] [blame]138};
139&prcm_clocks {
140 clk_32768_ck: clk_32768_ck {
141 #clock-cells = <0>;
142 compatible = "fixed-clock";
143 clock-frequency = <32768>;
144 };
145
146 clk_rc32k_ck: clk_rc32k_ck {
147 #clock-cells = <0>;
148 compatible = "fixed-clock";
149 clock-frequency = <32768>;
150 };
151
152 virt_19200000_ck: virt_19200000_ck {
153 #clock-cells = <0>;
154 compatible = "fixed-clock";
155 clock-frequency = <19200000>;
156 };
157
158 virt_24000000_ck: virt_24000000_ck {
159 #clock-cells = <0>;
160 compatible = "fixed-clock";
161 clock-frequency = <24000000>;
162 };
163
164 virt_25000000_ck: virt_25000000_ck {
165 #clock-cells = <0>;
166 compatible = "fixed-clock";
167 clock-frequency = <25000000>;
168 };
169
170 virt_26000000_ck: virt_26000000_ck {
171 #clock-cells = <0>;
172 compatible = "fixed-clock";
173 clock-frequency = <26000000>;
174 };
175
176 tclkin_ck: tclkin_ck {
177 #clock-cells = <0>;
178 compatible = "fixed-clock";
179 clock-frequency = <26000000>;
180 };
181
182 dpll_core_ck: dpll_core_ck {
183 #clock-cells = <0>;
184 compatible = "ti,am3-dpll-core-clock";
185 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
186 reg = <0x2d20>, <0x2d24>, <0x2d2c>;
187 };
188
189 dpll_core_x2_ck: dpll_core_x2_ck {
190 #clock-cells = <0>;
191 compatible = "ti,am3-dpll-x2-clock";
192 clocks = <&dpll_core_ck>;
193 };
194
195 dpll_core_m4_ck: dpll_core_m4_ck {
196 #clock-cells = <0>;
197 compatible = "ti,divider-clock";
198 clocks = <&dpll_core_x2_ck>;
199 ti,max-div = <31>;
200 ti,autoidle-shift = <8>;
201 reg = <0x2d38>;
202 ti,index-starts-at-one;
203 ti,invert-autoidle-bit;
204 };
205
206 dpll_core_m5_ck: dpll_core_m5_ck {
207 #clock-cells = <0>;
208 compatible = "ti,divider-clock";
209 clocks = <&dpll_core_x2_ck>;
210 ti,max-div = <31>;
211 ti,autoidle-shift = <8>;
212 reg = <0x2d3c>;
213 ti,index-starts-at-one;
214 ti,invert-autoidle-bit;
215 };
216
217 dpll_core_m6_ck: dpll_core_m6_ck {
218 #clock-cells = <0>;
219 compatible = "ti,divider-clock";
220 clocks = <&dpll_core_x2_ck>;
221 ti,max-div = <31>;
222 ti,autoidle-shift = <8>;
223 reg = <0x2d40>;
224 ti,index-starts-at-one;
225 ti,invert-autoidle-bit;
226 };
227
228 dpll_mpu_ck: dpll_mpu_ck {
229 #clock-cells = <0>;
230 compatible = "ti,am3-dpll-clock";
231 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
232 reg = <0x2d60>, <0x2d64>, <0x2d6c>;
233 };
234
235 dpll_mpu_m2_ck: dpll_mpu_m2_ck {
236 #clock-cells = <0>;
237 compatible = "ti,divider-clock";
238 clocks = <&dpll_mpu_ck>;
239 ti,max-div = <31>;
240 ti,autoidle-shift = <8>;
241 reg = <0x2d70>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 };
245
246 dpll_ddr_ck: dpll_ddr_ck {
247 #clock-cells = <0>;
248 compatible = "ti,am3-dpll-clock";
249 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
250 reg = <0x2da0>, <0x2da4>, <0x2dac>;
251 };
252
253 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
254 #clock-cells = <0>;
255 compatible = "ti,divider-clock";
256 clocks = <&dpll_ddr_ck>;
257 ti,max-div = <31>;
258 ti,autoidle-shift = <8>;
259 reg = <0x2db0>;
260 ti,index-starts-at-one;
261 ti,invert-autoidle-bit;
262 };
263
264 dpll_disp_ck: dpll_disp_ck {
265 #clock-cells = <0>;
266 compatible = "ti,am3-dpll-clock";
267 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
268 reg = <0x2e20>, <0x2e24>, <0x2e2c>;
269 };
270
271 dpll_disp_m2_ck: dpll_disp_m2_ck {
272 #clock-cells = <0>;
273 compatible = "ti,divider-clock";
274 clocks = <&dpll_disp_ck>;
275 ti,max-div = <31>;
276 ti,autoidle-shift = <8>;
277 reg = <0x2e30>;
278 ti,index-starts-at-one;
279 ti,invert-autoidle-bit;
280 };
281
282 dpll_per_ck: dpll_per_ck {
283 #clock-cells = <0>;
284 compatible = "ti,am3-dpll-j-type-clock";
285 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
286 reg = <0x2de0>, <0x2de4>, <0x2dec>;
287 };
288
289 dpll_per_m2_ck: dpll_per_m2_ck {
290 #clock-cells = <0>;
291 compatible = "ti,divider-clock";
292 clocks = <&dpll_per_ck>;
293 ti,max-div = <127>;
294 ti,autoidle-shift = <8>;
295 reg = <0x2df0>;
296 ti,index-starts-at-one;
297 ti,invert-autoidle-bit;
298 };
299
300 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
301 #clock-cells = <0>;
302 compatible = "fixed-factor-clock";
303 clocks = <&dpll_per_m2_ck>;
304 clock-mult = <1>;
305 clock-div = <4>;
306 };
307
308 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
309 #clock-cells = <0>;
310 compatible = "fixed-factor-clock";
311 clocks = <&dpll_per_m2_ck>;
312 clock-mult = <1>;
313 clock-div = <4>;
314 };
315
316 clk_24mhz: clk_24mhz {
317 #clock-cells = <0>;
318 compatible = "fixed-factor-clock";
319 clocks = <&dpll_per_m2_ck>;
320 clock-mult = <1>;
321 clock-div = <8>;
322 };
323
324 clkdiv32k_ck: clkdiv32k_ck {
325 #clock-cells = <0>;
326 compatible = "fixed-factor-clock";
327 clocks = <&clk_24mhz>;
328 clock-mult = <1>;
329 clock-div = <732>;
330 };
331
332 clkdiv32k_ick: clkdiv32k_ick {
333 #clock-cells = <0>;
334 compatible = "ti,gate-clock";
335 clocks = <&clkdiv32k_ck>;
336 ti,bit-shift = <8>;
337 reg = <0x2a38>;
338 };
339
340 sysclk_div: sysclk_div {
341 #clock-cells = <0>;
342 compatible = "fixed-factor-clock";
343 clocks = <&dpll_core_m4_ck>;
344 clock-mult = <1>;
345 clock-div = <1>;
346 };
347
348 pruss_ocp_gclk: pruss_ocp_gclk {
349 #clock-cells = <0>;
350 compatible = "ti,mux-clock";
351 clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
352 reg = <0x4248>;
353 };
354
355 clk_32k_tpm_ck: clk_32k_tpm_ck {
356 #clock-cells = <0>;
357 compatible = "fixed-clock";
358 clock-frequency = <32768>;
359 };
360
361 timer1_fck: timer1_fck {
362 #clock-cells = <0>;
363 compatible = "ti,mux-clock";
364 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
365 reg = <0x4200>;
366 };
367
368 timer2_fck: timer2_fck {
369 #clock-cells = <0>;
370 compatible = "ti,mux-clock";
371 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
372 reg = <0x4204>;
373 };
374
375 timer3_fck: timer3_fck {
376 #clock-cells = <0>;
377 compatible = "ti,mux-clock";
378 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
379 reg = <0x4208>;
380 };
381
382 timer4_fck: timer4_fck {
383 #clock-cells = <0>;
384 compatible = "ti,mux-clock";
385 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
386 reg = <0x420c>;
387 };
388
389 timer5_fck: timer5_fck {
390 #clock-cells = <0>;
391 compatible = "ti,mux-clock";
392 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
393 reg = <0x4210>;
394 };
395
396 timer6_fck: timer6_fck {
397 #clock-cells = <0>;
398 compatible = "ti,mux-clock";
399 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
400 reg = <0x4214>;
401 };
402
403 timer7_fck: timer7_fck {
404 #clock-cells = <0>;
405 compatible = "ti,mux-clock";
406 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
407 reg = <0x4218>;
408 };
409
410 wdt1_fck: wdt1_fck {
411 #clock-cells = <0>;
412 compatible = "ti,mux-clock";
413 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
414 reg = <0x422c>;
415 };
416
417 l3_gclk: l3_gclk {
418 #clock-cells = <0>;
419 compatible = "fixed-factor-clock";
420 clocks = <&dpll_core_m4_ck>;
421 clock-mult = <1>;
422 clock-div = <1>;
423 };
424
425 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
426 #clock-cells = <0>;
427 compatible = "fixed-factor-clock";
428 clocks = <&sysclk_div>;
429 clock-mult = <1>;
430 clock-div = <2>;
431 };
432
433 l4hs_gclk: l4hs_gclk {
434 #clock-cells = <0>;
435 compatible = "fixed-factor-clock";
436 clocks = <&dpll_core_m4_ck>;
437 clock-mult = <1>;
438 clock-div = <1>;
439 };
440
441 l3s_gclk: l3s_gclk {
442 #clock-cells = <0>;
443 compatible = "fixed-factor-clock";
444 clocks = <&dpll_core_m4_div2_ck>;
445 clock-mult = <1>;
446 clock-div = <1>;
447 };
448
449 l4ls_gclk: l4ls_gclk {
450 #clock-cells = <0>;
451 compatible = "fixed-factor-clock";
452 clocks = <&dpll_core_m4_div2_ck>;
453 clock-mult = <1>;
454 clock-div = <1>;
455 };
456
457 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
458 #clock-cells = <0>;
459 compatible = "fixed-factor-clock";
460 clocks = <&dpll_core_m5_ck>;
461 clock-mult = <1>;
462 clock-div = <2>;
463 };
464
465 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
466 #clock-cells = <0>;
467 compatible = "ti,mux-clock";
468 clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
469 reg = <0x4238>;
470 };
471
472 clk_32k_mosc_ck: clk_32k_mosc_ck {
473 #clock-cells = <0>;
474 compatible = "fixed-clock";
475 clock-frequency = <32768>;
476 };
477
478 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
479 #clock-cells = <0>;
480 compatible = "ti,mux-clock";
481 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
482 reg = <0x4240>;
483 };
484
485 gpio0_dbclk: gpio0_dbclk {
486 #clock-cells = <0>;
487 compatible = "ti,gate-clock";
488 clocks = <&gpio0_dbclk_mux_ck>;
489 ti,bit-shift = <8>;
490 reg = <0x2b68>;
491 };
492
493 gpio1_dbclk: gpio1_dbclk {
494 #clock-cells = <0>;
495 compatible = "ti,gate-clock";
496 clocks = <&clkdiv32k_ick>;
497 ti,bit-shift = <8>;
498 reg = <0x8c78>;
499 };
500
501 gpio2_dbclk: gpio2_dbclk {
502 #clock-cells = <0>;
503 compatible = "ti,gate-clock";
504 clocks = <&clkdiv32k_ick>;
505 ti,bit-shift = <8>;
506 reg = <0x8c80>;
507 };
508
509 gpio3_dbclk: gpio3_dbclk {
510 #clock-cells = <0>;
511 compatible = "ti,gate-clock";
512 clocks = <&clkdiv32k_ick>;
513 ti,bit-shift = <8>;
514 reg = <0x8c88>;
515 };
516
517 gpio4_dbclk: gpio4_dbclk {
518 #clock-cells = <0>;
519 compatible = "ti,gate-clock";
520 clocks = <&clkdiv32k_ick>;
521 ti,bit-shift = <8>;
522 reg = <0x8c90>;
523 };
524
525 gpio5_dbclk: gpio5_dbclk {
526 #clock-cells = <0>;
527 compatible = "ti,gate-clock";
528 clocks = <&clkdiv32k_ick>;
529 ti,bit-shift = <8>;
530 reg = <0x8c98>;
531 };
532
533 mmc_clk: mmc_clk {
534 #clock-cells = <0>;
535 compatible = "fixed-factor-clock";
536 clocks = <&dpll_per_m2_ck>;
537 clock-mult = <1>;
538 clock-div = <2>;
539 };
540
541 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
542 #clock-cells = <0>;
543 compatible = "ti,mux-clock";
544 clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
545 ti,bit-shift = <1>;
546 reg = <0x423c>;
547 };
548
549 gfx_fck_div_ck: gfx_fck_div_ck {
550 #clock-cells = <0>;
551 compatible = "ti,divider-clock";
552 clocks = <&gfx_fclk_clksel_ck>;
553 reg = <0x423c>;
554 ti,max-div = <2>;
555 };
556
557 disp_clk: disp_clk {
558 #clock-cells = <0>;
559 compatible = "ti,mux-clock";
560 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
561 reg = <0x4244>;
562 };
563
564 dpll_extdev_ck: dpll_extdev_ck {
565 #clock-cells = <0>;
566 compatible = "ti,am3-dpll-clock";
567 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
568 reg = <0x2e60>, <0x2e64>, <0x2e6c>;
569 };
570
571 dpll_extdev_m2_ck: dpll_extdev_m2_ck {
572 #clock-cells = <0>;
573 compatible = "ti,divider-clock";
574 clocks = <&dpll_extdev_ck>;
575 ti,max-div = <127>;
576 ti,autoidle-shift = <8>;
577 reg = <0x2e70>;
578 ti,index-starts-at-one;
579 ti,invert-autoidle-bit;
580 };
581
582 mux_synctimer32k_ck: mux_synctimer32k_ck {
583 #clock-cells = <0>;
584 compatible = "ti,mux-clock";
585 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
586 reg = <0x4230>;
587 };
588
589 synctimer_32kclk: synctimer_32kclk {
590 #clock-cells = <0>;
591 compatible = "ti,gate-clock";
592 clocks = <&mux_synctimer32k_ck>;
593 ti,bit-shift = <8>;
594 reg = <0x2a30>;
595 };
596
597 timer8_fck: timer8_fck {
598 #clock-cells = <0>;
599 compatible = "ti,mux-clock";
600 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
601 reg = <0x421c>;
602 };
603
604 timer9_fck: timer9_fck {
605 #clock-cells = <0>;
606 compatible = "ti,mux-clock";
607 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
608 reg = <0x4220>;
609 };
610
611 timer10_fck: timer10_fck {
612 #clock-cells = <0>;
613 compatible = "ti,mux-clock";
614 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
615 reg = <0x4224>;
616 };
617
618 timer11_fck: timer11_fck {
619 #clock-cells = <0>;
620 compatible = "ti,mux-clock";
621 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
622 reg = <0x4228>;
623 };
624
625 cpsw_50m_clkdiv: cpsw_50m_clkdiv {
626 #clock-cells = <0>;
627 compatible = "fixed-factor-clock";
628 clocks = <&dpll_core_m5_ck>;
629 clock-mult = <1>;
630 clock-div = <1>;
631 };
632
633 cpsw_5m_clkdiv: cpsw_5m_clkdiv {
634 #clock-cells = <0>;
635 compatible = "fixed-factor-clock";
636 clocks = <&cpsw_50m_clkdiv>;
637 clock-mult = <1>;
638 clock-div = <10>;
639 };
640
641 dpll_ddr_x2_ck: dpll_ddr_x2_ck {
642 #clock-cells = <0>;
643 compatible = "ti,am3-dpll-x2-clock";
644 clocks = <&dpll_ddr_ck>;
645 };
646
647 dpll_ddr_m4_ck: dpll_ddr_m4_ck {
648 #clock-cells = <0>;
649 compatible = "ti,divider-clock";
650 clocks = <&dpll_ddr_x2_ck>;
651 ti,max-div = <31>;
652 ti,autoidle-shift = <8>;
653 reg = <0x2db8>;
654 ti,index-starts-at-one;
655 ti,invert-autoidle-bit;
656 };
657
658 dpll_per_clkdcoldo: dpll_per_clkdcoldo {
659 #clock-cells = <0>;
Dave Gerlach50b96892014-03-28 15:54:31 -0500[diff] [blame]660 compatible = "ti,fixed-factor-clock";
Tero Kristo6a679202013-08-02 19:12:04 +0300[diff] [blame]661 clocks = <&dpll_per_ck>;
Dave Gerlach50b96892014-03-28 15:54:31 -0500[diff] [blame]662 ti,clock-mult = <1>;
663 ti,clock-div = <1>;
664 ti,autoidle-shift = <8>;
665 reg = <0x2e14>;
666 ti,invert-autoidle-bit;
Tero Kristo6a679202013-08-02 19:12:04 +0300[diff] [blame]667 };
668
669 dll_aging_clk_div: dll_aging_clk_div {
670 #clock-cells = <0>;
671 compatible = "ti,divider-clock";
672 clocks = <&sys_clkin_ck>;
673 reg = <0x4250>;
674 ti,dividers = <8>, <16>, <32>;
675 };
676
677 div_core_25m_ck: div_core_25m_ck {
678 #clock-cells = <0>;
679 compatible = "fixed-factor-clock";
680 clocks = <&sysclk_div>;
681 clock-mult = <1>;
682 clock-div = <8>;
683 };
684
685 func_12m_clk: func_12m_clk {
686 #clock-cells = <0>;
687 compatible = "fixed-factor-clock";
688 clocks = <&dpll_per_m2_ck>;
689 clock-mult = <1>;
690 clock-div = <16>;
691 };
692
693 vtp_clk_div: vtp_clk_div {
694 #clock-cells = <0>;
695 compatible = "fixed-factor-clock";
696 clocks = <&sys_clkin_ck>;
697 clock-mult = <1>;
698 clock-div = <2>;
699 };
700
701 usbphy_32khz_clkmux: usbphy_32khz_clkmux {
702 #clock-cells = <0>;
703 compatible = "ti,mux-clock";
704 clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
705 reg = <0x4260>;
706 };
707};