Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / 4ebbefd6b93c34d6da0d950b1d2e0dcca2f1e6ef / . / drivers / pinctrl / sunxi / pinctrl-sun7i-a20.c
blob: d8577ce5f1a405dc49c61e0ddee01b7079bf5563 [file] [log] [blame]
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]1/*
Maxime Ripard25198592014-04-18 20:12:50 +0200[diff] [blame]2 * Allwinner A20 SoCs pinctrl driver.
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]3 *
Maxime Ripard25198592014-04-18 20:12:50 +0200[diff] [blame]4 * Copyright (C) 2014 Maxime Ripard
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
Maxime Ripard25198592014-04-18 20:12:50 +0200[diff] [blame]13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/pinctrl.h>
Maxime Ripard44abb932013-06-09 18:36:03 +0200[diff] [blame]18
19#include "pinctrl-sunxi.h"
20
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]21static const struct sunxi_desc_pin sun7i_a20_pins[] = {
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]22 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]23 SUNXI_FUNCTION(0x0, "gpio_in"),
24 SUNXI_FUNCTION(0x1, "gpio_out"),
25 SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */
26 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
27 SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
28 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]29 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]30 SUNXI_FUNCTION(0x0, "gpio_in"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */
33 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
34 SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
35 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]36 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]37 SUNXI_FUNCTION(0x0, "gpio_in"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */
40 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
41 SUNXI_FUNCTION(0x4, "uart2"), /* TX */
42 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]44 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */
47 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
48 SUNXI_FUNCTION(0x4, "uart2"), /* RX */
49 SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]50 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]51 SUNXI_FUNCTION(0x0, "gpio_in"),
52 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
54 SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
55 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]56 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]57 SUNXI_FUNCTION(0x0, "gpio_in"),
58 SUNXI_FUNCTION(0x1, "gpio_out"),
59 SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
60 SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
61 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]62 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]63 SUNXI_FUNCTION(0x0, "gpio_in"),
64 SUNXI_FUNCTION(0x1, "gpio_out"),
65 SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
66 SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
67 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
72 SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
73 SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]74 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]75 SUNXI_FUNCTION(0x0, "gpio_in"),
76 SUNXI_FUNCTION(0x1, "gpio_out"),
77 SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
78 SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
79 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]80 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]81 SUNXI_FUNCTION(0x0, "gpio_in"),
82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
84 SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
85 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */
86 SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]87 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
91 SUNXI_FUNCTION(0x4, "uart1"), /* TX */
92 SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]93 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]94 SUNXI_FUNCTION(0x0, "gpio_in"),
95 SUNXI_FUNCTION(0x1, "gpio_out"),
96 SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
97 SUNXI_FUNCTION(0x4, "uart1"), /* RX */
98 SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]99 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]100 SUNXI_FUNCTION(0x0, "gpio_in"),
101 SUNXI_FUNCTION(0x1, "gpio_out"),
102 SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */
103 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
104 SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
105 SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]106 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]107 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out"),
109 SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */
110 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
111 SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
112 SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]113 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]114 SUNXI_FUNCTION(0x0, "gpio_in"),
115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */
117 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
118 SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
119 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */
120 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]121 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]122 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out"),
124 SUNXI_FUNCTION(0x2, "emac"), /* ECRS */
125 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
126 SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
127 SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */
128 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]129 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]130 SUNXI_FUNCTION(0x0, "gpio_in"),
131 SUNXI_FUNCTION(0x1, "gpio_out"),
132 SUNXI_FUNCTION(0x2, "emac"), /* ECOL */
133 SUNXI_FUNCTION(0x3, "can"), /* TX */
134 SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
135 SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */
136 SUNXI_FUNCTION(0x6, "i2s1")), /* DO */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]137 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]138 SUNXI_FUNCTION(0x0, "gpio_in"),
139 SUNXI_FUNCTION(0x1, "gpio_out"),
140 SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */
141 SUNXI_FUNCTION(0x3, "can"), /* RX */
142 SUNXI_FUNCTION(0x4, "uart1"), /* RING */
143 SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */
144 SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */
145 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]146 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]147 SUNXI_FUNCTION(0x0, "gpio_in"),
148 SUNXI_FUNCTION(0x1, "gpio_out"),
149 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]150 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]151 SUNXI_FUNCTION(0x0, "gpio_in"),
152 SUNXI_FUNCTION(0x1, "gpio_out"),
153 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]154 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]155 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out"),
157 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]158 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]159 SUNXI_FUNCTION(0x0, "gpio_in"),
160 SUNXI_FUNCTION(0x1, "gpio_out"),
161 SUNXI_FUNCTION(0x2, "ir0"), /* TX */
162 SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]163 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]167 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]168 SUNXI_FUNCTION(0x0, "gpio_in"),
169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */
171 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]172 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]173 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */
176 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]177 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]178 SUNXI_FUNCTION(0x0, "gpio_in"),
179 SUNXI_FUNCTION(0x1, "gpio_out"),
180 SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */
181 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]182 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]183 SUNXI_FUNCTION(0x0, "gpio_in"),
184 SUNXI_FUNCTION(0x1, "gpio_out"),
185 SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */
186 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]187 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]188 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out"),
190 SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]191 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]192 SUNXI_FUNCTION(0x0, "gpio_in"),
193 SUNXI_FUNCTION(0x1, "gpio_out"),
194 SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]195 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]196 SUNXI_FUNCTION(0x0, "gpio_in"),
197 SUNXI_FUNCTION(0x1, "gpio_out"),
198 SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]199 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "i2s0"), /* DI */
203 SUNXI_FUNCTION(0x3, "ac97"), /* DI */
204 SUNXI_FUNCTION(0x4, "spdif")), /* DI */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]205 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]206 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out"),
208 SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */
209 SUNXI_FUNCTION(0x4, "spdif")), /* DO */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]210 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]211 SUNXI_FUNCTION(0x0, "gpio_in"),
212 SUNXI_FUNCTION(0x1, "gpio_out"),
213 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
214 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]215 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]216 SUNXI_FUNCTION(0x0, "gpio_in"),
217 SUNXI_FUNCTION(0x1, "gpio_out"),
218 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
219 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]220 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]221 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out"),
223 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
224 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]225 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]226 SUNXI_FUNCTION(0x0, "gpio_in"),
227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
229 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]230 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]231 SUNXI_FUNCTION(0x0, "gpio_in"),
232 SUNXI_FUNCTION(0x1, "gpio_out"),
233 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]234 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]235 SUNXI_FUNCTION(0x0, "gpio_in"),
236 SUNXI_FUNCTION(0x1, "gpio_out"),
237 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]238 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]239 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out"),
241 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]242 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]246 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]247 SUNXI_FUNCTION(0x0, "gpio_in"),
248 SUNXI_FUNCTION(0x1, "gpio_out"),
249 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
250 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]251 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]252 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out"),
254 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
255 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
256 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]257 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]258 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out"),
260 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
261 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]262 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]263 SUNXI_FUNCTION(0x0, "gpio_in"),
264 SUNXI_FUNCTION(0x1, "gpio_out"),
265 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
266 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]267 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]268 SUNXI_FUNCTION(0x0, "gpio_in"),
269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
271 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]272 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]273 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]276 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]277 SUNXI_FUNCTION(0x0, "gpio_in"),
278 SUNXI_FUNCTION(0x1, "gpio_out"),
279 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]280 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]281 SUNXI_FUNCTION(0x0, "gpio_in"),
282 SUNXI_FUNCTION(0x1, "gpio_out"),
283 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]284 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out"),
287 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
288 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]289 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]290 SUNXI_FUNCTION(0x0, "gpio_in"),
291 SUNXI_FUNCTION(0x1, "gpio_out"),
292 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
293 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]294 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]295 SUNXI_FUNCTION(0x0, "gpio_in"),
296 SUNXI_FUNCTION(0x1, "gpio_out"),
297 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
298 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]299 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]300 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out"),
302 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
303 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]304 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]305 SUNXI_FUNCTION(0x0, "gpio_in"),
306 SUNXI_FUNCTION(0x1, "gpio_out"),
307 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
308 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]309 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]310 SUNXI_FUNCTION(0x0, "gpio_in"),
311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
313 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]314 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]315 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out"),
317 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]318 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]319 SUNXI_FUNCTION(0x0, "gpio_in"),
320 SUNXI_FUNCTION(0x1, "gpio_out"),
321 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]322 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]323 SUNXI_FUNCTION(0x0, "gpio_in"),
324 SUNXI_FUNCTION(0x1, "gpio_out"),
325 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]326 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]330 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]331 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]334 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]335 SUNXI_FUNCTION(0x0, "gpio_in"),
336 SUNXI_FUNCTION(0x1, "gpio_out"),
337 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]338 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]339 SUNXI_FUNCTION(0x0, "gpio_in"),
340 SUNXI_FUNCTION(0x1, "gpio_out"),
341 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]342 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]343 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out"),
345 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
346 SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
347 SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]348 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]349 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out"),
351 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
352 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
353 SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]354 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]355 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
358 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
359 SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]360 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]361 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out"),
363 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
364 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
365 SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]366 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]370 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]371 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out"),
373 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
374 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]375 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]376 SUNXI_FUNCTION(0x0, "gpio_in"),
377 SUNXI_FUNCTION(0x1, "gpio_out"),
378 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
379 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]380 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]381 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"),
383 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
384 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]385 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]386 SUNXI_FUNCTION(0x0, "gpio_in"),
387 SUNXI_FUNCTION(0x1, "gpio_out"),
388 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
389 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]390 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]391 SUNXI_FUNCTION(0x0, "gpio_in"),
392 SUNXI_FUNCTION(0x1, "gpio_out"),
393 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
394 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]395 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]396 SUNXI_FUNCTION(0x0, "gpio_in"),
397 SUNXI_FUNCTION(0x1, "gpio_out"),
398 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
399 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]400 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]401 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out"),
403 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
404 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]405 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]406 SUNXI_FUNCTION(0x0, "gpio_in"),
407 SUNXI_FUNCTION(0x1, "gpio_out"),
408 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
409 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]410 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]411 SUNXI_FUNCTION(0x0, "gpio_in"),
412 SUNXI_FUNCTION(0x1, "gpio_out"),
413 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
414 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]415 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]416 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out"),
418 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
419 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]420 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]421 SUNXI_FUNCTION(0x0, "gpio_in"),
422 SUNXI_FUNCTION(0x1, "gpio_out"),
423 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
424 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]425 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]426 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out"),
428 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
429 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]430 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]431 SUNXI_FUNCTION(0x0, "gpio_in"),
432 SUNXI_FUNCTION(0x1, "gpio_out"),
433 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
434 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]435 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]436 SUNXI_FUNCTION(0x0, "gpio_in"),
437 SUNXI_FUNCTION(0x1, "gpio_out"),
438 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
439 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]440 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]441 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out"),
443 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
444 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]445 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]446 SUNXI_FUNCTION(0x0, "gpio_in"),
447 SUNXI_FUNCTION(0x1, "gpio_out"),
448 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
449 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]450 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]451 SUNXI_FUNCTION(0x0, "gpio_in"),
452 SUNXI_FUNCTION(0x1, "gpio_out"),
453 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
454 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]455 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]456 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out"),
458 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
459 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]460 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]461 SUNXI_FUNCTION(0x0, "gpio_in"),
462 SUNXI_FUNCTION(0x1, "gpio_out"),
463 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
464 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]465 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]466 SUNXI_FUNCTION(0x0, "gpio_in"),
467 SUNXI_FUNCTION(0x1, "gpio_out"),
468 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
469 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]470 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]471 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out"),
473 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
474 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]475 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]476 SUNXI_FUNCTION(0x0, "gpio_in"),
477 SUNXI_FUNCTION(0x1, "gpio_out"),
478 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
479 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]480 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]481 SUNXI_FUNCTION(0x0, "gpio_in"),
482 SUNXI_FUNCTION(0x1, "gpio_out"),
483 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
484 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]485 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]486 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out"),
488 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
489 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]490 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]491 SUNXI_FUNCTION(0x0, "gpio_in"),
492 SUNXI_FUNCTION(0x1, "gpio_out"),
493 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
494 SUNXI_FUNCTION(0x3, "sim")), /* DET */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]495 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]496 SUNXI_FUNCTION(0x0, "gpio_in"),
497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
499 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]500 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
504 SUNXI_FUNCTION(0x3, "sim")), /* RST */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]505 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]506 SUNXI_FUNCTION(0x0, "gpio_in"),
507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
509 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]510 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]511 SUNXI_FUNCTION(0x0, "gpio_in"),
512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
514 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
515 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]516 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]517 SUNXI_FUNCTION(0x0, "gpio_in"),
518 SUNXI_FUNCTION(0x1, "gpio_out"),
519 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
520 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]521 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
525 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]526 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]527 SUNXI_FUNCTION(0x0, "gpio_in"),
528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
530 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]531 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]532 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out"),
534 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
535 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]536 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]537 SUNXI_FUNCTION(0x0, "gpio_in"),
538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
540 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]541 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]542 SUNXI_FUNCTION(0x0, "gpio_in"),
543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
545 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
546 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]547 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]548 SUNXI_FUNCTION(0x0, "gpio_in"),
549 SUNXI_FUNCTION(0x1, "gpio_out"),
550 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
551 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]552 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]553 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out"),
555 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
556 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]557 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
561 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]562 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
566 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]567 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]568 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
571 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]572 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
576 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
577 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]578 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]579 SUNXI_FUNCTION(0x0, "gpio_in"),
580 SUNXI_FUNCTION(0x1, "gpio_out"),
581 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
582 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]583 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]584 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out"),
586 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
587 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]588 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]589 SUNXI_FUNCTION(0x0, "gpio_in"),
590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
592 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]593 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]594 SUNXI_FUNCTION(0x0, "gpio_in"),
595 SUNXI_FUNCTION(0x1, "gpio_out"),
596 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
597 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]598 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]599 SUNXI_FUNCTION(0x0, "gpio_in"),
600 SUNXI_FUNCTION(0x1, "gpio_out"),
601 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
602 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]603 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
607 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
608 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]609 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]610 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out"),
612 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
613 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
614 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]615 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]616 SUNXI_FUNCTION(0x0, "gpio_in"),
617 SUNXI_FUNCTION(0x1, "gpio_out"),
618 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
619 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
620 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]621 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]622 SUNXI_FUNCTION(0x0, "gpio_in"),
623 SUNXI_FUNCTION(0x1, "gpio_out"),
624 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
625 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
626 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]627 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]628 SUNXI_FUNCTION(0x0, "gpio_in"),
629 SUNXI_FUNCTION(0x1, "gpio_out"),
630 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
631 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
632 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]633 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]634 SUNXI_FUNCTION(0x0, "gpio_in"),
635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
637 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
638 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
639 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]640 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]641 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
644 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
645 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
646 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]647 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]648 SUNXI_FUNCTION(0x0, "gpio_in"),
649 SUNXI_FUNCTION(0x1, "gpio_out"),
650 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
651 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
652 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
653 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]654 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]655 SUNXI_FUNCTION(0x0, "gpio_in"),
656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
658 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
659 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
660 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]661 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]662 SUNXI_FUNCTION(0x0, "gpio_in"),
663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
665 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
666 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
667 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]668 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]669 SUNXI_FUNCTION(0x0, "gpio_in"),
670 SUNXI_FUNCTION(0x1, "gpio_out"),
671 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
672 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
673 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
674 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]675 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]676 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out"),
678 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
679 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
680 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
681 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]682 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]683 SUNXI_FUNCTION(0x0, "gpio_in"),
684 SUNXI_FUNCTION(0x1, "gpio_out"),
685 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
686 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
687 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
688 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
689 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]690 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]691 SUNXI_FUNCTION(0x0, "gpio_in"),
692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
694 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
695 SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]697 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]698 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
701 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
702 SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */
703 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]704 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]705 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
708 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
709 SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */
710 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]711 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]712 SUNXI_FUNCTION(0x0, "gpio_in"),
713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
715 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
716 SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */
717 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]718 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]719 SUNXI_FUNCTION(0x0, "gpio_in"),
720 SUNXI_FUNCTION(0x1, "gpio_out"),
721 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
722 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
723 SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */
724 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
729 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
730 SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */
731 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]732 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]733 SUNXI_FUNCTION(0x0, "gpio_in"),
734 SUNXI_FUNCTION(0x1, "gpio_out"),
735 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
736 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
737 SUNXI_FUNCTION(0x5, "ms"), /* BS */
738 SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
739 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]740 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]741 SUNXI_FUNCTION(0x0, "gpio_in"),
742 SUNXI_FUNCTION(0x1, "gpio_out"),
743 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
744 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
745 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
746 SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
747 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]748 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]749 SUNXI_FUNCTION(0x0, "gpio_in"),
750 SUNXI_FUNCTION(0x1, "gpio_out"),
751 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
752 SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */
753 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
754 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
755 SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
756 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]757 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]758 SUNXI_FUNCTION(0x0, "gpio_in"),
759 SUNXI_FUNCTION(0x1, "gpio_out"),
760 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
761 SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */
762 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
763 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
764 SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
765 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]766 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]767 SUNXI_FUNCTION(0x0, "gpio_in"),
768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
770 SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */
771 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
772 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
773 SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
774 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]775 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]776 SUNXI_FUNCTION(0x0, "gpio_in"),
777 SUNXI_FUNCTION(0x1, "gpio_out"),
778 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
779 SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */
780 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
781 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
782 SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
783 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]784 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]785 SUNXI_FUNCTION(0x0, "gpio_in"),
786 SUNXI_FUNCTION(0x1, "gpio_out"),
787 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
788 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
789 SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */
790 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]791 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]792 SUNXI_FUNCTION(0x0, "gpio_in"),
793 SUNXI_FUNCTION(0x1, "gpio_out"),
794 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
795 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
796 SUNXI_FUNCTION(0x5, "sim"), /* RST */
797 SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */
798 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]799 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]800 SUNXI_FUNCTION(0x0, "gpio_in"),
801 SUNXI_FUNCTION(0x1, "gpio_out"),
802 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
803 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
804 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
805 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
806 SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
807 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]808 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]809 SUNXI_FUNCTION(0x0, "gpio_in"),
810 SUNXI_FUNCTION(0x1, "gpio_out"),
811 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
812 SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */
813 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
814 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
815 SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
816 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]817 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]818 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out"),
820 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
821 SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */
822 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
823 SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
824 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]825 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]826 SUNXI_FUNCTION(0x0, "gpio_in"),
827 SUNXI_FUNCTION(0x1, "gpio_out"),
828 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
829 SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */
830 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
831 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
832 SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
833 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]834 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]835 SUNXI_FUNCTION(0x0, "gpio_in"),
836 SUNXI_FUNCTION(0x1, "gpio_out"),
837 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
838 SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */
839 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
840 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
841 SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
842 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]843 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]844 SUNXI_FUNCTION(0x0, "gpio_in"),
845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
847 SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */
848 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
849 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
850 SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
851 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]852 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]853 SUNXI_FUNCTION(0x0, "gpio_in"),
854 SUNXI_FUNCTION(0x1, "gpio_out"),
855 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
856 SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */
857 SUNXI_FUNCTION(0x4, "can"), /* TX */
858 SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
859 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]860 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]861 SUNXI_FUNCTION(0x0, "gpio_in"),
862 SUNXI_FUNCTION(0x1, "gpio_out"),
863 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
864 SUNXI_FUNCTION(0x3, "emac"), /* EMDC */
865 SUNXI_FUNCTION(0x4, "can"), /* RX */
866 SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
867 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]868 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]869 SUNXI_FUNCTION(0x0, "gpio_in"),
870 SUNXI_FUNCTION(0x1, "gpio_out"),
871 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
872 SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */
873 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
874 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
875 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]876 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]877 SUNXI_FUNCTION(0x0, "gpio_in"),
878 SUNXI_FUNCTION(0x1, "gpio_out"),
879 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
880 SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */
881 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
882 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
883 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]884 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]885 SUNXI_FUNCTION(0x0, "gpio_in"),
886 SUNXI_FUNCTION(0x1, "gpio_out"),
887 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
888 SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */
889 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
890 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
891 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]892 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]893 SUNXI_FUNCTION(0x0, "gpio_in"),
894 SUNXI_FUNCTION(0x1, "gpio_out"),
895 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
896 SUNXI_FUNCTION(0x3, "emac"), /* ECRS */
897 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
898 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
899 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]900 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]901 SUNXI_FUNCTION(0x0, "gpio_in"),
902 SUNXI_FUNCTION(0x1, "gpio_out"),
903 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
904 SUNXI_FUNCTION(0x3, "emac"), /* ECOL */
905 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
906 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
907 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]908 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]909 SUNXI_FUNCTION(0x0, "gpio_in"),
910 SUNXI_FUNCTION(0x1, "gpio_out"),
911 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
912 SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */
913 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
914 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
915 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
916 /* Hole */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]917 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]918 SUNXI_FUNCTION(0x0, "gpio_in"),
919 SUNXI_FUNCTION(0x1, "gpio_out"),
920 SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]921 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]922 SUNXI_FUNCTION(0x0, "gpio_in"),
923 SUNXI_FUNCTION(0x1, "gpio_out"),
924 SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]925 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]926 SUNXI_FUNCTION(0x0, "gpio_in"),
927 SUNXI_FUNCTION(0x1, "gpio_out"),
928 SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]929 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]930 SUNXI_FUNCTION(0x0, "gpio_in"),
931 SUNXI_FUNCTION(0x1, "gpio_out"),
932 SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
933 SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]934 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]935 SUNXI_FUNCTION(0x0, "gpio_in"),
936 SUNXI_FUNCTION(0x1, "gpio_out"),
937 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]938 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]939 SUNXI_FUNCTION(0x0, "gpio_in"),
940 SUNXI_FUNCTION(0x1, "gpio_out"),
941 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]942 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]943 SUNXI_FUNCTION(0x0, "gpio_in"),
944 SUNXI_FUNCTION(0x1, "gpio_out"),
945 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]946 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]947 SUNXI_FUNCTION(0x0, "gpio_in"),
948 SUNXI_FUNCTION(0x1, "gpio_out"),
949 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]950 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]951 SUNXI_FUNCTION(0x0, "gpio_in"),
952 SUNXI_FUNCTION(0x1, "gpio_out"),
953 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]954 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]955 SUNXI_FUNCTION(0x0, "gpio_in"),
956 SUNXI_FUNCTION(0x1, "gpio_out"),
957 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]958 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]959 SUNXI_FUNCTION(0x0, "gpio_in"),
960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
962 SUNXI_FUNCTION(0x3, "uart5"), /* TX */
963 SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]964 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]965 SUNXI_FUNCTION(0x0, "gpio_in"),
966 SUNXI_FUNCTION(0x1, "gpio_out"),
967 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
968 SUNXI_FUNCTION(0x3, "uart5"), /* RX */
969 SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]970 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]971 SUNXI_FUNCTION(0x0, "gpio_in"),
972 SUNXI_FUNCTION(0x1, "gpio_out"),
973 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
974 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
Chen-Yu Tsaib6a32a22013-12-30 11:25:48 +0800[diff] [blame]975 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]976 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]977 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]978 SUNXI_FUNCTION(0x0, "gpio_in"),
979 SUNXI_FUNCTION(0x1, "gpio_out"),
980 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
981 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
Chen-Yu Tsaib6a32a22013-12-30 11:25:48 +0800[diff] [blame]982 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]983 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]984 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]985 SUNXI_FUNCTION(0x0, "gpio_in"),
986 SUNXI_FUNCTION(0x1, "gpio_out"),
987 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
988 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
989 SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
990 SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]991 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]992 SUNXI_FUNCTION(0x0, "gpio_in"),
993 SUNXI_FUNCTION(0x1, "gpio_out"),
994 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
995 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
996 SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
997 SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]998 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]999 SUNXI_FUNCTION(0x0, "gpio_in"),
1000 SUNXI_FUNCTION(0x1, "gpio_out"),
1001 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1002 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
1003 SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]1004 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1005 SUNXI_FUNCTION(0x0, "gpio_in"),
1006 SUNXI_FUNCTION(0x1, "gpio_out"),
1007 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1008 SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
1009 SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]1010 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1011 SUNXI_FUNCTION(0x0, "gpio_in"),
1012 SUNXI_FUNCTION(0x1, "gpio_out"),
1013 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1014 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
1015 SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]1016 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1017 SUNXI_FUNCTION(0x0, "gpio_in"),
1018 SUNXI_FUNCTION(0x1, "gpio_out"),
1019 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1020 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
1021 SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]1022 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1023 SUNXI_FUNCTION(0x0, "gpio_in"),
1024 SUNXI_FUNCTION(0x1, "gpio_out"),
1025 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
1026 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
1027 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
Maxime Ripardd10acc62014-04-24 16:06:52 +0200[diff] [blame]1028 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1029 SUNXI_FUNCTION(0x0, "gpio_in"),
1030 SUNXI_FUNCTION(0x1, "gpio_out"),
1031 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
1032 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
1033 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
1034};
1035
Maxime Ripard23ac6df2013-08-04 11:58:45 +0200[diff] [blame]1036static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = {
1037 .pins = sun7i_a20_pins,
1038 .npins = ARRAY_SIZE(sun7i_a20_pins),
1039};
1040
Maxime Ripard25198592014-04-18 20:12:50 +0200[diff] [blame]1041static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
1042{
1043 return sunxi_pinctrl_init(pdev,
1044 &sun7i_a20_pinctrl_data);
1045}
1046
1047static struct of_device_id sun7i_a20_pinctrl_match[] = {
1048 { .compatible = "allwinner,sun7i-a20-pinctrl", },
1049 {}
1050};
1051MODULE_DEVICE_TABLE(of, sun7i_a20_pinctrl_match);
1052
1053static struct platform_driver sun7i_a20_pinctrl_driver = {
1054 .probe = sun7i_a20_pinctrl_probe,
1055 .driver = {
1056 .name = "sun7i-a20-pinctrl",
1057 .owner = THIS_MODULE,
1058 .of_match_table = sun7i_a20_pinctrl_match,
1059 },
1060};
1061module_platform_driver(sun7i_a20_pinctrl_driver);
1062
1063MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
1064MODULE_DESCRIPTION("Allwinner A20 pinctrl driver");
1065MODULE_LICENSE("GPL");