| Catalin Marinas | 4f04d8f | 2012-03-05 11:49:27 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_PGTABLE_HWDEF_H |
| 17 | #define __ASM_PGTABLE_HWDEF_H |
| 18 | |
| 19 | #ifdef CONFIG_ARM64_64K_PAGES |
| 20 | #include <asm/pgtable-2level-hwdef.h> |
| 21 | #else |
| 22 | #include <asm/pgtable-3level-hwdef.h> |
| 23 | #endif |
| 24 | |
| 25 | /* |
| 26 | * Hardware page table definitions. |
| 27 | * |
| 28 | * Level 2 descriptor (PMD). |
| 29 | */ |
| 30 | #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) |
| 31 | #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) |
| 32 | #define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0) |
| 33 | #define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0) |
| 34 | |
| 35 | /* |
| 36 | * Section |
| 37 | */ |
| 38 | #define PMD_SECT_S (_AT(pmdval_t, 3) << 8) |
| 39 | #define PMD_SECT_AF (_AT(pmdval_t, 1) << 10) |
| 40 | #define PMD_SECT_NG (_AT(pmdval_t, 1) << 11) |
| 41 | #define PMD_SECT_XN (_AT(pmdval_t, 1) << 54) |
| 42 | |
| 43 | /* |
| 44 | * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). |
| 45 | */ |
| 46 | #define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2) |
| 47 | #define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2) |
| 48 | |
| 49 | /* |
| 50 | * Level 3 descriptor (PTE). |
| 51 | */ |
| 52 | #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) |
| 53 | #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) |
| 54 | #define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0) |
| 55 | #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ |
| 56 | #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ |
| 57 | #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ |
| 58 | #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ |
| 59 | #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ |
| 60 | #define PTE_XN (_AT(pteval_t, 1) << 54) /* XN */ |
| 61 | |
| 62 | /* |
| 63 | * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers). |
| 64 | */ |
| 65 | #define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2) |
| 66 | #define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2) |
| 67 | |
| 68 | /* |
| 69 | * 40-bit physical address supported. |
| 70 | */ |
| 71 | #define PHYS_MASK_SHIFT (40) |
| 72 | #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) |
| 73 | |
| 74 | /* |
| 75 | * TCR flags. |
| 76 | */ |
| 77 | #define TCR_TxSZ(x) (((UL(64) - (x)) << 16) | ((UL(64) - (x)) << 0)) |
| 78 | #define TCR_IRGN_NC ((UL(0) << 8) | (UL(0) << 24)) |
| 79 | #define TCR_IRGN_WBWA ((UL(1) << 8) | (UL(1) << 24)) |
| 80 | #define TCR_IRGN_WT ((UL(2) << 8) | (UL(2) << 24)) |
| 81 | #define TCR_IRGN_WBnWA ((UL(3) << 8) | (UL(3) << 24)) |
| 82 | #define TCR_IRGN_MASK ((UL(3) << 8) | (UL(3) << 24)) |
| 83 | #define TCR_ORGN_NC ((UL(0) << 10) | (UL(0) << 26)) |
| 84 | #define TCR_ORGN_WBWA ((UL(1) << 10) | (UL(1) << 26)) |
| 85 | #define TCR_ORGN_WT ((UL(2) << 10) | (UL(2) << 26)) |
| 86 | #define TCR_ORGN_WBnWA ((UL(3) << 10) | (UL(3) << 26)) |
| 87 | #define TCR_ORGN_MASK ((UL(3) << 10) | (UL(3) << 26)) |
| 88 | #define TCR_SHARED ((UL(3) << 12) | (UL(3) << 28)) |
| 89 | #define TCR_TG0_64K (UL(1) << 14) |
| 90 | #define TCR_TG1_64K (UL(1) << 30) |
| 91 | #define TCR_IPS_40BIT (UL(2) << 32) |
| 92 | #define TCR_ASID16 (UL(1) << 36) |
| 93 | |
| 94 | #endif |