blob: 3777b805b76ba8645c50c41993f8ba06b550927d [file] [log] [blame]
Shawn Guo69c31b72011-09-06 14:59:40 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <asm/page.h>
16#include <asm/smp_scu.h>
17#include <asm/hardware/gic.h>
18#include <asm/mach/map.h>
Shawn Guo69c31b72011-09-06 14:59:40 +080019
Shawn Guoe3372472012-09-13 21:01:00 +080020#include "common.h"
Shawn Guo50f2de62012-09-14 14:14:45 +080021#include "hardware.h"
Shawn Guoe3372472012-09-13 21:01:00 +080022
Shawn Guo69c31b72011-09-06 14:59:40 +080023static void __iomem *scu_base;
24
25static struct map_desc scu_io_desc __initdata = {
26 /* .virtual and .pfn are run-time assigned */
27 .length = SZ_4K,
28 .type = MT_DEVICE,
29};
30
31void __init imx_scu_map_io(void)
32{
33 unsigned long base;
34
35 /* Get SCU base */
36 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
37
38 scu_io_desc.virtual = IMX_IO_P2V(base);
39 scu_io_desc.pfn = __phys_to_pfn(base);
40 iotable_init(&scu_io_desc, 1);
41
42 scu_base = IMX_IO_ADDRESS(base);
43}
44
Marc Zyngiere4f2d972011-09-08 13:15:22 +010045static void __cpuinit imx_secondary_init(unsigned int cpu)
Shawn Guo69c31b72011-09-06 14:59:40 +080046{
47 /*
48 * if any interrupts are already enabled for the primary
49 * core (e.g. timer irq), then they will not have been enabled
50 * for us: do so
51 */
52 gic_secondary_init(0);
53}
54
Marc Zyngiere4f2d972011-09-08 13:15:22 +010055static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
Shawn Guo69c31b72011-09-06 14:59:40 +080056{
57 imx_set_cpu_jump(cpu, v7_secondary_startup);
58 imx_enable_cpu(cpu, true);
59 return 0;
60}
61
62/*
63 * Initialise the CPU possible map early - this describes the CPUs
64 * which may be present or become present in the system.
65 */
Marc Zyngiere4f2d972011-09-08 13:15:22 +010066static void __init imx_smp_init_cpus(void)
Shawn Guo69c31b72011-09-06 14:59:40 +080067{
68 int i, ncores;
69
70 ncores = scu_get_core_count(scu_base);
71
72 for (i = 0; i < ncores; i++)
73 set_cpu_possible(i, true);
74
75 set_smp_cross_call(gic_raise_softirq);
76}
77
78void imx_smp_prepare(void)
79{
80 scu_enable(scu_base);
81}
82
Marc Zyngiere4f2d972011-09-08 13:15:22 +010083static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
Shawn Guo69c31b72011-09-06 14:59:40 +080084{
85 imx_smp_prepare();
86}
Marc Zyngiere4f2d972011-09-08 13:15:22 +010087
88struct smp_operations imx_smp_ops __initdata = {
89 .smp_init_cpus = imx_smp_init_cpus,
90 .smp_prepare_cpus = imx_smp_prepare_cpus,
91 .smp_secondary_init = imx_secondary_init,
92 .smp_boot_secondary = imx_boot_secondary,
93#ifdef CONFIG_HOTPLUG_CPU
94 .cpu_die = imx_cpu_die,
95#endif
96};