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gerrit-public.fairphone.software / kernel / msm-5.4 / 5182f646c7615ede9a9ba3ecd241f6cbe16829dc / . / drivers / gpu / drm / i915 / i915_oa_sklgt2.c
blob: 9ab9d21ec335a7d77a26c025a65b7d5284d6bdfa [file] [log] [blame]
Robert Bragg5182f642017-06-13 12:23:02 +0100[diff] [blame^]1/*
2 * Autogenerated file by GPU Top : https://github.com/rib/gputop
3 * DO NOT EDIT manually!
4 *
5 *
6 * Copyright (c) 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 *
27 */
28
29#include <linux/sysfs.h>
30
31#include "i915_drv.h"
32#include "i915_oa_sklgt2.h"
33
34enum metric_set_id {
35 METRIC_SET_ID_RENDER_BASIC = 1,
36};
37
38int i915_oa_n_builtin_metric_sets_sklgt2 = 1;
39
40static const struct i915_oa_reg b_counter_config_render_basic[] = {
41 { _MMIO(0x2710), 0x00000000 },
42 { _MMIO(0x2714), 0x00800000 },
43 { _MMIO(0x2720), 0x00000000 },
44 { _MMIO(0x2724), 0x00800000 },
45 { _MMIO(0x2740), 0x00000000 },
46};
47
48static const struct i915_oa_reg flex_eu_config_render_basic[] = {
49 { _MMIO(0xe458), 0x00005004 },
50 { _MMIO(0xe558), 0x00010003 },
51 { _MMIO(0xe658), 0x00012011 },
52 { _MMIO(0xe758), 0x00015014 },
53 { _MMIO(0xe45c), 0x00051050 },
54 { _MMIO(0xe55c), 0x00053052 },
55 { _MMIO(0xe65c), 0x00055054 },
56};
57
58static const struct i915_oa_reg mux_config_render_basic_1_sku_gte_0x02[] = {
59 { _MMIO(0x9888), 0x166c01e0 },
60 { _MMIO(0x9888), 0x12170280 },
61 { _MMIO(0x9888), 0x12370280 },
62 { _MMIO(0x9888), 0x11930317 },
63 { _MMIO(0x9888), 0x159303df },
64 { _MMIO(0x9888), 0x3f900003 },
65 { _MMIO(0x9888), 0x1a4e0080 },
66 { _MMIO(0x9888), 0x0a6c0053 },
67 { _MMIO(0x9888), 0x106c0000 },
68 { _MMIO(0x9888), 0x1c6c0000 },
69 { _MMIO(0x9888), 0x0a1b4000 },
70 { _MMIO(0x9888), 0x1c1c0001 },
71 { _MMIO(0x9888), 0x002f1000 },
72 { _MMIO(0x9888), 0x042f1000 },
73 { _MMIO(0x9888), 0x004c4000 },
74 { _MMIO(0x9888), 0x0a4c8400 },
75 { _MMIO(0x9888), 0x000d2000 },
76 { _MMIO(0x9888), 0x060d8000 },
77 { _MMIO(0x9888), 0x080da000 },
78 { _MMIO(0x9888), 0x0a0d2000 },
79 { _MMIO(0x9888), 0x0c0f0400 },
80 { _MMIO(0x9888), 0x0e0f6600 },
81 { _MMIO(0x9888), 0x002c8000 },
82 { _MMIO(0x9888), 0x162c2200 },
83 { _MMIO(0x9888), 0x062d8000 },
84 { _MMIO(0x9888), 0x082d8000 },
85 { _MMIO(0x9888), 0x00133000 },
86 { _MMIO(0x9888), 0x08133000 },
87 { _MMIO(0x9888), 0x00170020 },
88 { _MMIO(0x9888), 0x08170021 },
89 { _MMIO(0x9888), 0x10170000 },
90 { _MMIO(0x9888), 0x0633c000 },
91 { _MMIO(0x9888), 0x0833c000 },
92 { _MMIO(0x9888), 0x06370800 },
93 { _MMIO(0x9888), 0x08370840 },
94 { _MMIO(0x9888), 0x10370000 },
95 { _MMIO(0x9888), 0x0d933031 },
96 { _MMIO(0x9888), 0x0f933e3f },
97 { _MMIO(0x9888), 0x01933d00 },
98 { _MMIO(0x9888), 0x0393073c },
99 { _MMIO(0x9888), 0x0593000e },
100 { _MMIO(0x9888), 0x1d930000 },
101 { _MMIO(0x9888), 0x19930000 },
102 { _MMIO(0x9888), 0x1b930000 },
103 { _MMIO(0x9888), 0x1d900157 },
104 { _MMIO(0x9888), 0x1f900158 },
105 { _MMIO(0x9888), 0x35900000 },
106 { _MMIO(0x9888), 0x2b908000 },
107 { _MMIO(0x9888), 0x2d908000 },
108 { _MMIO(0x9888), 0x2f908000 },
109 { _MMIO(0x9888), 0x31908000 },
110 { _MMIO(0x9888), 0x15908000 },
111 { _MMIO(0x9888), 0x17908000 },
112 { _MMIO(0x9888), 0x19908000 },
113 { _MMIO(0x9888), 0x1b908000 },
114 { _MMIO(0x9888), 0x1190001f },
115 { _MMIO(0x9888), 0x51904400 },
116 { _MMIO(0x9888), 0x41900020 },
117 { _MMIO(0x9888), 0x55900000 },
118 { _MMIO(0x9888), 0x45900c21 },
119 { _MMIO(0x9888), 0x47900061 },
120 { _MMIO(0x9888), 0x57904440 },
121 { _MMIO(0x9888), 0x49900000 },
122 { _MMIO(0x9888), 0x37900000 },
123 { _MMIO(0x9888), 0x33900000 },
124 { _MMIO(0x9888), 0x4b900000 },
125 { _MMIO(0x9888), 0x59900004 },
126 { _MMIO(0x9888), 0x43900000 },
127 { _MMIO(0x9888), 0x53904444 },
128};
129
130static int
131get_render_basic_mux_config(struct drm_i915_private *dev_priv,
132 const struct i915_oa_reg **regs,
133 int *lens)
134{
135 int n = 0;
136
137 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
138 BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
139
140 if (dev_priv->drm.pdev->revision >= 0x02) {
141 regs[n] = mux_config_render_basic_1_sku_gte_0x02;
142 lens[n] = ARRAY_SIZE(mux_config_render_basic_1_sku_gte_0x02);
143 n++;
144 }
145
146 return n;
147}
148
149int i915_oa_select_metric_set_sklgt2(struct drm_i915_private *dev_priv)
150{
151 dev_priv->perf.oa.n_mux_configs = 0;
152 dev_priv->perf.oa.b_counter_regs = NULL;
153 dev_priv->perf.oa.b_counter_regs_len = 0;
154 dev_priv->perf.oa.flex_regs = NULL;
155 dev_priv->perf.oa.flex_regs_len = 0;
156
157 switch (dev_priv->perf.oa.metrics_set) {
158 case METRIC_SET_ID_RENDER_BASIC:
159 dev_priv->perf.oa.n_mux_configs =
160 get_render_basic_mux_config(dev_priv,
161 dev_priv->perf.oa.mux_regs,
162 dev_priv->perf.oa.mux_regs_lens);
163 if (dev_priv->perf.oa.n_mux_configs == 0) {
164 DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
165
166 /* EINVAL because *_register_sysfs already checked this
167 * and so it wouldn't have been advertised to userspace and
168 * so shouldn't have been requested
169 */
170 return -EINVAL;
171 }
172
173 dev_priv->perf.oa.b_counter_regs =
174 b_counter_config_render_basic;
175 dev_priv->perf.oa.b_counter_regs_len =
176 ARRAY_SIZE(b_counter_config_render_basic);
177
178 dev_priv->perf.oa.flex_regs =
179 flex_eu_config_render_basic;
180 dev_priv->perf.oa.flex_regs_len =
181 ARRAY_SIZE(flex_eu_config_render_basic);
182
183 return 0;
184 default:
185 return -ENODEV;
186 }
187}
188
189static ssize_t
190show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
191{
192 return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
193}
194
195static struct device_attribute dev_attr_render_basic_id = {
196 .attr = { .name = "id", .mode = 0444 },
197 .show = show_render_basic_id,
198 .store = NULL,
199};
200
201static struct attribute *attrs_render_basic[] = {
202 &dev_attr_render_basic_id.attr,
203 NULL,
204};
205
206static struct attribute_group group_render_basic = {
207 .name = "f519e481-24d2-4d42-87c9-3fdd12c00202",
208 .attrs = attrs_render_basic,
209};
210
211int
212i915_perf_register_sysfs_sklgt2(struct drm_i915_private *dev_priv)
213{
214 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
215 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
216 int ret = 0;
217
218 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
219 ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
220 if (ret)
221 goto error_render_basic;
222 }
223
224 return 0;
225
226error_render_basic:
227 return ret;
228}
229
230void
231i915_perf_unregister_sysfs_sklgt2(struct drm_i915_private *dev_priv)
232{
233 const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
234 int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
235
236 if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
237 sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
238}