Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 1 | #ifndef _ASM_POWERPC_MMU_H_ |
| 2 | #define _ASM_POWERPC_MMU_H_ |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 3 | #ifdef __KERNEL__ |
Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 4 | |
Benjamin Herrenschmidt | cd3db0c | 2010-07-06 15:39:02 -0700 | [diff] [blame] | 5 | #include <linux/types.h> |
| 6 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 7 | #include <asm/asm-compat.h> |
| 8 | #include <asm/feature-fixups.h> |
| 9 | |
| 10 | /* |
| 11 | * MMU features bit definitions |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * First half is MMU families |
| 16 | */ |
| 17 | #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) |
| 18 | #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) |
| 19 | #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) |
| 20 | #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) |
| 21 | #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) |
Michael Ellerman | cd68098 | 2014-07-08 17:10:45 +1000 | [diff] [blame] | 22 | #define MMU_FTR_TYPE_47x ASM_CONST(0x00000020) |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * This is individual features |
| 26 | */ |
| 27 | |
| 28 | /* Enable use of high BAT registers */ |
| 29 | #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) |
| 30 | |
| 31 | /* Enable >32-bit physical addresses on 32-bit processor, only used |
| 32 | * by CONFIG_6xx currently as BookE supports that from day 1 |
| 33 | */ |
| 34 | #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) |
| 35 | |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 36 | /* Enable use of broadcast TLB invalidations. We don't always set it |
| 37 | * on processors that support it due to other constraints with the |
| 38 | * use of such invalidations |
| 39 | */ |
| 40 | #define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000) |
| 41 | |
Kumar Gala | c307195 | 2009-02-10 22:26:06 -0600 | [diff] [blame] | 42 | /* Enable use of tlbilx invalidate instructions. |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 43 | */ |
Kumar Gala | c307195 | 2009-02-10 22:26:06 -0600 | [diff] [blame] | 44 | #define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000) |
Benjamin Herrenschmidt | f048aac | 2008-12-18 19:13:38 +0000 | [diff] [blame] | 45 | |
| 46 | /* This indicates that the processor cannot handle multiple outstanding |
| 47 | * broadcast tlbivax or tlbsync. This makes the code use a spinlock |
| 48 | * around such invalidate forms. |
| 49 | */ |
| 50 | #define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000) |
| 51 | |
Kumar Gala | 2319f12 | 2009-03-19 03:55:41 +0000 | [diff] [blame] | 52 | /* This indicates that the processor doesn't handle way selection |
| 53 | * properly and needs SW to track and update the LRU state. This |
| 54 | * is specific to an errata on e300c2/c3/c4 class parts |
| 55 | */ |
| 56 | #define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000) |
| 57 | |
Kumar Gala | df5d6ec | 2009-08-24 15:52:48 +0000 | [diff] [blame] | 58 | /* Enable use of TLB reservation. Processor should support tlbsrx. |
| 59 | * instruction and MAS0[WQ]. |
| 60 | */ |
| 61 | #define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000) |
| 62 | |
| 63 | /* Use paired MAS registers (MAS7||MAS3, etc.) |
| 64 | */ |
| 65 | #define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000) |
| 66 | |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 67 | /* Doesn't support the B bit (1T segment) in SLBIE |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 68 | */ |
Michael Ellerman | 13b3d13 | 2014-07-10 12:29:20 +1000 | [diff] [blame] | 69 | #define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000) |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 70 | |
| 71 | /* Support 16M large pages |
| 72 | */ |
| 73 | #define MMU_FTR_16M_PAGE ASM_CONST(0x04000000) |
| 74 | |
| 75 | /* Supports TLBIEL variant |
| 76 | */ |
| 77 | #define MMU_FTR_TLBIEL ASM_CONST(0x08000000) |
| 78 | |
| 79 | /* Supports tlbies w/o locking |
| 80 | */ |
| 81 | #define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000) |
| 82 | |
| 83 | /* Large pages can be marked CI |
| 84 | */ |
| 85 | #define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000) |
| 86 | |
| 87 | /* 1T segments available |
| 88 | */ |
| 89 | #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000) |
| 90 | |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 91 | /* MMU feature bit sets for various CPUs */ |
| 92 | #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \ |
| 93 | MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2 |
| 94 | #define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2 |
| 95 | #define MMU_FTRS_PPC970 MMU_FTRS_POWER4 |
| 96 | #define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
| 97 | #define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
Michael Neuling | a32e252 | 2011-04-06 18:23:29 +0000 | [diff] [blame] | 98 | #define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
Michael Neuling | 71e1849 | 2012-10-30 19:34:15 +0000 | [diff] [blame] | 99 | #define MMU_FTRS_POWER8 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
Michael Neuling | c3ab300 | 2016-02-19 11:16:24 +1100 | [diff] [blame] | 100 | #define MMU_FTRS_POWER9 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE |
Matt Evans | 44ae3ab | 2011-04-06 19:48:50 +0000 | [diff] [blame] | 101 | #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ |
| 102 | MMU_FTR_CI_LARGE_PAGE |
| 103 | #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \ |
| 104 | MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 105 | #ifndef __ASSEMBLY__ |
| 106 | #include <asm/cputable.h> |
| 107 | |
Becky Bruce | 3160b09 | 2011-06-28 14:54:47 -0500 | [diff] [blame] | 108 | #ifdef CONFIG_PPC_FSL_BOOK3E |
| 109 | #include <asm/percpu.h> |
| 110 | DECLARE_PER_CPU(int, next_tlbcam_idx); |
| 111 | #endif |
| 112 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 113 | static inline int mmu_has_feature(unsigned long feature) |
| 114 | { |
| 115 | return (cur_cpu_spec->mmu_features & feature); |
| 116 | } |
| 117 | |
Dave Kleikamp | 91b191c | 2011-07-04 18:38:03 +0000 | [diff] [blame] | 118 | static inline void mmu_clear_feature(unsigned long feature) |
| 119 | { |
| 120 | cur_cpu_spec->mmu_features &= ~feature; |
| 121 | } |
| 122 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 123 | extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; |
| 124 | |
Dave Kleikamp | 91b191c | 2011-07-04 18:38:03 +0000 | [diff] [blame] | 125 | /* MMU initialization */ |
Benjamin Herrenschmidt | 757c74d | 2009-03-19 19:34:16 +0000 | [diff] [blame] | 126 | extern void early_init_mmu(void); |
| 127 | extern void early_init_mmu_secondary(void); |
| 128 | |
Benjamin Herrenschmidt | cd3db0c | 2010-07-06 15:39:02 -0700 | [diff] [blame] | 129 | extern void setup_initial_memory_limit(phys_addr_t first_memblock_base, |
| 130 | phys_addr_t first_memblock_size); |
| 131 | |
| 132 | #ifdef CONFIG_PPC64 |
| 133 | /* This is our real memory area size on ppc64 server, on embedded, we |
| 134 | * make it match the size our of bolted TLB area |
| 135 | */ |
| 136 | extern u64 ppc64_rma_size; |
| 137 | #endif /* CONFIG_PPC64 */ |
| 138 | |
Aneesh Kumar K.V | 78f1dbd | 2012-09-10 02:52:57 +0000 | [diff] [blame] | 139 | struct mm_struct; |
| 140 | #ifdef CONFIG_DEBUG_VM |
| 141 | extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr); |
| 142 | #else /* CONFIG_DEBUG_VM */ |
| 143 | static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr) |
| 144 | { |
| 145 | } |
| 146 | #endif /* !CONFIG_DEBUG_VM */ |
| 147 | |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 148 | #endif /* !__ASSEMBLY__ */ |
| 149 | |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 150 | /* The kernel use the constants below to index in the page sizes array. |
| 151 | * The use of fixed constants for this purpose is better for performances |
| 152 | * of the low level hash refill handlers. |
| 153 | * |
| 154 | * A non supported page size has a "shift" field set to 0 |
| 155 | * |
| 156 | * Any new page size being implemented can get a new entry in here. Whether |
| 157 | * the kernel will use it or not is a different matter though. The actual page |
| 158 | * size used by hugetlbfs is not defined here and may be made variable |
| 159 | * |
| 160 | * Note: This array ended up being a false good idea as it's growing to the |
| 161 | * point where I wonder if we should replace it with something different, |
| 162 | * to think about, feedback welcome. --BenH. |
| 163 | */ |
| 164 | |
Scott Wood | a8b91e4 | 2012-06-14 13:40:55 +0000 | [diff] [blame] | 165 | /* These are #defines as they have to be used in assembly */ |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 166 | #define MMU_PAGE_4K 0 |
| 167 | #define MMU_PAGE_16K 1 |
| 168 | #define MMU_PAGE_64K 2 |
| 169 | #define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */ |
| 170 | #define MMU_PAGE_256K 4 |
| 171 | #define MMU_PAGE_1M 5 |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 172 | #define MMU_PAGE_2M 6 |
| 173 | #define MMU_PAGE_4M 7 |
| 174 | #define MMU_PAGE_8M 8 |
| 175 | #define MMU_PAGE_16M 9 |
| 176 | #define MMU_PAGE_64M 10 |
| 177 | #define MMU_PAGE_256M 11 |
| 178 | #define MMU_PAGE_1G 12 |
| 179 | #define MMU_PAGE_16G 13 |
| 180 | #define MMU_PAGE_64G 14 |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 181 | |
Scott Wood | 28efc35 | 2013-10-11 19:22:38 -0500 | [diff] [blame] | 182 | #define MMU_PAGE_COUNT 15 |
Benjamin Herrenschmidt | 7c03d65 | 2008-12-18 19:13:32 +0000 | [diff] [blame] | 183 | |
Aneesh Kumar K.V | 11a6f6a | 2016-04-29 23:25:41 +1000 | [diff] [blame] | 184 | #ifdef CONFIG_PPC_BOOK3S_64 |
| 185 | #include <asm/book3s/64/mmu.h> |
| 186 | #else /* CONFIG_PPC_BOOK3S_64 */ |
| 187 | |
| 188 | #endif |
| 189 | |
| 190 | #if defined(CONFIG_PPC_STD_MMU_32) |
David Gibson | 4db68bf | 2007-06-13 14:52:54 +1000 | [diff] [blame] | 191 | /* 32-bit classic hash table MMU */ |
Aneesh Kumar K.V | f64e808 | 2016-03-01 12:59:20 +0530 | [diff] [blame] | 192 | #include <asm/book3s/32/mmu-hash.h> |
Josh Boyer | 4d922c8 | 2007-08-20 07:28:48 -0500 | [diff] [blame] | 193 | #elif defined(CONFIG_40x) |
| 194 | /* 40x-style software loaded TLB */ |
| 195 | # include <asm/mmu-40x.h> |
David Gibson | 57d7909 | 2007-04-30 14:06:25 +1000 | [diff] [blame] | 196 | #elif defined(CONFIG_44x) |
| 197 | /* 44x-style software loaded TLB */ |
| 198 | # include <asm/mmu-44x.h> |
Kumar Gala | 70fe3af | 2009-02-12 16:12:40 -0600 | [diff] [blame] | 199 | #elif defined(CONFIG_PPC_BOOK3E_MMU) |
| 200 | /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ |
| 201 | # include <asm/mmu-book3e.h> |
David Gibson | 3120234 | 2007-06-22 14:58:55 +1000 | [diff] [blame] | 202 | #elif defined (CONFIG_PPC_8xx) |
| 203 | /* Motorola/Freescale 8xx software loaded TLB */ |
| 204 | # include <asm/mmu-8xx.h> |
David Gibson | 1f8d419 | 2005-05-05 16:15:13 -0700 | [diff] [blame] | 205 | #endif |
David Gibson | 1f8d419 | 2005-05-05 16:15:13 -0700 | [diff] [blame] | 206 | |
Aneesh Kumar K.V | 566ca99 | 2016-04-29 23:25:53 +1000 | [diff] [blame^] | 207 | #ifndef radix_enabled |
| 208 | #define radix_enabled() (0) |
| 209 | #endif |
Benjamin Herrenschmidt | 57e2a99 | 2009-07-28 11:59:34 +1000 | [diff] [blame] | 210 | |
Arnd Bergmann | 88ced03 | 2005-12-16 22:43:46 +0100 | [diff] [blame] | 211 | #endif /* __KERNEL__ */ |
Paul Mackerras | 047ea78 | 2005-11-19 20:17:32 +1100 | [diff] [blame] | 212 | #endif /* _ASM_POWERPC_MMU_H_ */ |