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Yuval Mintze712d522015-10-26 11:02:27 +02001/* QLogic qede NIC Driver
2* Copyright (c) 2015 QLogic Corporation
3*
4* This software is available under the terms of the GNU General Public License
5* (GPL) Version 2, available from the file COPYING in the main directory of
6* this source tree.
7*/
8
9#ifndef _QEDE_H_
10#define _QEDE_H_
11#include <linux/compiler.h>
12#include <linux/version.h>
13#include <linux/workqueue.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/bitmap.h>
17#include <linux/kernel.h>
18#include <linux/mutex.h>
19#include <linux/io.h>
20#include <linux/qed/common_hsi.h>
21#include <linux/qed/eth_common.h>
22#include <linux/qed/qed_if.h>
23#include <linux/qed/qed_chain.h>
24#include <linux/qed/qed_eth_if.h>
25
26#define QEDE_MAJOR_VERSION 8
Manish Chopra831a8e62016-06-30 02:35:22 -040027#define QEDE_MINOR_VERSION 10
Yuval Mintz05fafbf2016-08-19 09:33:31 +030028#define QEDE_REVISION_VERSION 9
Yuval Mintz7c2d7d72016-04-10 12:43:02 +030029#define QEDE_ENGINEERING_VERSION 20
Yuval Mintze712d522015-10-26 11:02:27 +020030#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
31 __stringify(QEDE_MINOR_VERSION) "." \
32 __stringify(QEDE_REVISION_VERSION) "." \
33 __stringify(QEDE_ENGINEERING_VERSION)
34
Yuval Mintze712d522015-10-26 11:02:27 +020035#define DRV_MODULE_SYM qede
36
Sudarsana Kalluru133fac02015-10-26 11:02:34 +020037struct qede_stats {
38 u64 no_buff_discards;
Sudarsana Reddy Kalluru1a5a3662016-08-16 10:51:01 -040039 u64 packet_too_big_discard;
40 u64 ttl0_discard;
Sudarsana Kalluru133fac02015-10-26 11:02:34 +020041 u64 rx_ucast_bytes;
42 u64 rx_mcast_bytes;
43 u64 rx_bcast_bytes;
44 u64 rx_ucast_pkts;
45 u64 rx_mcast_pkts;
46 u64 rx_bcast_pkts;
47 u64 mftag_filter_discards;
48 u64 mac_filter_discards;
49 u64 tx_ucast_bytes;
50 u64 tx_mcast_bytes;
51 u64 tx_bcast_bytes;
52 u64 tx_ucast_pkts;
53 u64 tx_mcast_pkts;
54 u64 tx_bcast_pkts;
55 u64 tx_err_drop_pkts;
56 u64 coalesced_pkts;
57 u64 coalesced_events;
58 u64 coalesced_aborts_num;
59 u64 non_coalesced_pkts;
60 u64 coalesced_bytes;
61
62 /* port */
63 u64 rx_64_byte_packets;
Yuval Mintzd4967cf2016-04-22 08:41:01 +030064 u64 rx_65_to_127_byte_packets;
65 u64 rx_128_to_255_byte_packets;
66 u64 rx_256_to_511_byte_packets;
67 u64 rx_512_to_1023_byte_packets;
68 u64 rx_1024_to_1518_byte_packets;
69 u64 rx_1519_to_1522_byte_packets;
70 u64 rx_1519_to_2047_byte_packets;
71 u64 rx_2048_to_4095_byte_packets;
72 u64 rx_4096_to_9216_byte_packets;
73 u64 rx_9217_to_16383_byte_packets;
Sudarsana Kalluru133fac02015-10-26 11:02:34 +020074 u64 rx_crc_errors;
75 u64 rx_mac_crtl_frames;
76 u64 rx_pause_frames;
77 u64 rx_pfc_frames;
78 u64 rx_align_errors;
79 u64 rx_carrier_errors;
80 u64 rx_oversize_packets;
81 u64 rx_jabbers;
82 u64 rx_undersize_packets;
83 u64 rx_fragments;
84 u64 tx_64_byte_packets;
85 u64 tx_65_to_127_byte_packets;
86 u64 tx_128_to_255_byte_packets;
87 u64 tx_256_to_511_byte_packets;
88 u64 tx_512_to_1023_byte_packets;
89 u64 tx_1024_to_1518_byte_packets;
90 u64 tx_1519_to_2047_byte_packets;
91 u64 tx_2048_to_4095_byte_packets;
92 u64 tx_4096_to_9216_byte_packets;
93 u64 tx_9217_to_16383_byte_packets;
94 u64 tx_pause_frames;
95 u64 tx_pfc_frames;
96 u64 tx_lpi_entry_count;
97 u64 tx_total_collisions;
98 u64 brb_truncates;
99 u64 brb_discards;
100 u64 tx_mac_ctrl_frames;
101};
102
Sudarsana Reddy Kalluru7c1bfca2016-02-18 17:00:40 +0200103struct qede_vlan {
104 struct list_head list;
105 u16 vid;
106 bool configured;
107};
108
Ram Amranicee9fbd2016-10-01 21:59:56 +0300109struct qede_rdma_dev {
110 struct qedr_dev *qedr_dev;
111 struct list_head entry;
112 struct list_head roce_event_list;
113 struct workqueue_struct *roce_wq;
114};
115
Yuval Mintze712d522015-10-26 11:02:27 +0200116struct qede_dev {
117 struct qed_dev *cdev;
118 struct net_device *ndev;
119 struct pci_dev *pdev;
120
121 u32 dp_module;
122 u8 dp_level;
123
Yuval Mintzfefb0202016-05-11 16:36:19 +0300124 u32 flags;
125#define QEDE_FLAG_IS_VF BIT(0)
126#define IS_VF(edev) (!!((edev)->flags & QEDE_FLAG_IS_VF))
127
Yuval Mintze712d522015-10-26 11:02:27 +0200128 const struct qed_eth_ops *ops;
129
Mintz, Yuval80439a12016-11-29 16:47:02 +0200130 struct qed_dev_eth_info dev_info;
Yuval Mintze712d522015-10-26 11:02:27 +0200131#define QEDE_MAX_RSS_CNT(edev) ((edev)->dev_info.num_queues)
Mintz, Yuval80439a12016-11-29 16:47:02 +0200132#define QEDE_MAX_TSS_CNT(edev) ((edev)->dev_info.num_queues)
Yuval Mintze712d522015-10-26 11:02:27 +0200133
Yuval Mintz29502192015-10-26 11:02:29 +0200134 struct qede_fastpath *fp_array;
Sudarsana Reddy Kalluru9a4d7e82016-08-23 10:56:55 -0400135 u8 req_num_tx;
136 u8 fp_num_tx;
137 u8 req_num_rx;
138 u8 fp_num_rx;
139 u16 req_queues;
140 u16 num_queues;
Sudarsana Reddy Kalluru9a4d7e82016-08-23 10:56:55 -0400141#define QEDE_QUEUE_CNT(edev) ((edev)->num_queues)
142#define QEDE_RSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_tx)
Mintz, Yuval80439a12016-11-29 16:47:02 +0200143#define QEDE_TSS_COUNT(edev) ((edev)->num_queues - (edev)->fp_num_rx)
Yuval Mintze712d522015-10-26 11:02:27 +0200144
145 struct qed_int_info int_info;
146 unsigned char primary_mac[ETH_ALEN];
147
148 /* Smaller private varaiant of the RTNL lock */
149 struct mutex qede_lock;
150 u32 state; /* Protected by qede_lock */
Yuval Mintz29502192015-10-26 11:02:29 +0200151 u16 rx_buf_size;
Manish Chopra3d789992016-06-30 02:35:21 -0400152 u32 rx_copybreak;
153
Yuval Mintz29502192015-10-26 11:02:29 +0200154 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
155#define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
156 /* Max supported alignment is 256 (8 shift)
157 * minimal alignment shift 6 is optimal for 57xxx HW performance
158 */
159#define QEDE_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
160 /* We assume skb_build() uses sizeof(struct skb_shared_info) bytes
161 * at the end of skb->data, to avoid wasting a full cache line.
162 * This reduces memory use (skb->truesize).
163 */
164#define QEDE_FW_RX_ALIGN_END \
165 max_t(u64, 1UL << QEDE_RX_ALIGN_SHIFT, \
166 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
167
Sudarsana Kalluru133fac02015-10-26 11:02:34 +0200168 struct qede_stats stats;
Sudarsana Reddy Kalluru961acde2016-04-10 12:43:01 +0300169#define QEDE_RSS_INDIR_INITED BIT(0)
170#define QEDE_RSS_KEY_INITED BIT(1)
171#define QEDE_RSS_CAPS_INITED BIT(2)
172 u32 rss_params_inited; /* bit-field to track initialized rss params */
Yuval Mintz29502192015-10-26 11:02:29 +0200173 struct qed_update_vport_rss_params rss_params;
174 u16 q_num_rx_buffers; /* Must be a power of two */
175 u16 q_num_tx_buffers; /* Must be a power of two */
Sudarsana Kalluru0d8e0aa2015-10-26 11:02:30 +0200176
Manish Chopra55482ed2016-03-04 12:35:06 -0500177 bool gro_disable;
Sudarsana Reddy Kalluru7c1bfca2016-02-18 17:00:40 +0200178 struct list_head vlan_list;
179 u16 configured_vlans;
180 u16 non_configured_vlans;
181 bool accept_any_vlan;
Sudarsana Kalluru0d8e0aa2015-10-26 11:02:30 +0200182 struct delayed_work sp_task;
183 unsigned long sp_flags;
Manish Choprab18e1702016-04-14 01:38:30 -0400184 u16 vxlan_dst_port;
Manish Chopra9a109dd2016-04-14 01:38:31 -0400185 u16 geneve_dst_port;
Ram Amranicee9fbd2016-10-01 21:59:56 +0300186
Mintz, Yuval14d39642016-10-31 07:14:23 +0200187 bool wol_enabled;
188
Ram Amranicee9fbd2016-10-01 21:59:56 +0300189 struct qede_rdma_dev rdma_info;
Yuval Mintz29502192015-10-26 11:02:29 +0200190};
191
192enum QEDE_STATE {
193 QEDE_STATE_CLOSED,
194 QEDE_STATE_OPEN,
195};
196
197#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
198
199#define MAX_NUM_TC 8
200#define MAX_NUM_PRI 8
201
202/* The driver supports the new build_skb() API:
203 * RX ring buffer contains pointer to kmalloc() data only,
204 * skb are built only after the frame was DMA-ed.
205 */
206struct sw_rx_data {
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500207 struct page *data;
208 dma_addr_t mapping;
209 unsigned int page_offset;
Yuval Mintz29502192015-10-26 11:02:29 +0200210};
211
Manish Chopra55482ed2016-03-04 12:35:06 -0500212enum qede_agg_state {
213 QEDE_AGG_STATE_NONE = 0,
214 QEDE_AGG_STATE_START = 1,
215 QEDE_AGG_STATE_ERROR = 2
216};
217
218struct qede_agg_info {
Mintz, Yuval01e23012016-11-29 16:47:00 +0200219 /* rx_buf is a data buffer that can be placed / consumed from rx bd
220 * chain. It has two purposes: We will preallocate the data buffer
221 * for each aggregation when we open the interface and will place this
222 * buffer on the rx-bd-ring when we receive TPA_START. We don't want
223 * to be in a state where allocation fails, as we can't reuse the
224 * consumer buffer in the rx-chain since FW may still be writing to it
225 * (since header needs to be modified for TPA).
226 * The second purpose is to keep a pointer to the bd buffer during
227 * aggregation.
228 */
229 struct sw_rx_data buffer;
230 dma_addr_t buffer_mapping;
231
Manish Chopra55482ed2016-03-04 12:35:06 -0500232 struct sk_buff *skb;
Mintz, Yuval01e23012016-11-29 16:47:00 +0200233
234 /* We need some structs from the start cookie until termination */
Manish Chopra55482ed2016-03-04 12:35:06 -0500235 u16 vlan_tag;
Mintz, Yuval01e23012016-11-29 16:47:00 +0200236 u16 start_cqe_bd_len;
237 u8 start_cqe_placement_offset;
238
239 u8 state;
240 u8 frag_id;
241
242 u8 tunnel_type;
Manish Chopra55482ed2016-03-04 12:35:06 -0500243};
244
Yuval Mintz29502192015-10-26 11:02:29 +0200245struct qede_rx_queue {
246 __le16 *hw_cons_ptr;
247 struct sw_rx_data *sw_rx_ring;
248 u16 sw_rx_cons;
249 u16 sw_rx_prod;
250 struct qed_chain rx_bd_ring;
251 struct qed_chain rx_comp_ring;
252 void __iomem *hw_rxq_prod_addr;
253
Manish Chopra55482ed2016-03-04 12:35:06 -0500254 /* GRO */
255 struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM];
256
Yuval Mintz29502192015-10-26 11:02:29 +0200257 int rx_buf_size;
Yuval Mintzfc48b7a2016-02-15 13:22:35 -0500258 unsigned int rx_buf_seg_size;
Yuval Mintz29502192015-10-26 11:02:29 +0200259
260 u16 num_rx_buffers;
261 u16 rxq_id;
262
Sudarsana Reddy Kalluru68db9ec2016-08-16 10:51:02 -0400263 u64 rcv_pkts;
Yuval Mintz29502192015-10-26 11:02:29 +0200264 u64 rx_hw_errors;
265 u64 rx_alloc_errors;
Manish Choprac72a6122016-06-30 02:35:18 -0400266 u64 rx_ip_frags;
Yuval Mintz29502192015-10-26 11:02:29 +0200267};
268
269union db_prod {
270 struct eth_db_data data;
271 u32 raw;
272};
273
274struct sw_tx_bd {
275 struct sk_buff *skb;
276 u8 flags;
277/* Set on the first BD descriptor when there is a split BD */
278#define QEDE_TSO_SPLIT_BD BIT(0)
279};
280
281struct qede_tx_queue {
282 int index; /* Queue index */
283 __le16 *hw_cons_ptr;
284 struct sw_tx_bd *sw_tx_ring;
285 u16 sw_tx_cons;
286 u16 sw_tx_prod;
287 struct qed_chain tx_pbl;
288 void __iomem *doorbell_addr;
289 union db_prod tx_db;
290
291 u16 num_tx_buffers;
Sudarsana Reddy Kalluru68db9ec2016-08-16 10:51:02 -0400292 u64 xmit_pkts;
293 u64 stopped_cnt;
Yuval Mintzd8c2c7e2016-08-22 13:25:11 +0300294
295 bool is_legacy;
Yuval Mintz29502192015-10-26 11:02:29 +0200296};
297
298#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr.hi), \
299 le32_to_cpu((bd)->addr.lo))
300#define BD_SET_UNMAP_ADDR_LEN(bd, maddr, len) \
301 do { \
302 (bd)->addr.hi = cpu_to_le32(upper_32_bits(maddr)); \
303 (bd)->addr.lo = cpu_to_le32(lower_32_bits(maddr)); \
304 (bd)->nbytes = cpu_to_le16(len); \
305 } while (0)
306#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
307
308struct qede_fastpath {
309 struct qede_dev *edev;
Sudarsana Reddy Kalluru9a4d7e82016-08-23 10:56:55 -0400310#define QEDE_FASTPATH_TX BIT(0)
311#define QEDE_FASTPATH_RX BIT(1)
312#define QEDE_FASTPATH_COMBINED (QEDE_FASTPATH_TX | QEDE_FASTPATH_RX)
313 u8 type;
314 u8 id;
Yuval Mintz29502192015-10-26 11:02:29 +0200315 struct napi_struct napi;
316 struct qed_sb_info *sb_info;
317 struct qede_rx_queue *rxq;
Mintz, Yuval80439a12016-11-29 16:47:02 +0200318 struct qede_tx_queue *txq;
Yuval Mintz29502192015-10-26 11:02:29 +0200319
320#define VEC_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
321 char name[VEC_NAME_SIZE];
Yuval Mintze712d522015-10-26 11:02:27 +0200322};
323
324/* Debug print definitions */
325#define DP_NAME(edev) ((edev)->ndev->name)
326
Yuval Mintz29502192015-10-26 11:02:29 +0200327#define XMIT_PLAIN 0
328#define XMIT_L4_CSUM BIT(0)
329#define XMIT_LSO BIT(1)
330#define XMIT_ENC BIT(2)
Manish Chopraa1502412016-10-14 05:19:18 -0400331#define XMIT_ENC_GSO_L4_CSUM BIT(3)
Yuval Mintz29502192015-10-26 11:02:29 +0200332
333#define QEDE_CSUM_ERROR BIT(0)
334#define QEDE_CSUM_UNNECESSARY BIT(1)
Manish Chopra14db81d2016-04-14 01:38:33 -0400335#define QEDE_TUNN_CSUM_UNNECESSARY BIT(2)
Sudarsana Kalluru0d8e0aa2015-10-26 11:02:30 +0200336
Manish Choprab18e1702016-04-14 01:38:30 -0400337#define QEDE_SP_RX_MODE 1
338#define QEDE_SP_VXLAN_PORT_CONFIG 2
Manish Chopra9a109dd2016-04-14 01:38:31 -0400339#define QEDE_SP_GENEVE_PORT_CONFIG 3
Sudarsana Kalluru0d8e0aa2015-10-26 11:02:30 +0200340
Mintz, Yuval567b3c12016-11-29 16:47:05 +0200341struct qede_reload_args {
342 void (*func)(struct qede_dev *edev, struct qede_reload_args *args);
343 union {
344 netdev_features_t features;
345 u16 mtu;
346 } u;
Sudarsana Kalluru0d8e0aa2015-10-26 11:02:30 +0200347};
348
Sudarsana Reddy Kalluru489e45a2016-06-08 06:22:12 -0400349#ifdef CONFIG_DCB
350void qede_set_dcbnl_ops(struct net_device *ndev);
351#endif
Sudarsana Kalluru133fac02015-10-26 11:02:34 +0200352void qede_config_debug(uint debug, u32 *p_dp_module, u8 *p_dp_level);
353void qede_set_ethtool_ops(struct net_device *netdev);
354void qede_reload(struct qede_dev *edev,
Mintz, Yuval567b3c12016-11-29 16:47:05 +0200355 struct qede_reload_args *args, bool is_locked);
Sudarsana Kalluru133fac02015-10-26 11:02:34 +0200356int qede_change_mtu(struct net_device *dev, int new_mtu);
357void qede_fill_by_demand_stats(struct qede_dev *edev);
Mintz, Yuval567b3c12016-11-29 16:47:05 +0200358void __qede_lock(struct qede_dev *edev);
359void __qede_unlock(struct qede_dev *edev);
Sudarsana Reddy Kalluru16f46bf2016-04-28 20:20:54 -0400360bool qede_has_rx_work(struct qede_rx_queue *rxq);
361int qede_txq_has_work(struct qede_tx_queue *txq);
362void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
363 u8 count);
Sudarsana Reddy Kalluru837d4eb2016-10-21 04:43:41 -0400364void qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq);
Sudarsana Kalluru133fac02015-10-26 11:02:34 +0200365
Yuval Mintz29502192015-10-26 11:02:29 +0200366#define RX_RING_SIZE_POW 13
Sudarsana Kalluru01ef7e02015-11-30 12:25:02 +0200367#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
Yuval Mintz29502192015-10-26 11:02:29 +0200368#define NUM_RX_BDS_MAX (RX_RING_SIZE - 1)
369#define NUM_RX_BDS_MIN 128
Sudarsana Reddy Kalluru0e191822016-10-21 04:43:42 -0400370#define NUM_RX_BDS_DEF ((u16)BIT(10) - 1)
Yuval Mintz29502192015-10-26 11:02:29 +0200371
372#define TX_RING_SIZE_POW 13
Sudarsana Kalluru01ef7e02015-11-30 12:25:02 +0200373#define TX_RING_SIZE ((u16)BIT(TX_RING_SIZE_POW))
Yuval Mintz29502192015-10-26 11:02:29 +0200374#define NUM_TX_BDS_MAX (TX_RING_SIZE - 1)
375#define NUM_TX_BDS_MIN 128
376#define NUM_TX_BDS_DEF NUM_TX_BDS_MAX
377
Jarod Wilsoncaff2a82016-10-17 15:54:08 -0400378#define QEDE_MIN_PKT_LEN 64
379#define QEDE_RX_HDR_SIZE 256
380#define QEDE_MAX_JUMBO_PACKET_SIZE 9600
Sudarsana Reddy Kalluru9a4d7e82016-08-23 10:56:55 -0400381#define for_each_queue(i) for (i = 0; i < edev->num_queues; i++)
Yuval Mintz29502192015-10-26 11:02:29 +0200382
Yuval Mintze712d522015-10-26 11:02:27 +0200383#endif /* _QEDE_H_ */