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Shawn Guo117ccd552013-05-03 11:28:42 +08001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
Anson Huang4291b642014-01-14 17:30:28 +080011#include <dt-bindings/input/input.h>
Shawn Guo117ccd552013-05-03 11:28:42 +080012#include "imx6sl.dtsi"
13
14/ {
15 model = "Freescale i.MX6 SoloLite EVK Board";
16 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
17
18 memory {
19 reg = <0x80000000 0x40000000>;
20 };
Peter Chen60222322013-09-10 10:23:16 +080021
22 regulators {
23 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080024 #address-cells = <1>;
25 #size-cells = <0>;
Peter Chen60222322013-09-10 10:23:16 +080026
Shawn Guo56160e32014-02-07 23:22:50 +080027 reg_usb_otg1_vbus: regulator@0 {
Peter Chen60222322013-09-10 10:23:16 +080028 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080029 reg = <0>;
Peter Chen60222322013-09-10 10:23:16 +080030 regulator-name = "usb_otg1_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 0 0>;
34 enable-active-high;
35 };
36
Shawn Guo56160e32014-02-07 23:22:50 +080037 reg_usb_otg2_vbus: regulator@1 {
Peter Chen60222322013-09-10 10:23:16 +080038 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080039 reg = <1>;
Peter Chen60222322013-09-10 10:23:16 +080040 regulator-name = "usb_otg2_vbus";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 gpio = <&gpio4 2 0>;
44 enable-active-high;
45 };
46 };
Shawn Guo117ccd552013-05-03 11:28:42 +080047};
48
Huang Shijied1b53972013-10-18 10:32:53 +080049&ecspi1 {
50 fsl,spi-num-chipselects = <1>;
51 cs-gpios = <&gpio4 11 0>;
52 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080053 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijied1b53972013-10-18 10:32:53 +080054 status = "okay";
55
56 flash: m25p80@0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "st,m25p32";
60 spi-max-frequency = <20000000>;
61 reg = <0>;
62 };
63};
64
Shawn Guo117ccd552013-05-03 11:28:42 +080065&fec {
66 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080067 pinctrl-0 = <&pinctrl_fec>;
Shawn Guo117ccd552013-05-03 11:28:42 +080068 phy-mode = "rmii";
69 status = "okay";
70};
71
Fabio Estevam56df2682014-02-06 08:57:50 -020072&i2c1 {
73 clock-frequency = <100000>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_i2c1>;
76 status = "okay";
77
78 pmic: pfuze100@08 {
79 compatible = "fsl,pfuze100";
80 reg = <0x08>;
81
82 regulators {
83 sw1a_reg: sw1ab {
84 regulator-min-microvolt = <300000>;
85 regulator-max-microvolt = <1875000>;
86 regulator-boot-on;
87 regulator-always-on;
88 regulator-ramp-delay = <6250>;
89 };
90
91 sw1c_reg: sw1c {
92 regulator-min-microvolt = <300000>;
93 regulator-max-microvolt = <1875000>;
94 regulator-boot-on;
95 regulator-always-on;
96 regulator-ramp-delay = <6250>;
97 };
98
99 sw2_reg: sw2 {
100 regulator-min-microvolt = <800000>;
101 regulator-max-microvolt = <3300000>;
102 regulator-boot-on;
103 regulator-always-on;
104 };
105
106 sw3a_reg: sw3a {
107 regulator-min-microvolt = <400000>;
108 regulator-max-microvolt = <1975000>;
109 regulator-boot-on;
110 regulator-always-on;
111 };
112
113 sw3b_reg: sw3b {
114 regulator-min-microvolt = <400000>;
115 regulator-max-microvolt = <1975000>;
116 regulator-boot-on;
117 regulator-always-on;
118 };
119
120 sw4_reg: sw4 {
121 regulator-min-microvolt = <800000>;
122 regulator-max-microvolt = <3300000>;
123 };
124
125 swbst_reg: swbst {
126 regulator-min-microvolt = <5000000>;
127 regulator-max-microvolt = <5150000>;
128 };
129
130 snvs_reg: vsnvs {
131 regulator-min-microvolt = <1000000>;
132 regulator-max-microvolt = <3000000>;
133 regulator-boot-on;
134 regulator-always-on;
135 };
136
137 vref_reg: vrefddr {
138 regulator-boot-on;
139 regulator-always-on;
140 };
141
142 vgen1_reg: vgen1 {
143 regulator-min-microvolt = <800000>;
144 regulator-max-microvolt = <1550000>;
145 };
146
147 vgen2_reg: vgen2 {
148 regulator-min-microvolt = <800000>;
149 regulator-max-microvolt = <1550000>;
150 };
151
152 vgen3_reg: vgen3 {
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <3300000>;
155 };
156
157 vgen4_reg: vgen4 {
158 regulator-min-microvolt = <1800000>;
159 regulator-max-microvolt = <3300000>;
160 regulator-always-on;
161 };
162
163 vgen5_reg: vgen5 {
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <3300000>;
166 regulator-always-on;
167 };
168
169 vgen6_reg: vgen6 {
170 regulator-min-microvolt = <1800000>;
171 regulator-max-microvolt = <3300000>;
172 regulator-always-on;
173 };
174 };
175 };
176};
177
Shawn Guo117ccd552013-05-03 11:28:42 +0800178&iomuxc {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_hog>;
181
Shawn Guofffaa652013-11-04 10:49:04 +0800182 imx6sl-evk {
Shawn Guo117ccd552013-05-03 11:28:42 +0800183 pinctrl_hog: hoggrp {
184 fsl,pins = <
185 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
186 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
187 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
188 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
189 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
Peter Chen60222322013-09-10 10:23:16 +0800190 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
191 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
Shawn Guo117ccd552013-05-03 11:28:42 +0800192 >;
193 };
Shawn Guofffaa652013-11-04 10:49:04 +0800194
195 pinctrl_ecspi1: ecspi1grp {
196 fsl,pins = <
197 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
198 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
199 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
200 >;
201 };
202
203 pinctrl_fec: fecgrp {
204 fsl,pins = <
205 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
206 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
207 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
208 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
209 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
210 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
211 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
212 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
213 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
214 >;
215 };
216
Fabio Estevam56df2682014-02-06 08:57:50 -0200217 pinctrl_i2c1: i2c1grp {
218 fsl,pins = <
219 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
220 MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
221 >;
222 };
223
Anson Huang4291b642014-01-14 17:30:28 +0800224 pinctrl_kpp: kppgrp {
225 fsl,pins = <
226 MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
227 MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
228 MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
229 MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
230 MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
231 MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
232 >;
233 };
234
Shawn Guofffaa652013-11-04 10:49:04 +0800235 pinctrl_uart1: uart1grp {
236 fsl,pins = <
237 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
238 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
239 >;
240 };
241
242 pinctrl_usbotg1: usbotg1grp {
243 fsl,pins = <
244 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
245 >;
246 };
247
248 pinctrl_usdhc1: usdhc1grp {
249 fsl,pins = <
250 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
251 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
252 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
253 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
254 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
255 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
256 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
257 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
258 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
259 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
260 >;
261 };
262
263 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
264 fsl,pins = <
265 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
266 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
267 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
268 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
269 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
270 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
271 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
272 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
273 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
274 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
275 >;
276 };
277
278 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
279 fsl,pins = <
280 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
281 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
282 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
283 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
284 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
285 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
286 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
287 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
288 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
289 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
290 >;
291 };
292
293 pinctrl_usdhc2: usdhc2grp {
294 fsl,pins = <
295 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
296 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
297 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
298 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
299 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
300 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
301 >;
302 };
303
304 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
305 fsl,pins = <
306 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
307 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
308 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
309 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
310 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
311 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
312 >;
313 };
314
315 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
316 fsl,pins = <
317 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
318 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
319 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
320 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
321 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
322 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
323 >;
324 };
325
326 pinctrl_usdhc3: usdhc3grp {
327 fsl,pins = <
328 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
329 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
330 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
331 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
332 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
333 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
334 >;
335 };
336
337 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
338 fsl,pins = <
339 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
340 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
341 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
342 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
343 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
344 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
345 >;
346 };
347
348 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
349 fsl,pins = <
350 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
351 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
352 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
353 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
354 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
355 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
356 >;
357 };
Shawn Guo117ccd552013-05-03 11:28:42 +0800358 };
359};
360
Anson Huang4291b642014-01-14 17:30:28 +0800361&kpp {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_kpp>;
364 linux,keymap = <
365 MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
366 MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
367 MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
368 MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
369 MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
370 MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
371 MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
372 MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
373 >;
374 status = "okay";
375};
376
Shawn Guo117ccd552013-05-03 11:28:42 +0800377&uart1 {
378 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800379 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800380 status = "okay";
381};
382
Peter Chen60222322013-09-10 10:23:16 +0800383&usbotg1 {
384 vbus-supply = <&reg_usb_otg1_vbus>;
385 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800386 pinctrl-0 = <&pinctrl_usbotg1>;
Peter Chen60222322013-09-10 10:23:16 +0800387 disable-over-current;
388 status = "okay";
389};
390
391&usbotg2 {
392 vbus-supply = <&reg_usb_otg2_vbus>;
393 dr_mode = "host";
394 disable-over-current;
395 status = "okay";
396};
397
Shawn Guo117ccd552013-05-03 11:28:42 +0800398&usdhc1 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800399 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800400 pinctrl-0 = <&pinctrl_usdhc1>;
401 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
402 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800403 bus-width = <8>;
404 cd-gpios = <&gpio4 7 0>;
405 wp-gpios = <&gpio4 6 0>;
406 status = "okay";
407};
408
409&usdhc2 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800410 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800411 pinctrl-0 = <&pinctrl_usdhc2>;
412 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
413 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800414 cd-gpios = <&gpio5 0 0>;
415 wp-gpios = <&gpio4 29 0>;
416 status = "okay";
417};
418
419&usdhc3 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800420 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800421 pinctrl-0 = <&pinctrl_usdhc3>;
422 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
423 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800424 cd-gpios = <&gpio3 22 0>;
425 status = "okay";
426};