Marian Balakowicz | 30d992e | 2007-11-10 04:12:20 +1100 | [diff] [blame] | 1 | /* |
| 2 | * TQM5200 board Device Tree Source |
| 3 | * |
| 4 | * Copyright (C) 2007 Semihalf |
| 5 | * Marian Balakowicz <m8@semihalf.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * WARNING: Do not depend on this tree layout remaining static just yet. |
| 15 | * The MPC5200 device tree conventions are still in flux |
| 16 | * Keep an eye on the linuxppc-dev mailing list for more details |
| 17 | */ |
| 18 | |
| 19 | / { |
| 20 | model = "tqc,tqm5200"; |
| 21 | compatible = "tqc,tqm5200"; |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <1>; |
| 24 | |
| 25 | cpus { |
| 26 | #address-cells = <1>; |
| 27 | #size-cells = <0>; |
| 28 | |
| 29 | PowerPC,5200@0 { |
| 30 | device_type = "cpu"; |
| 31 | reg = <0>; |
| 32 | d-cache-line-size = <20>; |
| 33 | i-cache-line-size = <20>; |
| 34 | d-cache-size = <4000>; // L1, 16K |
| 35 | i-cache-size = <4000>; // L1, 16K |
| 36 | timebase-frequency = <0>; // from bootloader |
| 37 | bus-frequency = <0>; // from bootloader |
| 38 | clock-frequency = <0>; // from bootloader |
| 39 | }; |
| 40 | }; |
| 41 | |
| 42 | memory { |
| 43 | device_type = "memory"; |
| 44 | reg = <00000000 04000000>; // 64MB |
| 45 | }; |
| 46 | |
| 47 | soc5200@f0000000 { |
Paul Gortmaker | 58a5be3 | 2008-01-26 07:33:20 +1100 | [diff] [blame^] | 48 | #address-cells = <1>; |
| 49 | #size-cells = <1>; |
Marian Balakowicz | 30d992e | 2007-11-10 04:12:20 +1100 | [diff] [blame] | 50 | model = "fsl,mpc5200"; |
| 51 | compatible = "fsl,mpc5200"; |
| 52 | revision = ""; // from bootloader |
| 53 | device_type = "soc"; |
| 54 | ranges = <0 f0000000 0000c000>; |
| 55 | reg = <f0000000 00000100>; |
| 56 | bus-frequency = <0>; // from bootloader |
| 57 | system-frequency = <0>; // from bootloader |
| 58 | |
| 59 | cdm@200 { |
| 60 | compatible = "mpc5200-cdm"; |
| 61 | reg = <200 38>; |
| 62 | }; |
| 63 | |
| 64 | mpc5200_pic: pic@500 { |
| 65 | // 5200 interrupts are encoded into two levels; |
| 66 | interrupt-controller; |
| 67 | #interrupt-cells = <3>; |
| 68 | compatible = "mpc5200-pic"; |
| 69 | reg = <500 80>; |
| 70 | }; |
| 71 | |
| 72 | gpt@600 { // General Purpose Timer |
| 73 | compatible = "fsl,mpc5200-gpt"; |
| 74 | reg = <600 10>; |
| 75 | interrupts = <1 9 0>; |
| 76 | interrupt-parent = <&mpc5200_pic>; |
| 77 | fsl,has-wdt; |
| 78 | }; |
| 79 | |
| 80 | gpio@b00 { |
| 81 | compatible = "mpc5200-gpio"; |
| 82 | reg = <b00 40>; |
| 83 | interrupts = <1 7 0>; |
| 84 | interrupt-parent = <&mpc5200_pic>; |
| 85 | }; |
| 86 | |
| 87 | usb@1000 { |
| 88 | compatible = "mpc5200-ohci","ohci-be"; |
| 89 | reg = <1000 ff>; |
| 90 | interrupts = <2 6 0>; |
| 91 | interrupt-parent = <&mpc5200_pic>; |
| 92 | }; |
| 93 | |
| 94 | dma-controller@1200 { |
| 95 | compatible = "mpc5200-bestcomm"; |
| 96 | reg = <1200 80>; |
| 97 | interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 |
| 98 | 3 4 0 3 5 0 3 6 0 3 7 0 |
| 99 | 3 8 0 3 9 0 3 a 0 3 b 0 |
| 100 | 3 c 0 3 d 0 3 e 0 3 f 0>; |
| 101 | interrupt-parent = <&mpc5200_pic>; |
| 102 | }; |
| 103 | |
| 104 | xlb@1f00 { |
| 105 | compatible = "mpc5200-xlb"; |
| 106 | reg = <1f00 100>; |
| 107 | }; |
| 108 | |
| 109 | serial@2000 { // PSC1 |
| 110 | device_type = "serial"; |
| 111 | compatible = "mpc5200-psc-uart"; |
| 112 | port-number = <0>; // Logical port assignment |
| 113 | reg = <2000 100>; |
| 114 | interrupts = <2 1 0>; |
| 115 | interrupt-parent = <&mpc5200_pic>; |
| 116 | }; |
| 117 | |
| 118 | serial@2200 { // PSC2 |
| 119 | device_type = "serial"; |
| 120 | compatible = "mpc5200-psc-uart"; |
| 121 | port-number = <1>; // Logical port assignment |
| 122 | reg = <2200 100>; |
| 123 | interrupts = <2 2 0>; |
| 124 | interrupt-parent = <&mpc5200_pic>; |
| 125 | }; |
| 126 | |
| 127 | serial@2400 { // PSC3 |
| 128 | device_type = "serial"; |
| 129 | compatible = "mpc5200-psc-uart"; |
| 130 | port-number = <2>; // Logical port assignment |
| 131 | reg = <2400 100>; |
| 132 | interrupts = <2 3 0>; |
| 133 | interrupt-parent = <&mpc5200_pic>; |
| 134 | }; |
| 135 | |
| 136 | ethernet@3000 { |
| 137 | device_type = "network"; |
| 138 | compatible = "mpc5200-fec"; |
| 139 | reg = <3000 800>; |
| 140 | local-mac-address = [ 00 00 00 00 00 00 ]; /* Filled in by U-Boot */ |
| 141 | interrupts = <2 5 0>; |
| 142 | interrupt-parent = <&mpc5200_pic>; |
| 143 | }; |
| 144 | |
| 145 | ata@3a00 { |
| 146 | compatible = "mpc5200-ata"; |
| 147 | reg = <3a00 100>; |
| 148 | interrupts = <2 7 0>; |
| 149 | interrupt-parent = <&mpc5200_pic>; |
| 150 | }; |
| 151 | |
| 152 | i2c@3d40 { |
| 153 | compatible = "mpc5200-i2c","fsl-i2c"; |
| 154 | reg = <3d40 40>; |
| 155 | interrupts = <2 10 0>; |
| 156 | interrupt-parent = <&mpc5200_pic>; |
| 157 | fsl5200-clocking; |
| 158 | }; |
| 159 | |
| 160 | sram@8000 { |
| 161 | compatible = "mpc5200-sram"; |
| 162 | reg = <8000 4000>; |
| 163 | }; |
| 164 | }; |
| 165 | |
| 166 | pci@f0000d00 { |
| 167 | #interrupt-cells = <1>; |
| 168 | #size-cells = <2>; |
| 169 | #address-cells = <3>; |
| 170 | device_type = "pci"; |
| 171 | compatible = "fsl,mpc5200-pci"; |
| 172 | reg = <f0000d00 100>; |
| 173 | interrupt-map-mask = <f800 0 0 7>; |
| 174 | interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 |
| 175 | c000 0 0 2 &mpc5200_pic 0 0 3 |
| 176 | c000 0 0 3 &mpc5200_pic 0 0 3 |
| 177 | c000 0 0 4 &mpc5200_pic 0 0 3>; |
| 178 | clock-frequency = <0>; // From boot loader |
| 179 | interrupts = <2 8 0 2 9 0 2 a 0>; |
| 180 | interrupt-parent = <&mpc5200_pic>; |
| 181 | bus-range = <0 0>; |
| 182 | ranges = <42000000 0 80000000 80000000 0 10000000 |
| 183 | 02000000 0 90000000 90000000 0 10000000 |
| 184 | 01000000 0 00000000 a0000000 0 01000000>; |
| 185 | }; |
| 186 | }; |