blob: 4b961b1b4252947e8fb9491b0a1493d96d0c2efd [file] [log] [blame]
Marc Dietrichcc2afa42011-11-01 10:37:05 +00001/dts-v1/;
2
Stephen Warren1bd0bd42012-10-17 16:38:21 -06003#include "tegra20.dtsi"
Marc Dietrichcc2afa42011-11-01 10:37:05 +00004
5/ {
6 model = "Toshiba AC100 / Dynabook AZ";
7 compatible = "compal,paz00", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Marc Dietrichcc2afa42011-11-01 10:37:05 +000010 reg = <0x00000000 0x20000000>;
11 };
12
Stephen Warren58ecb232013-11-25 17:53:16 -070013 host1x@50000000 {
14 hdmi@54280000 {
Stephen Warren11a3c862013-01-02 14:53:22 -070015 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -070021 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
22 GPIO_ACTIVE_HIGH>;
Stephen Warren11a3c862013-01-02 14:53:22 -070023 };
24 };
25
Stephen Warren58ecb232013-11-25 17:53:16 -070026 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -060027 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>;
29
30 state_default: pinmux {
31 ata {
32 nvidia,pins = "ata", "atc", "atd", "ate",
33 "dap2", "gmb", "gmc", "gmd", "spia",
34 "spib", "spic", "spid", "spie";
35 nvidia,function = "gmi";
36 };
37 atb {
38 nvidia,pins = "atb", "gma", "gme";
39 nvidia,function = "sdio4";
40 };
41 cdev1 {
42 nvidia,pins = "cdev1";
43 nvidia,function = "plla_out";
44 };
45 cdev2 {
46 nvidia,pins = "cdev2";
47 nvidia,function = "pllp_out4";
48 };
49 crtp {
50 nvidia,pins = "crtp";
51 nvidia,function = "crt";
52 };
53 csus {
54 nvidia,pins = "csus";
55 nvidia,function = "pllc_out1";
56 };
57 dap1 {
58 nvidia,pins = "dap1";
59 nvidia,function = "dap1";
60 };
61 dap3 {
62 nvidia,pins = "dap3";
63 nvidia,function = "dap3";
64 };
65 dap4 {
66 nvidia,pins = "dap4";
67 nvidia,function = "dap4";
68 };
69 ddc {
70 nvidia,pins = "ddc";
71 nvidia,function = "i2c2";
72 };
73 dta {
74 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
75 nvidia,function = "rsvd1";
76 };
77 dtf {
78 nvidia,pins = "dtf";
79 nvidia,function = "i2c3";
80 };
81 gpu {
82 nvidia,pins = "gpu", "sdb", "sdd";
83 nvidia,function = "pwm";
84 };
85 gpu7 {
86 nvidia,pins = "gpu7";
87 nvidia,function = "rtck";
88 };
89 gpv {
90 nvidia,pins = "gpv", "slxa", "slxk";
91 nvidia,function = "pcie";
92 };
93 hdint {
94 nvidia,pins = "hdint", "pta";
95 nvidia,function = "hdmi";
96 };
97 i2cp {
98 nvidia,pins = "i2cp";
99 nvidia,function = "i2cp";
100 };
101 irrx {
102 nvidia,pins = "irrx", "irtx";
103 nvidia,function = "uarta";
104 };
105 kbca {
106 nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
107 nvidia,function = "kbc";
108 };
109 kbcb {
110 nvidia,pins = "kbcb", "kbcd";
111 nvidia,function = "sdio2";
112 };
113 lcsn {
114 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
115 "ld3", "ld4", "ld5", "ld6", "ld7",
116 "ld8", "ld9", "ld10", "ld11", "ld12",
117 "ld13", "ld14", "ld15", "ld16", "ld17",
118 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
119 "lhs", "lm0", "lm1", "lpp", "lpw0",
120 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
121 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
122 "lvs";
123 nvidia,function = "displaya";
124 };
125 owc {
126 nvidia,pins = "owc";
127 nvidia,function = "owr";
128 };
129 pmc {
130 nvidia,pins = "pmc";
131 nvidia,function = "pwr_on";
132 };
133 rm {
134 nvidia,pins = "rm";
135 nvidia,function = "i2c1";
136 };
137 sdc {
138 nvidia,pins = "sdc";
139 nvidia,function = "twc";
140 };
141 sdio1 {
142 nvidia,pins = "sdio1";
143 nvidia,function = "sdio1";
144 };
145 slxc {
146 nvidia,pins = "slxc", "slxd";
147 nvidia,function = "spi4";
148 };
149 spdi {
150 nvidia,pins = "spdi", "spdo";
151 nvidia,function = "rsvd2";
152 };
153 spif {
154 nvidia,pins = "spif", "uac";
155 nvidia,function = "rsvd4";
156 };
157 spig {
158 nvidia,pins = "spig", "spih";
159 nvidia,function = "spi2_alt";
160 };
161 uaa {
162 nvidia,pins = "uaa", "uab", "uda";
163 nvidia,function = "ulpi";
164 };
165 uad {
166 nvidia,pins = "uad";
167 nvidia,function = "spdif";
168 };
169 uca {
170 nvidia,pins = "uca", "ucb";
171 nvidia,function = "uartc";
172 };
173 conf_ata {
174 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600175 "cdev1", "cdev2", "dap1", "dap2", "dtf",
176 "gma", "gmb", "gmc", "gmd", "gme",
177 "gpu", "gpu7", "gpv", "i2cp", "pta",
178 "rm", "sdio1", "slxk", "spdo", "uac",
179 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600183 conf_ck32 {
184 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
185 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
186 nvidia,pull = <0>;
187 };
188 conf_crtp {
189 nvidia,pins = "crtp", "dap3", "dap4", "dtb",
190 "dtc", "dte", "slxa", "slxc", "slxd",
191 "spdi";
192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_csus {
196 nvidia,pins = "csus", "spia", "spib", "spid",
197 "spif";
198 nvidia,pull = <1>;
199 nvidia,tristate = <1>;
200 };
201 conf_ddc {
202 nvidia,pins = "ddc", "irrx", "irtx", "kbca",
203 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
204 "spic", "spig", "uaa", "uab";
205 nvidia,pull = <2>;
206 nvidia,tristate = <0>;
207 };
208 conf_dta {
209 nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
210 "spie", "spih", "uad", "uca", "ucb";
211 nvidia,pull = <2>;
212 nvidia,tristate = <1>;
213 };
214 conf_hdint {
215 nvidia,pins = "hdint", "ld0", "ld1", "ld2",
216 "ld3", "ld4", "ld5", "ld6", "ld7",
217 "ld8", "ld9", "ld10", "ld11", "ld12",
218 "ld13", "ld14", "ld15", "ld16", "ld17",
219 "ldc", "ldi", "lhs", "lsc0", "lspi",
220 "lvs", "pmc";
221 nvidia,tristate = <0>;
222 };
223 conf_lc {
224 nvidia,pins = "lc", "ls";
225 nvidia,pull = <2>;
226 };
227 conf_lcsn {
228 nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
229 "lm0", "lm1", "lpp", "lpw0", "lpw1",
230 "lpw2", "lsc1", "lsck", "lsda", "lsdi",
231 "lvp0", "lvp1", "sdb";
232 nvidia,tristate = <1>;
233 };
234 conf_ld17_0 {
235 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
236 "ld23_22";
237 nvidia,pull = <1>;
238 };
239 };
240 };
241
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600242 i2s@70002800 {
243 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600244 };
245
246 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600247 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600248 };
249
Stephen Warrenc04abb32012-05-11 17:03:26 -0600250 serial@70006200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600251 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600252 };
253
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000254 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600255 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000256 clock-frequency = <400000>;
Leon Romanovsky613e9652012-02-02 22:13:35 +0200257
258 alc5632: alc5632@1e {
259 compatible = "realtek,alc5632";
260 reg = <0x1e>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000264 };
265
Stephen Warren11a3c862013-01-02 14:53:22 -0700266 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600267 status = "okay";
Stephen Warren11a3c862013-01-02 14:53:22 -0700268 clock-frequency = <100000>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000269 };
270
Stephen Warren58ecb232013-11-25 17:53:16 -0700271 nvec@7000c500 {
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000272 compatible = "nvidia,nvec";
Stephen Warrenba04c282012-05-11 16:28:59 -0600273 reg = <0x7000c500 0x100>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600275 #address-cells = <1>;
276 #size-cells = <0>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000277 clock-frequency = <80000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700278 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000279 slave-addr = <138>;
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300280 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
281 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
Prashant Gaikwadd409b3a2013-01-11 13:31:23 +0530282 clock-names = "div-clk", "fast-clk";
Stephen Warren3393d422013-11-06 14:01:16 -0700283 resets = <&tegra_car 67>;
284 reset-names = "i2c";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000285 };
286
287 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600288 status = "okay";
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000289 clock-frequency = <400000>;
Marc Dietrich1266f892012-01-31 19:53:21 +0100290
Stephen Warren217b8f02012-06-21 14:24:57 -0600291 pmic: tps6586x@34 {
292 compatible = "ti,tps6586x";
293 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700294 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Stephen Warren217b8f02012-06-21 14:24:57 -0600295
296 #gpio-cells = <2>;
297 gpio-controller;
298
299 sys-supply = <&p5valw_reg>;
300 vin-sm0-supply = <&sys_reg>;
301 vin-sm1-supply = <&sys_reg>;
302 vin-sm2-supply = <&sys_reg>;
303 vinldo01-supply = <&sm2_reg>;
304 vinldo23-supply = <&sm2_reg>;
305 vinldo4-supply = <&sm2_reg>;
306 vinldo678-supply = <&sm2_reg>;
307 vinldo9-supply = <&sm2_reg>;
308
309 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600310 sys_reg: sys {
Stephen Warren217b8f02012-06-21 14:24:57 -0600311 regulator-name = "vdd_sys";
312 regulator-always-on;
313 };
314
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600315 sm0 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600316 regulator-name = "+1.2vs_sm0,vdd_core";
317 regulator-min-microvolt = <1200000>;
318 regulator-max-microvolt = <1200000>;
319 regulator-always-on;
320 };
321
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600322 sm1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600323 regulator-name = "+1.0vs_sm1,vdd_cpu";
324 regulator-min-microvolt = <1000000>;
325 regulator-max-microvolt = <1000000>;
326 regulator-always-on;
327 };
328
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600329 sm2_reg: sm2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600330 regulator-name = "+3.7vs_sm2,vin_ldo*";
331 regulator-min-microvolt = <3700000>;
332 regulator-max-microvolt = <3700000>;
333 regulator-always-on;
334 };
335
336 /* LDO0 is not connected to anything */
337
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600338 ldo1 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600339 regulator-name = "+1.1vs_ldo1,avdd_pll*";
340 regulator-min-microvolt = <1100000>;
341 regulator-max-microvolt = <1100000>;
342 regulator-always-on;
343 };
344
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600345 ldo2 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600346 regulator-name = "+1.2vs_ldo2,vdd_rtc";
347 regulator-min-microvolt = <1200000>;
348 regulator-max-microvolt = <1200000>;
349 };
350
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600351 ldo3 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600352 regulator-name = "+3.3vs_ldo3,avdd_usb*";
353 regulator-min-microvolt = <3300000>;
354 regulator-max-microvolt = <3300000>;
355 regulator-always-on;
356 };
357
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600358 ldo4 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600359 regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
360 regulator-min-microvolt = <1800000>;
361 regulator-max-microvolt = <1800000>;
362 regulator-always-on;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600365 ldo5 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600366 regulator-name = "+2.85vs_ldo5,vcore_mmc";
367 regulator-min-microvolt = <2850000>;
368 regulator-max-microvolt = <2850000>;
369 regulator-always-on;
370 };
371
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600372 ldo6 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600373 /*
374 * Research indicates this should be
375 * 1.8v; other boards that use this
376 * rail for the same purpose need it
377 * set to 1.8v. The schematic signal
378 * name is incorrect; perhaps copied
379 * from an incorrect NVIDIA reference.
380 */
381 regulator-name = "+2.85vs_ldo6,avdd_vdac";
382 regulator-min-microvolt = <1800000>;
383 regulator-max-microvolt = <1800000>;
384 };
385
Stephen Warren11a3c862013-01-02 14:53:22 -0700386 hdmi_vdd_reg: ldo7 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600387 regulator-name = "+3.3vs_ldo7,avdd_hdmi";
388 regulator-min-microvolt = <3300000>;
389 regulator-max-microvolt = <3300000>;
390 };
391
Stephen Warren11a3c862013-01-02 14:53:22 -0700392 hdmi_pll_reg: ldo8 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600393 regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <1800000>;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600398 ldo9 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600399 regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
400 regulator-min-microvolt = <2850000>;
401 regulator-max-microvolt = <2850000>;
402 regulator-always-on;
403 };
404
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600405 ldo_rtc {
Stephen Warren217b8f02012-06-21 14:24:57 -0600406 regulator-name = "+3.3vs_rtc";
407 regulator-min-microvolt = <3300000>;
408 regulator-max-microvolt = <3300000>;
409 regulator-always-on;
410 };
411 };
412 };
413
Marc Dietrich1266f892012-01-31 19:53:21 +0100414 adt7461@4c {
415 compatible = "adi,adt7461";
416 reg = <0x4c>;
417 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000418 };
419
Stephen Warren58ecb232013-11-25 17:53:16 -0700420 pmc@7000e400 {
Stephen Warren217b8f02012-06-21 14:24:57 -0600421 nvidia,invert-interrupt;
Joseph Lo47d2d632013-08-12 17:40:07 +0800422 nvidia,suspend-mode = <1>;
Joseph Loa44a0192013-04-03 19:31:52 +0800423 nvidia,cpu-pwr-good-time = <2000>;
424 nvidia,cpu-pwr-off-time = <0>;
425 nvidia,core-pwr-good-time = <3845 3845>;
426 nvidia,core-pwr-off-time = <0>;
427 nvidia,sys-clock-req-active-high;
Stephen Warren217b8f02012-06-21 14:24:57 -0600428 };
429
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600430 usb@c5000000 {
431 status = "okay";
432 };
433
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530434 usb-phy@c5000000 {
435 status = "okay";
436 };
437
Stephen Warrenc04abb32012-05-11 17:03:26 -0600438 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600439 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700440 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
441 GPIO_ACTIVE_LOW>;
Venu Byravarasu9dffe3b2013-05-16 19:42:56 +0530442 };
443
444 usb-phy@c5004000 {
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530445 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700446 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
447 GPIO_ACTIVE_LOW>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000448 };
449
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600450 usb@c5008000 {
451 status = "okay";
452 };
453
Venu Byravarasu4c94c8b2013-05-16 19:42:57 +0530454 usb-phy@c5008000 {
455 status = "okay";
456 };
457
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000458 sdhci@c8000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600459 status = "okay";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700460 cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
461 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
462 power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
Arnd Bergmann7f217792012-05-13 00:14:24 -0400463 bus-width = <4>;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000464 };
465
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000466 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600467 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400468 bus-width = <8>;
Joseph Lo7a2617a2013-04-03 14:34:39 -0600469 non-removable;
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000470 };
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100471
Joseph Lo7021d122013-04-03 19:31:27 +0800472 clocks {
473 compatible = "simple-bus";
474 #address-cells = <1>;
475 #size-cells = <0>;
476
Stephen Warren58ecb232013-11-25 17:53:16 -0700477 clk32k_in: clock@0 {
Joseph Lo7021d122013-04-03 19:31:27 +0800478 compatible = "fixed-clock";
479 reg=<0>;
480 #clock-cells = <0>;
481 clock-frequency = <32768>;
482 };
483 };
484
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100485 gpio-keys {
486 compatible = "gpio-keys";
487
488 power {
489 label = "Power";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700490 gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
Marc Dietrichd8d56c82012-01-28 20:03:07 +0100491 linux,code = <116>; /* KEY_POWER */
492 gpio-key,wakeup;
493 };
494 };
Marc Dietrich80c94732012-01-28 20:03:08 +0100495
496 gpio-leds {
497 compatible = "gpio-leds";
498
499 wifi {
500 label = "wifi-led";
Stephen Warren3325f1b2013-02-12 17:25:15 -0700501 gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
Marc Dietrich80c94732012-01-28 20:03:08 +0100502 linux,default-trigger = "rfkill0";
503 };
504 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600505
Stephen Warren217b8f02012-06-21 14:24:57 -0600506 regulators {
507 compatible = "simple-bus";
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 p5valw_reg: regulator@0 {
512 compatible = "regulator-fixed";
513 reg = <0>;
514 regulator-name = "+5valw";
515 regulator-min-microvolt = <5000000>;
516 regulator-max-microvolt = <5000000>;
517 regulator-always-on;
518 };
519 };
520
Stephen Warrenc04abb32012-05-11 17:03:26 -0600521 sound {
522 compatible = "nvidia,tegra-audio-alc5632-paz00",
523 "nvidia,tegra-audio-alc5632";
524
525 nvidia,model = "Compal PAZ00";
526
527 nvidia,audio-routing =
528 "Int Spk", "SPKOUT",
529 "Int Spk", "SPKOUTN",
530 "Headset Mic", "MICBIAS1",
531 "MIC1", "Headset Mic",
532 "Headset Stereophone", "HPR",
533 "Headset Stereophone", "HPL",
534 "DMICDAT", "Digital Mic";
535
536 nvidia,audio-codec = <&alc5632>;
537 nvidia,i2s-controller = <&tegra_i2s1>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700538 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
539 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600540
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300541 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
542 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
543 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600544 clock-names = "pll_a", "pll_a_out0", "mclk";
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600545 };
Marc Dietrichcc2afa42011-11-01 10:37:05 +0000546};