blob: a626c539fb17ffcb78f1508566aa90fbbe99481d [file] [log] [blame]
Harry Morrisded845a2017-03-28 13:08:58 +01001/*
2 * http://www.cascoda.com/products/ca-821x/
3 * Copyright (c) 2016, Cascoda, Ltd.
4 * All rights reserved.
5 *
6 * This code is dual-licensed under both GPLv2 and 3-clause BSD. What follows is
7 * the license notice for both respectively.
8 *
9 *******************************************************************************
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 *******************************************************************************
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions are met:
25 *
26 * 1. Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.
28 *
29 * 2. Redistributions in binary form must reproduce the above copyright notice,
30 * this list of conditions and the following disclaimer in the documentation
31 * and/or other materials provided with the distribution.
32 *
33 * 3. Neither the name of the copyright holder nor the names of its contributors
34 * may be used to endorse or promote products derived from this software without
35 * specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
40 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
41 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
42 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
43 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
44 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
45 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
46 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
47 * POSSIBILITY OF SUCH DAMAGE.
48 */
49
50#include <linux/cdev.h>
51#include <linux/clk-provider.h>
52#include <linux/debugfs.h>
53#include <linux/delay.h>
54#include <linux/gpio.h>
55#include <linux/ieee802154.h>
56#include <linux/kfifo.h>
57#include <linux/of.h>
58#include <linux/of_device.h>
59#include <linux/of_gpio.h>
60#include <linux/module.h>
61#include <linux/mutex.h>
62#include <linux/poll.h>
63#include <linux/skbuff.h>
64#include <linux/slab.h>
65#include <linux/spi/spi.h>
66#include <linux/spinlock.h>
67#include <linux/string.h>
68#include <linux/workqueue.h>
69
70#include <net/ieee802154_netdev.h>
71#include <net/mac802154.h>
72
73#define DRIVER_NAME "ca8210"
74
75/* external clock frequencies */
76#define ONE_MHZ 1000000
77#define TWO_MHZ (2 * ONE_MHZ)
78#define FOUR_MHZ (4 * ONE_MHZ)
79#define EIGHT_MHZ (8 * ONE_MHZ)
80#define SIXTEEN_MHZ (16 * ONE_MHZ)
81
82/* spi constants */
83#define CA8210_SPI_BUF_SIZE 256
84#define CA8210_SYNC_TIMEOUT 1000 /* Timeout for synchronous commands [ms] */
85
86/* test interface constants */
87#define CA8210_TEST_INT_FILE_NAME "ca8210_test"
88#define CA8210_TEST_INT_FIFO_SIZE 256
89
90/* MAC status enumerations */
91#define MAC_SUCCESS (0x00)
92#define MAC_ERROR (0x01)
93#define MAC_CANCELLED (0x02)
94#define MAC_READY_FOR_POLL (0x03)
95#define MAC_COUNTER_ERROR (0xDB)
96#define MAC_IMPROPER_KEY_TYPE (0xDC)
97#define MAC_IMPROPER_SECURITY_LEVEL (0xDD)
98#define MAC_UNSUPPORTED_LEGACY (0xDE)
99#define MAC_UNSUPPORTED_SECURITY (0xDF)
100#define MAC_BEACON_LOST (0xE0)
101#define MAC_CHANNEL_ACCESS_FAILURE (0xE1)
102#define MAC_DENIED (0xE2)
103#define MAC_DISABLE_TRX_FAILURE (0xE3)
104#define MAC_SECURITY_ERROR (0xE4)
105#define MAC_FRAME_TOO_LONG (0xE5)
106#define MAC_INVALID_GTS (0xE6)
107#define MAC_INVALID_HANDLE (0xE7)
108#define MAC_INVALID_PARAMETER (0xE8)
109#define MAC_NO_ACK (0xE9)
110#define MAC_NO_BEACON (0xEA)
111#define MAC_NO_DATA (0xEB)
112#define MAC_NO_SHORT_ADDRESS (0xEC)
113#define MAC_OUT_OF_CAP (0xED)
114#define MAC_PAN_ID_CONFLICT (0xEE)
115#define MAC_REALIGNMENT (0xEF)
116#define MAC_TRANSACTION_EXPIRED (0xF0)
117#define MAC_TRANSACTION_OVERFLOW (0xF1)
118#define MAC_TX_ACTIVE (0xF2)
119#define MAC_UNAVAILABLE_KEY (0xF3)
120#define MAC_UNSUPPORTED_ATTRIBUTE (0xF4)
121#define MAC_INVALID_ADDRESS (0xF5)
122#define MAC_ON_TIME_TOO_LONG (0xF6)
123#define MAC_PAST_TIME (0xF7)
124#define MAC_TRACKING_OFF (0xF8)
125#define MAC_INVALID_INDEX (0xF9)
126#define MAC_LIMIT_REACHED (0xFA)
127#define MAC_READ_ONLY (0xFB)
128#define MAC_SCAN_IN_PROGRESS (0xFC)
129#define MAC_SUPERFRAME_OVERLAP (0xFD)
130#define MAC_SYSTEM_ERROR (0xFF)
131
132/* HWME attribute IDs */
133#define HWME_EDTHRESHOLD (0x04)
134#define HWME_EDVALUE (0x06)
135#define HWME_SYSCLKOUT (0x0F)
136#define HWME_LQILIMIT (0x11)
137
138/* TDME attribute IDs */
139#define TDME_CHANNEL (0x00)
140#define TDME_ATM_CONFIG (0x06)
141
142#define MAX_HWME_ATTRIBUTE_SIZE 16
143#define MAX_TDME_ATTRIBUTE_SIZE 2
144
145/* PHY/MAC PIB Attribute Enumerations */
146#define PHY_CURRENT_CHANNEL (0x00)
147#define PHY_TRANSMIT_POWER (0x02)
148#define PHY_CCA_MODE (0x03)
149#define MAC_ASSOCIATION_PERMIT (0x41)
150#define MAC_AUTO_REQUEST (0x42)
151#define MAC_BATT_LIFE_EXT (0x43)
152#define MAC_BATT_LIFE_EXT_PERIODS (0x44)
153#define MAC_BEACON_PAYLOAD (0x45)
154#define MAC_BEACON_PAYLOAD_LENGTH (0x46)
155#define MAC_BEACON_ORDER (0x47)
156#define MAC_GTS_PERMIT (0x4d)
157#define MAC_MAX_CSMA_BACKOFFS (0x4e)
158#define MAC_MIN_BE (0x4f)
159#define MAC_PAN_ID (0x50)
160#define MAC_PROMISCUOUS_MODE (0x51)
161#define MAC_RX_ON_WHEN_IDLE (0x52)
162#define MAC_SHORT_ADDRESS (0x53)
163#define MAC_SUPERFRAME_ORDER (0x54)
164#define MAC_ASSOCIATED_PAN_COORD (0x56)
165#define MAC_MAX_BE (0x57)
166#define MAC_MAX_FRAME_RETRIES (0x59)
167#define MAC_RESPONSE_WAIT_TIME (0x5A)
168#define MAC_SECURITY_ENABLED (0x5D)
169
170#define MAC_AUTO_REQUEST_SECURITY_LEVEL (0x78)
171#define MAC_AUTO_REQUEST_KEY_ID_MODE (0x79)
172
173#define NS_IEEE_ADDRESS (0xFF) /* Non-standard IEEE address */
174
175/* MAC Address Mode Definitions */
176#define MAC_MODE_NO_ADDR (0x00)
177#define MAC_MODE_SHORT_ADDR (0x02)
178#define MAC_MODE_LONG_ADDR (0x03)
179
180/* MAC constants */
181#define MAX_BEACON_OVERHEAD (75)
182#define MAX_BEACON_PAYLOAD_LENGTH (IEEE802154_MTU - MAX_BEACON_OVERHEAD)
183
184#define MAX_ATTRIBUTE_SIZE (122)
185#define MAX_DATA_SIZE (114)
186
187#define CA8210_VALID_CHANNELS (0x07FFF800)
188
189/* MAC workarounds for V1.1 and MPW silicon (V0.x) */
190#define CA8210_MAC_WORKAROUNDS (0)
191#define CA8210_MAC_MPW (0)
192
193/* memory manipulation macros */
194#define LS_BYTE(x) ((u8)((x) & 0xFF))
195#define MS_BYTE(x) ((u8)(((x) >> 8) & 0xFF))
196
197/* message ID codes in SPI commands */
198/* downstream */
199#define MCPS_DATA_REQUEST (0x00)
200#define MLME_ASSOCIATE_REQUEST (0x02)
201#define MLME_ASSOCIATE_RESPONSE (0x03)
202#define MLME_DISASSOCIATE_REQUEST (0x04)
203#define MLME_GET_REQUEST (0x05)
204#define MLME_ORPHAN_RESPONSE (0x06)
205#define MLME_RESET_REQUEST (0x07)
206#define MLME_RX_ENABLE_REQUEST (0x08)
207#define MLME_SCAN_REQUEST (0x09)
208#define MLME_SET_REQUEST (0x0A)
209#define MLME_START_REQUEST (0x0B)
210#define MLME_POLL_REQUEST (0x0D)
211#define HWME_SET_REQUEST (0x0E)
212#define HWME_GET_REQUEST (0x0F)
213#define TDME_SETSFR_REQUEST (0x11)
214#define TDME_GETSFR_REQUEST (0x12)
215#define TDME_SET_REQUEST (0x14)
216/* upstream */
217#define MCPS_DATA_INDICATION (0x00)
218#define MCPS_DATA_CONFIRM (0x01)
219#define MLME_RESET_CONFIRM (0x0A)
220#define MLME_SET_CONFIRM (0x0E)
221#define MLME_START_CONFIRM (0x0F)
222#define HWME_SET_CONFIRM (0x12)
223#define HWME_GET_CONFIRM (0x13)
224#define HWME_WAKEUP_INDICATION (0x15)
225#define TDME_SETSFR_CONFIRM (0x17)
226
227/* SPI command IDs */
228/* bit indicating a confirm or indication from slave to master */
229#define SPI_S2M (0x20)
230/* bit indicating a synchronous message */
231#define SPI_SYN (0x40)
232
233/* SPI command definitions */
234#define SPI_IDLE (0xFF)
235#define SPI_NACK (0xF0)
236
237#define SPI_MCPS_DATA_REQUEST (MCPS_DATA_REQUEST)
238#define SPI_MCPS_DATA_INDICATION (MCPS_DATA_INDICATION + SPI_S2M)
239#define SPI_MCPS_DATA_CONFIRM (MCPS_DATA_CONFIRM + SPI_S2M)
240
241#define SPI_MLME_ASSOCIATE_REQUEST (MLME_ASSOCIATE_REQUEST)
242#define SPI_MLME_RESET_REQUEST (MLME_RESET_REQUEST + SPI_SYN)
243#define SPI_MLME_SET_REQUEST (MLME_SET_REQUEST + SPI_SYN)
244#define SPI_MLME_START_REQUEST (MLME_START_REQUEST + SPI_SYN)
245#define SPI_MLME_RESET_CONFIRM (MLME_RESET_CONFIRM + SPI_S2M + SPI_SYN)
246#define SPI_MLME_SET_CONFIRM (MLME_SET_CONFIRM + SPI_S2M + SPI_SYN)
247#define SPI_MLME_START_CONFIRM (MLME_START_CONFIRM + SPI_S2M + SPI_SYN)
248
249#define SPI_HWME_SET_REQUEST (HWME_SET_REQUEST + SPI_SYN)
250#define SPI_HWME_GET_REQUEST (HWME_GET_REQUEST + SPI_SYN)
251#define SPI_HWME_SET_CONFIRM (HWME_SET_CONFIRM + SPI_S2M + SPI_SYN)
252#define SPI_HWME_GET_CONFIRM (HWME_GET_CONFIRM + SPI_S2M + SPI_SYN)
253#define SPI_HWME_WAKEUP_INDICATION (HWME_WAKEUP_INDICATION + SPI_S2M)
254
255#define SPI_TDME_SETSFR_REQUEST (TDME_SETSFR_REQUEST + SPI_SYN)
256#define SPI_TDME_SET_REQUEST (TDME_SET_REQUEST + SPI_SYN)
257#define SPI_TDME_SETSFR_CONFIRM (TDME_SETSFR_CONFIRM + SPI_S2M + SPI_SYN)
258
259/* TDME SFR addresses */
260/* Page 0 */
261#define CA8210_SFR_PACFG (0xB1)
262#define CA8210_SFR_MACCON (0xD8)
263#define CA8210_SFR_PACFGIB (0xFE)
264/* Page 1 */
265#define CA8210_SFR_LOTXCAL (0xBF)
266#define CA8210_SFR_PTHRH (0xD1)
267#define CA8210_SFR_PRECFG (0xD3)
268#define CA8210_SFR_LNAGX40 (0xE1)
269#define CA8210_SFR_LNAGX41 (0xE2)
270#define CA8210_SFR_LNAGX42 (0xE3)
271#define CA8210_SFR_LNAGX43 (0xE4)
272#define CA8210_SFR_LNAGX44 (0xE5)
273#define CA8210_SFR_LNAGX45 (0xE6)
274#define CA8210_SFR_LNAGX46 (0xE7)
275#define CA8210_SFR_LNAGX47 (0xE9)
276
277#define PACFGIB_DEFAULT_CURRENT (0x3F)
278#define PTHRH_DEFAULT_THRESHOLD (0x5A)
279#define LNAGX40_DEFAULT_GAIN (0x29) /* 10dB */
280#define LNAGX41_DEFAULT_GAIN (0x54) /* 21dB */
281#define LNAGX42_DEFAULT_GAIN (0x6C) /* 27dB */
282#define LNAGX43_DEFAULT_GAIN (0x7A) /* 30dB */
283#define LNAGX44_DEFAULT_GAIN (0x84) /* 33dB */
284#define LNAGX45_DEFAULT_GAIN (0x8B) /* 34dB */
285#define LNAGX46_DEFAULT_GAIN (0x92) /* 36dB */
286#define LNAGX47_DEFAULT_GAIN (0x96) /* 37dB */
287
288#define CA8210_IOCTL_HARD_RESET (0x00)
289
290/* Structs/Enums */
291
292/**
293 * struct cas_control - spi transfer structure
294 * @msg: spi_message for each exchange
295 * @transfer: spi_transfer for each exchange
296 * @tx_buf: source array for transmission
297 * @tx_in_buf: array storing bytes received during transmission
298 * @priv: pointer to private data
299 *
300 * This structure stores all the necessary data passed around during a single
301 * spi exchange.
302 */
303struct cas_control {
304 struct spi_message msg;
305 struct spi_transfer transfer;
306
307 u8 tx_buf[CA8210_SPI_BUF_SIZE];
308 u8 tx_in_buf[CA8210_SPI_BUF_SIZE];
309
310 struct ca8210_priv *priv;
311};
312
313/**
314 * struct ca8210_test - ca8210 test interface structure
315 * @ca8210_dfs_spi_int: pointer to the entry in the debug fs for this device
316 * @up_fifo: fifo for upstream messages
317 *
318 * This structure stores all the data pertaining to the debug interface
319 */
320struct ca8210_test {
321 struct dentry *ca8210_dfs_spi_int;
322 struct kfifo up_fifo;
323 wait_queue_head_t readq;
324};
325
326/**
327 * struct ca8210_priv - ca8210 private data structure
328 * @spi: pointer to the ca8210 spi device object
329 * @hw: pointer to the ca8210 ieee802154_hw object
330 * @hw_registered: true if hw has been registered with ieee802154
331 * @lock: spinlock protecting the private data area
332 * @mlme_workqueue: workqueue for triggering MLME Reset
333 * @irq_workqueue: workqueue for irq processing
334 * @tx_skb: current socket buffer to transmit
335 * @nextmsduhandle: msdu handle to pass to the 15.4 MAC layer for the
336 * next transmission
337 * @clk: external clock provided by the ca8210
338 * @last_dsn: sequence number of last data packet received, for
339 * resend detection
340 * @test: test interface data section for this instance
341 * @async_tx_pending: true if an asynchronous transmission was started and
342 * is not complete
343 * @sync_command_response: pointer to buffer to fill with sync response
344 * @ca8210_is_awake: nonzero if ca8210 is initialised, ready for comms
345 * @sync_down: counts number of downstream synchronous commands
346 * @sync_up: counts number of upstream synchronous commands
347 * @spi_transfer_complete completion object for a single spi_transfer
348 * @sync_exchange_complete completion object for a complete synchronous API
349 * exchange
350 * @promiscuous whether the ca8210 is in promiscuous mode or not
351 * @retries: records how many times the current pending spi
352 * transfer has been retried
353 */
354struct ca8210_priv {
355 struct spi_device *spi;
356 struct ieee802154_hw *hw;
357 bool hw_registered;
358 spinlock_t lock;
359 struct workqueue_struct *mlme_workqueue;
360 struct workqueue_struct *irq_workqueue;
361 struct sk_buff *tx_skb;
362 u8 nextmsduhandle;
363 struct clk *clk;
364 int last_dsn;
365 struct ca8210_test test;
366 bool async_tx_pending;
367 u8 *sync_command_response;
368 struct completion ca8210_is_awake;
369 int sync_down, sync_up;
370 struct completion spi_transfer_complete, sync_exchange_complete;
371 bool promiscuous;
372 int retries;
373};
374
375/**
376 * struct work_priv_container - link between a work object and the relevant
377 * device's private data
378 * @work: work object being executed
379 * @priv: device's private data section
380 *
381 */
382struct work_priv_container {
383 struct work_struct work;
384 struct ca8210_priv *priv;
385};
386
387/**
388 * struct ca8210_platform_data - ca8210 platform data structure
389 * @extclockenable: true if the external clock is to be enabled
390 * @extclockfreq: frequency of the external clock
391 * @extclockgpio: ca8210 output gpio of the external clock
392 * @gpio_reset: gpio number of ca8210 reset line
393 * @gpio_irq: gpio number of ca8210 interrupt line
394 * @irq_id: identifier for the ca8210 irq
395 *
396 */
397struct ca8210_platform_data {
398 bool extclockenable;
399 unsigned int extclockfreq;
400 unsigned int extclockgpio;
401 int gpio_reset;
402 int gpio_irq;
403 int irq_id;
404};
405
406/**
407 * struct fulladdr - full MAC addressing information structure
408 * @mode: address mode (none, short, extended)
409 * @pan_id: 16-bit LE pan id
410 * @address: LE address, variable length as specified by mode
411 *
412 */
413struct fulladdr {
414 u8 mode;
415 u8 pan_id[2];
416 u8 address[8];
417};
418
419/**
420 * union macaddr: generic MAC address container
421 * @short_addr: 16-bit short address
422 * @ieee_address: 64-bit extended address as LE byte array
423 *
424 */
425union macaddr {
426 u16 short_address;
427 u8 ieee_address[8];
428};
429
430/**
431 * struct secspec: security specification for SAP commands
432 * @security_level: 0-7, controls level of authentication & encryption
433 * @key_id_mode: 0-3, specifies how to obtain key
434 * @key_source: extended key retrieval data
435 * @key_index: single-byte key identifier
436 *
437 */
438struct secspec {
439 u8 security_level;
440 u8 key_id_mode;
441 u8 key_source[8];
442 u8 key_index;
443};
444
445/* downlink functions parameter set definitions */
446struct mcps_data_request_pset {
447 u8 src_addr_mode;
448 struct fulladdr dst;
449 u8 msdu_length;
450 u8 msdu_handle;
451 u8 tx_options;
452 u8 msdu[MAX_DATA_SIZE];
453};
454
455struct mlme_set_request_pset {
456 u8 pib_attribute;
457 u8 pib_attribute_index;
458 u8 pib_attribute_length;
459 u8 pib_attribute_value[MAX_ATTRIBUTE_SIZE];
460};
461
462struct hwme_set_request_pset {
463 u8 hw_attribute;
464 u8 hw_attribute_length;
465 u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
466};
467
468struct hwme_get_request_pset {
469 u8 hw_attribute;
470};
471
472struct tdme_setsfr_request_pset {
473 u8 sfr_page;
474 u8 sfr_address;
475 u8 sfr_value;
476};
477
478/* uplink functions parameter set definitions */
479struct hwme_set_confirm_pset {
480 u8 status;
481 u8 hw_attribute;
482};
483
484struct hwme_get_confirm_pset {
485 u8 status;
486 u8 hw_attribute;
487 u8 hw_attribute_length;
488 u8 hw_attribute_value[MAX_HWME_ATTRIBUTE_SIZE];
489};
490
491struct tdme_setsfr_confirm_pset {
492 u8 status;
493 u8 sfr_page;
494 u8 sfr_address;
495};
496
497struct mac_message {
498 u8 command_id;
499 u8 length;
500 union {
501 struct mcps_data_request_pset data_req;
502 struct mlme_set_request_pset set_req;
503 struct hwme_set_request_pset hwme_set_req;
504 struct hwme_get_request_pset hwme_get_req;
505 struct tdme_setsfr_request_pset tdme_set_sfr_req;
506 struct hwme_set_confirm_pset hwme_set_cnf;
507 struct hwme_get_confirm_pset hwme_get_cnf;
508 struct tdme_setsfr_confirm_pset tdme_set_sfr_cnf;
509 u8 u8param;
510 u8 status;
511 u8 payload[148];
512 } pdata;
513};
514
515union pa_cfg_sfr {
516 struct {
517 u8 bias_current_trim : 3;
518 u8 /* reserved */ : 1;
519 u8 buffer_capacitor_trim : 3;
520 u8 boost : 1;
521 };
522 u8 paib;
523};
524
525struct preamble_cfg_sfr {
526 u8 timeout_symbols : 3;
527 u8 acquisition_symbols : 3;
528 u8 search_symbols : 2;
529};
530
531static int (*cascoda_api_upstream)(
532 const u8 *buf,
533 size_t len,
534 void *device_ref
535);
536
537/**
538 * link_to_linux_err() - Translates an 802.15.4 return code into the closest
539 * linux error
540 * @link_status: 802.15.4 status code
541 *
542 * Return: 0 or Linux error code
543 */
544static int link_to_linux_err(int link_status)
545{
546 if (link_status < 0) {
547 /* status is already a Linux code */
548 return link_status;
549 }
550 switch (link_status) {
551 case MAC_SUCCESS:
552 case MAC_REALIGNMENT:
553 return 0;
554 case MAC_IMPROPER_KEY_TYPE:
555 return -EKEYREJECTED;
556 case MAC_IMPROPER_SECURITY_LEVEL:
557 case MAC_UNSUPPORTED_LEGACY:
558 case MAC_DENIED:
559 return -EACCES;
560 case MAC_BEACON_LOST:
561 case MAC_NO_ACK:
562 case MAC_NO_BEACON:
563 return -ENETUNREACH;
564 case MAC_CHANNEL_ACCESS_FAILURE:
565 case MAC_TX_ACTIVE:
566 case MAC_SCAN_IN_PROGRESS:
567 return -EBUSY;
568 case MAC_DISABLE_TRX_FAILURE:
569 case MAC_OUT_OF_CAP:
570 return -EAGAIN;
571 case MAC_FRAME_TOO_LONG:
572 return -EMSGSIZE;
573 case MAC_INVALID_GTS:
574 case MAC_PAST_TIME:
575 return -EBADSLT;
576 case MAC_INVALID_HANDLE:
577 return -EBADMSG;
578 case MAC_INVALID_PARAMETER:
579 case MAC_UNSUPPORTED_ATTRIBUTE:
580 case MAC_ON_TIME_TOO_LONG:
581 case MAC_INVALID_INDEX:
582 return -EINVAL;
583 case MAC_NO_DATA:
584 return -ENODATA;
585 case MAC_NO_SHORT_ADDRESS:
586 return -EFAULT;
587 case MAC_PAN_ID_CONFLICT:
588 return -EADDRINUSE;
589 case MAC_TRANSACTION_EXPIRED:
590 return -ETIME;
591 case MAC_TRANSACTION_OVERFLOW:
592 return -ENOBUFS;
593 case MAC_UNAVAILABLE_KEY:
594 return -ENOKEY;
595 case MAC_INVALID_ADDRESS:
596 return -ENXIO;
597 case MAC_TRACKING_OFF:
598 case MAC_SUPERFRAME_OVERLAP:
599 return -EREMOTEIO;
600 case MAC_LIMIT_REACHED:
601 return -EDQUOT;
602 case MAC_READ_ONLY:
603 return -EROFS;
604 default:
605 return -EPROTO;
606 }
607}
608
609/**
610 * ca8210_test_int_driver_write() - Writes a message to the test interface to be
611 * read by the userspace
612 * @buf: Buffer containing upstream message
613 * @len: length of message to write
614 * @spi: SPI device of message originator
615 *
616 * Return: 0 or linux error code
617 */
618static int ca8210_test_int_driver_write(
619 const u8 *buf,
620 size_t len,
621 void *spi
622)
623{
624 struct ca8210_priv *priv = spi_get_drvdata(spi);
625 struct ca8210_test *test = &priv->test;
626 char *fifo_buffer;
627 int i;
628
629 dev_dbg(
630 &priv->spi->dev,
631 "test_interface: Buffering upstream message:\n"
632 );
633 for (i = 0; i < len; i++)
634 dev_dbg(&priv->spi->dev, "%#03x\n", buf[i]);
635
636 fifo_buffer = kmalloc(len, GFP_KERNEL);
Colin Ian King941825e2017-03-29 18:05:40 +0100637 if (!fifo_buffer)
638 return -ENOMEM;
Harry Morrisded845a2017-03-28 13:08:58 +0100639 memcpy(fifo_buffer, buf, len);
640 kfifo_in(&test->up_fifo, &fifo_buffer, 4);
641 wake_up_interruptible(&priv->test.readq);
642
643 return 0;
644}
645
646/* SPI Operation */
647
648static int ca8210_net_rx(
649 struct ieee802154_hw *hw,
650 u8 *command,
651 size_t len
652);
653static u8 mlme_reset_request_sync(
654 u8 set_default_pib,
655 void *device_ref
656);
657static int ca8210_spi_transfer(
658 struct spi_device *spi,
659 const u8 *buf,
660 size_t len
661);
662
663/**
664 * ca8210_reset_send() - Hard resets the ca8210 for a given time
665 * @spi: Pointer to target ca8210 spi device
666 * @ms: Milliseconds to hold the reset line low for
667 */
668static void ca8210_reset_send(struct spi_device *spi, unsigned int ms)
669{
670 struct ca8210_platform_data *pdata = spi->dev.platform_data;
671 struct ca8210_priv *priv = spi_get_drvdata(spi);
672 long status;
673
674 gpio_set_value(pdata->gpio_reset, 0);
675 reinit_completion(&priv->ca8210_is_awake);
676 msleep(ms);
677 gpio_set_value(pdata->gpio_reset, 1);
678 priv->promiscuous = false;
679
680 /* Wait until wakeup indication seen */
681 status = wait_for_completion_interruptible_timeout(
682 &priv->ca8210_is_awake,
683 msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
684 );
685 if (status == 0) {
686 dev_crit(
687 &spi->dev,
688 "Fatal: No wakeup from ca8210 after reset!\n"
689 );
690 }
691
692 dev_dbg(&spi->dev, "Reset the device\n");
693}
694
695/**
696 * ca8210_mlme_reset_worker() - Resets the MLME, Called when the MAC OVERFLOW
697 * condition happens.
698 * @work: Pointer to work being executed
699 */
700static void ca8210_mlme_reset_worker(struct work_struct *work)
701{
702 struct work_priv_container *wpc = container_of(
703 work,
704 struct work_priv_container,
705 work
706 );
707 struct ca8210_priv *priv = wpc->priv;
708
709 mlme_reset_request_sync(0, priv->spi);
710 kfree(wpc);
711}
712
713/**
714 * ca8210_rx_done() - Calls various message dispatches responding to a received
715 * command
716 * @arg: Pointer to the cas_control object for the relevant spi transfer
717 *
718 * Presents a received SAP command from the ca8210 to the Cascoda EVBME, test
719 * interface and network driver.
720 */
721static void ca8210_rx_done(struct cas_control *cas_ctl)
722{
723 u8 *buf;
724 u8 len;
725 struct work_priv_container *mlme_reset_wpc;
726 struct ca8210_priv *priv = cas_ctl->priv;
727
728 buf = cas_ctl->tx_in_buf;
729 len = buf[1] + 2;
730 if (len > CA8210_SPI_BUF_SIZE) {
731 dev_crit(
732 &priv->spi->dev,
733 "Received packet len (%d) erroneously long\n",
734 len
735 );
736 goto finish;
737 }
738
739 if (buf[0] & SPI_SYN) {
740 if (priv->sync_command_response) {
741 memcpy(priv->sync_command_response, buf, len);
742 complete(&priv->sync_exchange_complete);
743 } else {
744 if (cascoda_api_upstream)
745 cascoda_api_upstream(buf, len, priv->spi);
746 priv->sync_up++;
747 }
748 } else {
749 if (cascoda_api_upstream)
750 cascoda_api_upstream(buf, len, priv->spi);
751 }
752
753 ca8210_net_rx(priv->hw, buf, len);
754 if (buf[0] == SPI_MCPS_DATA_CONFIRM) {
755 if (buf[3] == MAC_TRANSACTION_OVERFLOW) {
756 dev_info(
757 &priv->spi->dev,
758 "Waiting for transaction overflow to stabilise...\n");
759 msleep(2000);
760 dev_info(
761 &priv->spi->dev,
762 "Resetting MAC...\n");
763
Colin Ian King941825e2017-03-29 18:05:40 +0100764 mlme_reset_wpc = kmalloc(sizeof(*mlme_reset_wpc),
765 GFP_KERNEL);
766 if (!mlme_reset_wpc)
767 goto finish;
Harry Morrisded845a2017-03-28 13:08:58 +0100768 INIT_WORK(
769 &mlme_reset_wpc->work,
770 ca8210_mlme_reset_worker
771 );
772 mlme_reset_wpc->priv = priv;
773 queue_work(priv->mlme_workqueue, &mlme_reset_wpc->work);
774 }
775 } else if (buf[0] == SPI_HWME_WAKEUP_INDICATION) {
776 dev_notice(
777 &priv->spi->dev,
778 "Wakeup indication received, reason:\n"
779 );
780 switch (buf[2]) {
781 case 0:
782 dev_notice(
783 &priv->spi->dev,
784 "Transceiver woken up from Power Up / System Reset\n"
785 );
786 break;
787 case 1:
788 dev_notice(
789 &priv->spi->dev,
790 "Watchdog Timer Time-Out\n"
791 );
792 break;
793 case 2:
794 dev_notice(
795 &priv->spi->dev,
796 "Transceiver woken up from Power-Off by Sleep Timer Time-Out\n");
797 break;
798 case 3:
799 dev_notice(
800 &priv->spi->dev,
801 "Transceiver woken up from Power-Off by GPIO Activity\n"
802 );
803 break;
804 case 4:
805 dev_notice(
806 &priv->spi->dev,
807 "Transceiver woken up from Standby by Sleep Timer Time-Out\n"
808 );
809 break;
810 case 5:
811 dev_notice(
812 &priv->spi->dev,
813 "Transceiver woken up from Standby by GPIO Activity\n"
814 );
815 break;
816 case 6:
817 dev_notice(
818 &priv->spi->dev,
819 "Sleep-Timer Time-Out in Active Mode\n"
820 );
821 break;
822 default:
823 dev_warn(&priv->spi->dev, "Wakeup reason unknown\n");
824 break;
825 }
826 complete(&priv->ca8210_is_awake);
827 }
828
829finish:;
830}
831
832static int ca8210_remove(struct spi_device *spi_device);
833
834/**
835 * ca8210_spi_transfer_complete() - Called when a single spi transfer has
836 * completed
837 * @context: Pointer to the cas_control object for the finished transfer
838 */
839static void ca8210_spi_transfer_complete(void *context)
840{
841 struct cas_control *cas_ctl = context;
842 struct ca8210_priv *priv = cas_ctl->priv;
843 bool duplex_rx = false;
844 int i;
845 u8 retry_buffer[CA8210_SPI_BUF_SIZE];
846
847 if (
848 cas_ctl->tx_in_buf[0] == SPI_NACK ||
849 (cas_ctl->tx_in_buf[0] == SPI_IDLE &&
850 cas_ctl->tx_in_buf[1] == SPI_NACK)
851 ) {
852 /* ca8210 is busy */
853 dev_info(&priv->spi->dev, "ca8210 was busy during attempted write\n");
854 if (cas_ctl->tx_buf[0] == SPI_IDLE) {
855 dev_warn(
856 &priv->spi->dev,
857 "IRQ servicing NACKd, dropping transfer\n"
858 );
859 kfree(cas_ctl);
860 return;
861 }
862 if (priv->retries > 3) {
863 dev_err(&priv->spi->dev, "too many retries!\n");
864 kfree(cas_ctl);
865 ca8210_remove(priv->spi);
866 return;
867 }
868 memcpy(retry_buffer, cas_ctl->tx_buf, CA8210_SPI_BUF_SIZE);
869 kfree(cas_ctl);
870 ca8210_spi_transfer(
871 priv->spi,
872 retry_buffer,
873 CA8210_SPI_BUF_SIZE
874 );
875 priv->retries++;
876 dev_info(&priv->spi->dev, "retried spi write\n");
877 return;
878 } else if (
879 cas_ctl->tx_in_buf[0] != SPI_IDLE &&
880 cas_ctl->tx_in_buf[0] != SPI_NACK
881 ) {
882 duplex_rx = true;
883 }
884
885 if (duplex_rx) {
886 dev_dbg(&priv->spi->dev, "READ CMD DURING TX\n");
887 for (i = 0; i < cas_ctl->tx_in_buf[1] + 2; i++)
888 dev_dbg(
889 &priv->spi->dev,
890 "%#03x\n",
891 cas_ctl->tx_in_buf[i]
892 );
893 ca8210_rx_done(cas_ctl);
894 }
895 complete(&priv->spi_transfer_complete);
896 kfree(cas_ctl);
897 priv->retries = 0;
898}
899
900/**
901 * ca8210_spi_transfer() - Initiate duplex spi transfer with ca8210
902 * @spi: Pointer to spi device for transfer
903 * @buf: Octet array to send
904 * @len: length of the buffer being sent
905 *
906 * Return: 0 or linux error code
907 */
908static int ca8210_spi_transfer(
909 struct spi_device *spi,
910 const u8 *buf,
911 size_t len
912)
913{
914 int i, status = 0;
Gustavo A. R. Silva7dab5462017-05-23 13:11:47 -0500915 struct ca8210_priv *priv;
Harry Morrisded845a2017-03-28 13:08:58 +0100916 struct cas_control *cas_ctl;
917
918 if (!spi) {
919 dev_crit(
920 &spi->dev,
921 "NULL spi device passed to ca8210_spi_transfer\n"
922 );
923 return -ENODEV;
924 }
925
Gustavo A. R. Silva7dab5462017-05-23 13:11:47 -0500926 priv = spi_get_drvdata(spi);
Harry Morrisded845a2017-03-28 13:08:58 +0100927 reinit_completion(&priv->spi_transfer_complete);
928
929 dev_dbg(&spi->dev, "ca8210_spi_transfer called\n");
930
Colin Ian King941825e2017-03-29 18:05:40 +0100931 cas_ctl = kmalloc(sizeof(*cas_ctl), GFP_ATOMIC);
932 if (!cas_ctl)
933 return -ENOMEM;
934
Harry Morrisded845a2017-03-28 13:08:58 +0100935 cas_ctl->priv = priv;
936 memset(cas_ctl->tx_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
937 memset(cas_ctl->tx_in_buf, SPI_IDLE, CA8210_SPI_BUF_SIZE);
938 memcpy(cas_ctl->tx_buf, buf, len);
939
940 for (i = 0; i < len; i++)
941 dev_dbg(&spi->dev, "%#03x\n", cas_ctl->tx_buf[i]);
942
943 spi_message_init(&cas_ctl->msg);
944
945 cas_ctl->transfer.tx_nbits = 1; /* 1 MOSI line */
946 cas_ctl->transfer.rx_nbits = 1; /* 1 MISO line */
947 cas_ctl->transfer.speed_hz = 0; /* Use device setting */
948 cas_ctl->transfer.bits_per_word = 0; /* Use device setting */
949 cas_ctl->transfer.tx_buf = cas_ctl->tx_buf;
950 cas_ctl->transfer.rx_buf = cas_ctl->tx_in_buf;
951 cas_ctl->transfer.delay_usecs = 0;
952 cas_ctl->transfer.cs_change = 0;
953 cas_ctl->transfer.len = sizeof(struct mac_message);
954 cas_ctl->msg.complete = ca8210_spi_transfer_complete;
955 cas_ctl->msg.context = cas_ctl;
956
957 spi_message_add_tail(
958 &cas_ctl->transfer,
959 &cas_ctl->msg
960 );
961
962 status = spi_async(spi, &cas_ctl->msg);
963 if (status < 0) {
964 dev_crit(
965 &spi->dev,
966 "status %d from spi_sync in write\n",
967 status
968 );
969 }
970
971 return status;
972}
973
974/**
975 * ca8210_spi_exchange() - Exchange API/SAP commands with the radio
976 * @buf: Octet array of command being sent downstream
977 * @len: length of buf
978 * @response: buffer for storing synchronous response
979 * @device_ref: spi_device pointer for ca8210
980 *
981 * Effectively calls ca8210_spi_transfer to write buf[] to the spi, then for
982 * synchronous commands waits for the corresponding response to be read from
983 * the spi before returning. The response is written to the response parameter.
984 *
985 * Return: 0 or linux error code
986 */
987static int ca8210_spi_exchange(
988 const u8 *buf,
989 size_t len,
990 u8 *response,
991 void *device_ref
992)
993{
994 int status = 0;
995 struct spi_device *spi = device_ref;
996 struct ca8210_priv *priv = spi->dev.driver_data;
997 long wait_remaining;
998
999 if ((buf[0] & SPI_SYN) && response) { /* if sync wait for confirm */
1000 reinit_completion(&priv->sync_exchange_complete);
1001 priv->sync_command_response = response;
1002 }
1003
1004 do {
1005 reinit_completion(&priv->spi_transfer_complete);
1006 status = ca8210_spi_transfer(priv->spi, buf, len);
1007 if (status) {
1008 dev_warn(
1009 &spi->dev,
1010 "spi write failed, returned %d\n",
1011 status
1012 );
1013 if (status == -EBUSY)
1014 continue;
1015 if (((buf[0] & SPI_SYN) && response))
1016 complete(&priv->sync_exchange_complete);
1017 goto cleanup;
1018 }
1019
1020 wait_remaining = wait_for_completion_interruptible_timeout(
1021 &priv->spi_transfer_complete,
1022 msecs_to_jiffies(1000)
1023 );
1024 if (wait_remaining == -ERESTARTSYS) {
1025 status = -ERESTARTSYS;
1026 } else if (wait_remaining == 0) {
1027 dev_err(
1028 &spi->dev,
1029 "SPI downstream transfer timed out!\n"
1030 );
1031 status = -ETIME;
1032 goto cleanup;
1033 }
1034 } while (status < 0);
1035
1036 if (!((buf[0] & SPI_SYN) && response))
1037 goto cleanup;
1038
1039 wait_remaining = wait_for_completion_interruptible_timeout(
1040 &priv->sync_exchange_complete,
1041 msecs_to_jiffies(CA8210_SYNC_TIMEOUT)
1042 );
1043 if (wait_remaining == -ERESTARTSYS) {
1044 status = -ERESTARTSYS;
1045 } else if (wait_remaining == 0) {
1046 dev_err(
1047 &spi->dev,
1048 "Synchronous confirm timeout\n"
1049 );
1050 status = -ETIME;
1051 }
1052
1053cleanup:
1054 priv->sync_command_response = NULL;
1055 return status;
1056}
1057
1058/**
1059 * ca8210_interrupt_handler() - Called when an irq is received from the ca8210
1060 * @irq: Id of the irq being handled
1061 * @dev_id: Pointer passed by the system, pointing to the ca8210's private data
1062 *
1063 * This function is called when the irq line from the ca8210 is asserted,
1064 * signifying that the ca8210 has a message to send upstream to us. Starts the
1065 * asynchronous spi read.
1066 *
1067 * Return: irq return code
1068 */
1069static irqreturn_t ca8210_interrupt_handler(int irq, void *dev_id)
1070{
1071 struct ca8210_priv *priv = dev_id;
1072 int status;
1073
1074 dev_dbg(&priv->spi->dev, "irq: Interrupt occurred\n");
1075 do {
1076 status = ca8210_spi_transfer(priv->spi, NULL, 0);
1077 if (status && (status != -EBUSY)) {
1078 dev_warn(
1079 &priv->spi->dev,
1080 "spi read failed, returned %d\n",
1081 status
1082 );
1083 }
1084 } while (status == -EBUSY);
1085 return IRQ_HANDLED;
1086}
1087
1088static int (*cascoda_api_downstream)(
1089 const u8 *buf,
1090 size_t len,
1091 u8 *response,
1092 void *device_ref
1093) = ca8210_spi_exchange;
1094
1095/* Cascoda API / 15.4 SAP Primitives */
1096
1097/**
1098 * tdme_setsfr_request_sync() - TDME_SETSFR_request/confirm according to API
1099 * @sfr_page: SFR Page
1100 * @sfr_address: SFR Address
1101 * @sfr_value: SFR Value
1102 * @device_ref: Nondescript pointer to target device
1103 *
1104 * Return: 802.15.4 status code of TDME-SETSFR.confirm
1105 */
1106static u8 tdme_setsfr_request_sync(
1107 u8 sfr_page,
1108 u8 sfr_address,
1109 u8 sfr_value,
1110 void *device_ref
1111)
1112{
1113 int ret;
1114 struct mac_message command, response;
1115 struct spi_device *spi = device_ref;
1116
1117 command.command_id = SPI_TDME_SETSFR_REQUEST;
1118 command.length = 3;
1119 command.pdata.tdme_set_sfr_req.sfr_page = sfr_page;
1120 command.pdata.tdme_set_sfr_req.sfr_address = sfr_address;
1121 command.pdata.tdme_set_sfr_req.sfr_value = sfr_value;
1122 response.command_id = SPI_IDLE;
1123 ret = cascoda_api_downstream(
1124 &command.command_id,
1125 command.length + 2,
1126 &response.command_id,
1127 device_ref
1128 );
1129 if (ret) {
1130 dev_crit(&spi->dev, "cascoda_api_downstream returned %d", ret);
1131 return MAC_SYSTEM_ERROR;
1132 }
1133
1134 if (response.command_id != SPI_TDME_SETSFR_CONFIRM) {
1135 dev_crit(
1136 &spi->dev,
1137 "sync response to SPI_TDME_SETSFR_REQUEST was not SPI_TDME_SETSFR_CONFIRM, it was %d\n",
1138 response.command_id
1139 );
1140 return MAC_SYSTEM_ERROR;
1141 }
1142
1143 return response.pdata.tdme_set_sfr_cnf.status;
1144}
1145
1146/**
1147 * tdme_chipinit() - TDME Chip Register Default Initialisation Macro
1148 * @device_ref: Nondescript pointer to target device
1149 *
1150 * Return: 802.15.4 status code of API calls
1151 */
1152static u8 tdme_chipinit(void *device_ref)
1153{
1154 u8 status = MAC_SUCCESS;
1155 u8 sfr_address;
1156 struct spi_device *spi = device_ref;
1157 struct preamble_cfg_sfr pre_cfg_value = {
1158 .timeout_symbols = 3,
1159 .acquisition_symbols = 3,
1160 .search_symbols = 1,
1161 };
1162 /* LNA Gain Settings */
1163 status = tdme_setsfr_request_sync(
1164 1, (sfr_address = CA8210_SFR_LNAGX40),
1165 LNAGX40_DEFAULT_GAIN, device_ref);
1166 if (status)
1167 goto finish;
1168 status = tdme_setsfr_request_sync(
1169 1, (sfr_address = CA8210_SFR_LNAGX41),
1170 LNAGX41_DEFAULT_GAIN, device_ref);
1171 if (status)
1172 goto finish;
1173 status = tdme_setsfr_request_sync(
1174 1, (sfr_address = CA8210_SFR_LNAGX42),
1175 LNAGX42_DEFAULT_GAIN, device_ref);
1176 if (status)
1177 goto finish;
1178 status = tdme_setsfr_request_sync(
1179 1, (sfr_address = CA8210_SFR_LNAGX43),
1180 LNAGX43_DEFAULT_GAIN, device_ref);
1181 if (status)
1182 goto finish;
1183 status = tdme_setsfr_request_sync(
1184 1, (sfr_address = CA8210_SFR_LNAGX44),
1185 LNAGX44_DEFAULT_GAIN, device_ref);
1186 if (status)
1187 goto finish;
1188 status = tdme_setsfr_request_sync(
1189 1, (sfr_address = CA8210_SFR_LNAGX45),
1190 LNAGX45_DEFAULT_GAIN, device_ref);
1191 if (status)
1192 goto finish;
1193 status = tdme_setsfr_request_sync(
1194 1, (sfr_address = CA8210_SFR_LNAGX46),
1195 LNAGX46_DEFAULT_GAIN, device_ref);
1196 if (status)
1197 goto finish;
1198 status = tdme_setsfr_request_sync(
1199 1, (sfr_address = CA8210_SFR_LNAGX47),
1200 LNAGX47_DEFAULT_GAIN, device_ref);
1201 if (status)
1202 goto finish;
1203 /* Preamble Timing Config */
1204 status = tdme_setsfr_request_sync(
1205 1, (sfr_address = CA8210_SFR_PRECFG),
1206 *((u8 *)&pre_cfg_value), device_ref);
1207 if (status)
1208 goto finish;
1209 /* Preamble Threshold High */
1210 status = tdme_setsfr_request_sync(
1211 1, (sfr_address = CA8210_SFR_PTHRH),
1212 PTHRH_DEFAULT_THRESHOLD, device_ref);
1213 if (status)
1214 goto finish;
1215 /* Tx Output Power 8 dBm */
1216 status = tdme_setsfr_request_sync(
1217 0, (sfr_address = CA8210_SFR_PACFGIB),
1218 PACFGIB_DEFAULT_CURRENT, device_ref);
1219 if (status)
1220 goto finish;
1221
1222finish:
1223 if (status != MAC_SUCCESS) {
1224 dev_err(
1225 &spi->dev,
1226 "failed to set sfr at %#03x, status = %#03x\n",
1227 sfr_address,
1228 status
1229 );
1230 }
1231 return status;
1232}
1233
1234/**
1235 * tdme_channelinit() - TDME Channel Register Default Initialisation Macro (Tx)
1236 * @channel: 802.15.4 channel to initialise chip for
1237 * @device_ref: Nondescript pointer to target device
1238 *
1239 * Return: 802.15.4 status code of API calls
1240 */
1241static u8 tdme_channelinit(u8 channel, void *device_ref)
1242{
1243 /* Transceiver front-end local oscillator tx two-point calibration
1244 * value. Tuned for the hardware.
1245 */
1246 u8 txcalval;
1247
1248 if (channel >= 25)
1249 txcalval = 0xA7;
1250 else if (channel >= 23)
1251 txcalval = 0xA8;
1252 else if (channel >= 22)
1253 txcalval = 0xA9;
1254 else if (channel >= 20)
1255 txcalval = 0xAA;
1256 else if (channel >= 17)
1257 txcalval = 0xAB;
1258 else if (channel >= 16)
1259 txcalval = 0xAC;
1260 else if (channel >= 14)
1261 txcalval = 0xAD;
1262 else if (channel >= 12)
1263 txcalval = 0xAE;
1264 else
1265 txcalval = 0xAF;
1266
1267 return tdme_setsfr_request_sync(
1268 1,
1269 CA8210_SFR_LOTXCAL,
1270 txcalval,
1271 device_ref
1272 ); /* LO Tx Cal */
1273}
1274
1275/**
1276 * tdme_checkpibattribute() - Checks Attribute Values that are not checked in
1277 * MAC
1278 * @pib_attribute: Attribute Number
1279 * @pib_attribute_length: Attribute length
1280 * @pib_attribute_value: Pointer to Attribute Value
1281 * @device_ref: Nondescript pointer to target device
1282 *
1283 * Return: 802.15.4 status code of checks
1284 */
1285static u8 tdme_checkpibattribute(
1286 u8 pib_attribute,
1287 u8 pib_attribute_length,
1288 const void *pib_attribute_value
1289)
1290{
1291 u8 status = MAC_SUCCESS;
1292 u8 value;
1293
1294 value = *((u8 *)pib_attribute_value);
1295
1296 switch (pib_attribute) {
1297 /* PHY */
1298 case PHY_TRANSMIT_POWER:
1299 if (value > 0x3F)
1300 status = MAC_INVALID_PARAMETER;
1301 break;
1302 case PHY_CCA_MODE:
1303 if (value > 0x03)
1304 status = MAC_INVALID_PARAMETER;
1305 break;
1306 /* MAC */
1307 case MAC_BATT_LIFE_EXT_PERIODS:
1308 if ((value < 6) || (value > 41))
1309 status = MAC_INVALID_PARAMETER;
1310 break;
1311 case MAC_BEACON_PAYLOAD:
1312 if (pib_attribute_length > MAX_BEACON_PAYLOAD_LENGTH)
1313 status = MAC_INVALID_PARAMETER;
1314 break;
1315 case MAC_BEACON_PAYLOAD_LENGTH:
1316 if (value > MAX_BEACON_PAYLOAD_LENGTH)
1317 status = MAC_INVALID_PARAMETER;
1318 break;
1319 case MAC_BEACON_ORDER:
1320 if (value > 15)
1321 status = MAC_INVALID_PARAMETER;
1322 break;
1323 case MAC_MAX_BE:
1324 if ((value < 3) || (value > 8))
1325 status = MAC_INVALID_PARAMETER;
1326 break;
1327 case MAC_MAX_CSMA_BACKOFFS:
1328 if (value > 5)
1329 status = MAC_INVALID_PARAMETER;
1330 break;
1331 case MAC_MAX_FRAME_RETRIES:
1332 if (value > 7)
1333 status = MAC_INVALID_PARAMETER;
1334 break;
1335 case MAC_MIN_BE:
1336 if (value > 8)
1337 status = MAC_INVALID_PARAMETER;
1338 break;
1339 case MAC_RESPONSE_WAIT_TIME:
1340 if ((value < 2) || (value > 64))
1341 status = MAC_INVALID_PARAMETER;
1342 break;
1343 case MAC_SUPERFRAME_ORDER:
1344 if (value > 15)
1345 status = MAC_INVALID_PARAMETER;
1346 break;
1347 /* boolean */
1348 case MAC_ASSOCIATED_PAN_COORD:
1349 case MAC_ASSOCIATION_PERMIT:
1350 case MAC_AUTO_REQUEST:
1351 case MAC_BATT_LIFE_EXT:
1352 case MAC_GTS_PERMIT:
1353 case MAC_PROMISCUOUS_MODE:
1354 case MAC_RX_ON_WHEN_IDLE:
1355 case MAC_SECURITY_ENABLED:
1356 if (value > 1)
1357 status = MAC_INVALID_PARAMETER;
1358 break;
1359 /* MAC SEC */
1360 case MAC_AUTO_REQUEST_SECURITY_LEVEL:
1361 if (value > 7)
1362 status = MAC_INVALID_PARAMETER;
1363 break;
1364 case MAC_AUTO_REQUEST_KEY_ID_MODE:
1365 if (value > 3)
1366 status = MAC_INVALID_PARAMETER;
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 return status;
1373}
1374
1375/**
1376 * tdme_settxpower() - Sets the tx power for MLME_SET phyTransmitPower
1377 * @txp: Transmit Power
1378 * @device_ref: Nondescript pointer to target device
1379 *
1380 * Normalised to 802.15.4 Definition (6-bit, signed):
1381 * Bit 7-6: not used
1382 * Bit 5-0: tx power (-32 - +31 dB)
1383 *
1384 * Return: 802.15.4 status code of api calls
1385 */
1386static u8 tdme_settxpower(u8 txp, void *device_ref)
1387{
1388 u8 status;
1389 s8 txp_val;
1390 u8 txp_ext;
1391 union pa_cfg_sfr pa_cfg_val;
1392
1393 /* extend from 6 to 8 bit */
1394 txp_ext = 0x3F & txp;
1395 if (txp_ext & 0x20)
1396 txp_ext += 0xC0;
1397 txp_val = (s8)txp_ext;
1398
1399 if (CA8210_MAC_MPW) {
1400 if (txp_val > 0) {
1401 /* 8 dBm: ptrim = 5, itrim = +3 => +4 dBm */
1402 pa_cfg_val.bias_current_trim = 3;
1403 pa_cfg_val.buffer_capacitor_trim = 5;
1404 pa_cfg_val.boost = 1;
1405 } else {
1406 /* 0 dBm: ptrim = 7, itrim = +3 => -6 dBm */
1407 pa_cfg_val.bias_current_trim = 3;
1408 pa_cfg_val.buffer_capacitor_trim = 7;
1409 pa_cfg_val.boost = 0;
1410 }
1411 /* write PACFG */
1412 status = tdme_setsfr_request_sync(
1413 0,
1414 CA8210_SFR_PACFG,
1415 pa_cfg_val.paib,
1416 device_ref
1417 );
1418 } else {
1419 /* Look-Up Table for Setting Current and Frequency Trim values
1420 * for desired Output Power
1421 */
1422 if (txp_val > 8) {
1423 pa_cfg_val.paib = 0x3F;
1424 } else if (txp_val == 8) {
1425 pa_cfg_val.paib = 0x32;
1426 } else if (txp_val == 7) {
1427 pa_cfg_val.paib = 0x22;
1428 } else if (txp_val == 6) {
1429 pa_cfg_val.paib = 0x18;
1430 } else if (txp_val == 5) {
1431 pa_cfg_val.paib = 0x10;
1432 } else if (txp_val == 4) {
1433 pa_cfg_val.paib = 0x0C;
1434 } else if (txp_val == 3) {
1435 pa_cfg_val.paib = 0x08;
1436 } else if (txp_val == 2) {
1437 pa_cfg_val.paib = 0x05;
1438 } else if (txp_val == 1) {
1439 pa_cfg_val.paib = 0x03;
1440 } else if (txp_val == 0) {
1441 pa_cfg_val.paib = 0x01;
1442 } else { /* < 0 */
1443 pa_cfg_val.paib = 0x00;
1444 }
1445 /* write PACFGIB */
1446 status = tdme_setsfr_request_sync(
1447 0,
1448 CA8210_SFR_PACFGIB,
1449 pa_cfg_val.paib,
1450 device_ref
1451 );
1452 }
1453
1454 return status;
1455}
1456
1457/**
1458 * mcps_data_request() - mcps_data_request (Send Data) according to API Spec
1459 * @src_addr_mode: Source Addressing Mode
1460 * @dst_address_mode: Destination Addressing Mode
1461 * @dst_pan_id: Destination PAN ID
1462 * @dst_addr: Pointer to Destination Address
1463 * @msdu_length: length of Data
1464 * @msdu: Pointer to Data
1465 * @msdu_handle: Handle of Data
1466 * @tx_options: Tx Options Bit Field
1467 * @security: Pointer to Security Structure or NULL
1468 * @device_ref: Nondescript pointer to target device
1469 *
1470 * Return: 802.15.4 status code of action
1471 */
1472static u8 mcps_data_request(
1473 u8 src_addr_mode,
1474 u8 dst_address_mode,
1475 u16 dst_pan_id,
1476 union macaddr *dst_addr,
1477 u8 msdu_length,
1478 u8 *msdu,
1479 u8 msdu_handle,
1480 u8 tx_options,
1481 struct secspec *security,
1482 void *device_ref
1483)
1484{
1485 struct secspec *psec;
1486 struct mac_message command;
1487
1488 command.command_id = SPI_MCPS_DATA_REQUEST;
1489 command.pdata.data_req.src_addr_mode = src_addr_mode;
1490 command.pdata.data_req.dst.mode = dst_address_mode;
1491 if (dst_address_mode != MAC_MODE_NO_ADDR) {
1492 command.pdata.data_req.dst.pan_id[0] = LS_BYTE(dst_pan_id);
1493 command.pdata.data_req.dst.pan_id[1] = MS_BYTE(dst_pan_id);
1494 if (dst_address_mode == MAC_MODE_SHORT_ADDR) {
1495 command.pdata.data_req.dst.address[0] = LS_BYTE(
1496 dst_addr->short_address
1497 );
1498 command.pdata.data_req.dst.address[1] = MS_BYTE(
1499 dst_addr->short_address
1500 );
1501 } else { /* MAC_MODE_LONG_ADDR*/
1502 memcpy(
1503 command.pdata.data_req.dst.address,
1504 dst_addr->ieee_address,
1505 8
1506 );
1507 }
1508 }
1509 command.pdata.data_req.msdu_length = msdu_length;
1510 command.pdata.data_req.msdu_handle = msdu_handle;
1511 command.pdata.data_req.tx_options = tx_options;
1512 memcpy(command.pdata.data_req.msdu, msdu, msdu_length);
1513 psec = (struct secspec *)(command.pdata.data_req.msdu + msdu_length);
1514 command.length = sizeof(struct mcps_data_request_pset) -
1515 MAX_DATA_SIZE + msdu_length;
1516 if (!security || (security->security_level == 0)) {
1517 psec->security_level = 0;
1518 command.length += 1;
1519 } else {
1520 *psec = *security;
1521 command.length += sizeof(struct secspec);
1522 }
1523
1524 if (ca8210_spi_transfer(device_ref, &command.command_id,
1525 command.length + 2))
1526 return MAC_SYSTEM_ERROR;
1527
1528 return MAC_SUCCESS;
1529}
1530
1531/**
1532 * mlme_reset_request_sync() - MLME_RESET_request/confirm according to API Spec
1533 * @set_default_pib: Set defaults in PIB
1534 * @device_ref: Nondescript pointer to target device
1535 *
1536 * Return: 802.15.4 status code of MLME-RESET.confirm
1537 */
1538static u8 mlme_reset_request_sync(
1539 u8 set_default_pib,
1540 void *device_ref
1541)
1542{
1543 u8 status;
1544 struct mac_message command, response;
1545 struct spi_device *spi = device_ref;
1546
1547 command.command_id = SPI_MLME_RESET_REQUEST;
1548 command.length = 1;
1549 command.pdata.u8param = set_default_pib;
1550
1551 if (cascoda_api_downstream(
1552 &command.command_id,
1553 command.length + 2,
1554 &response.command_id,
1555 device_ref)) {
1556 dev_err(&spi->dev, "cascoda_api_downstream failed\n");
1557 return MAC_SYSTEM_ERROR;
1558 }
1559
1560 if (response.command_id != SPI_MLME_RESET_CONFIRM)
1561 return MAC_SYSTEM_ERROR;
1562
1563 status = response.pdata.status;
1564
1565 /* reset COORD Bit for Channel Filtering as Coordinator */
1566 if (CA8210_MAC_WORKAROUNDS && set_default_pib && (!status)) {
1567 status = tdme_setsfr_request_sync(
1568 0,
1569 CA8210_SFR_MACCON,
1570 0,
1571 device_ref
1572 );
1573 }
1574
1575 return status;
1576}
1577
1578/**
1579 * mlme_set_request_sync() - MLME_SET_request/confirm according to API Spec
1580 * @pib_attribute: Attribute Number
1581 * @pib_attribute_index: Index within Attribute if an Array
1582 * @pib_attribute_length: Attribute length
1583 * @pib_attribute_value: Pointer to Attribute Value
1584 * @device_ref: Nondescript pointer to target device
1585 *
1586 * Return: 802.15.4 status code of MLME-SET.confirm
1587 */
1588static u8 mlme_set_request_sync(
1589 u8 pib_attribute,
1590 u8 pib_attribute_index,
1591 u8 pib_attribute_length,
1592 const void *pib_attribute_value,
1593 void *device_ref
1594)
1595{
1596 u8 status;
1597 struct mac_message command, response;
1598
1599 /* pre-check the validity of pib_attribute values that are not checked
1600 * in MAC
1601 */
1602 if (tdme_checkpibattribute(
1603 pib_attribute, pib_attribute_length, pib_attribute_value)) {
1604 return MAC_INVALID_PARAMETER;
1605 }
1606
1607 if (pib_attribute == PHY_CURRENT_CHANNEL) {
1608 status = tdme_channelinit(
1609 *((u8 *)pib_attribute_value),
1610 device_ref
1611 );
1612 if (status)
1613 return status;
1614 }
1615
1616 if (pib_attribute == PHY_TRANSMIT_POWER) {
1617 return tdme_settxpower(
1618 *((u8 *)pib_attribute_value),
1619 device_ref
1620 );
1621 }
1622
1623 command.command_id = SPI_MLME_SET_REQUEST;
1624 command.length = sizeof(struct mlme_set_request_pset) -
1625 MAX_ATTRIBUTE_SIZE + pib_attribute_length;
1626 command.pdata.set_req.pib_attribute = pib_attribute;
1627 command.pdata.set_req.pib_attribute_index = pib_attribute_index;
1628 command.pdata.set_req.pib_attribute_length = pib_attribute_length;
1629 memcpy(
1630 command.pdata.set_req.pib_attribute_value,
1631 pib_attribute_value,
1632 pib_attribute_length
1633 );
1634
1635 if (cascoda_api_downstream(
1636 &command.command_id,
1637 command.length + 2,
1638 &response.command_id,
1639 device_ref)) {
1640 return MAC_SYSTEM_ERROR;
1641 }
1642
1643 if (response.command_id != SPI_MLME_SET_CONFIRM)
1644 return MAC_SYSTEM_ERROR;
1645
1646 return response.pdata.status;
1647}
1648
1649/**
1650 * hwme_set_request_sync() - HWME_SET_request/confirm according to API Spec
1651 * @hw_attribute: Attribute Number
1652 * @hw_attribute_length: Attribute length
1653 * @hw_attribute_value: Pointer to Attribute Value
1654 * @device_ref: Nondescript pointer to target device
1655 *
1656 * Return: 802.15.4 status code of HWME-SET.confirm
1657 */
1658static u8 hwme_set_request_sync(
1659 u8 hw_attribute,
1660 u8 hw_attribute_length,
1661 u8 *hw_attribute_value,
1662 void *device_ref
1663)
1664{
1665 struct mac_message command, response;
1666
1667 command.command_id = SPI_HWME_SET_REQUEST;
1668 command.length = 2 + hw_attribute_length;
1669 command.pdata.hwme_set_req.hw_attribute = hw_attribute;
1670 command.pdata.hwme_set_req.hw_attribute_length = hw_attribute_length;
1671 memcpy(
1672 command.pdata.hwme_set_req.hw_attribute_value,
1673 hw_attribute_value,
1674 hw_attribute_length
1675 );
1676
1677 if (cascoda_api_downstream(
1678 &command.command_id,
1679 command.length + 2,
1680 &response.command_id,
1681 device_ref)) {
1682 return MAC_SYSTEM_ERROR;
1683 }
1684
1685 if (response.command_id != SPI_HWME_SET_CONFIRM)
1686 return MAC_SYSTEM_ERROR;
1687
1688 return response.pdata.hwme_set_cnf.status;
1689}
1690
1691/**
1692 * hwme_get_request_sync() - HWME_GET_request/confirm according to API Spec
1693 * @hw_attribute: Attribute Number
1694 * @hw_attribute_length: Attribute length
1695 * @hw_attribute_value: Pointer to Attribute Value
1696 * @device_ref: Nondescript pointer to target device
1697 *
1698 * Return: 802.15.4 status code of HWME-GET.confirm
1699 */
1700static u8 hwme_get_request_sync(
1701 u8 hw_attribute,
1702 u8 *hw_attribute_length,
1703 u8 *hw_attribute_value,
1704 void *device_ref
1705)
1706{
1707 struct mac_message command, response;
1708
1709 command.command_id = SPI_HWME_GET_REQUEST;
1710 command.length = 1;
1711 command.pdata.hwme_get_req.hw_attribute = hw_attribute;
1712
1713 if (cascoda_api_downstream(
1714 &command.command_id,
1715 command.length + 2,
1716 &response.command_id,
1717 device_ref)) {
1718 return MAC_SYSTEM_ERROR;
1719 }
1720
1721 if (response.command_id != SPI_HWME_GET_CONFIRM)
1722 return MAC_SYSTEM_ERROR;
1723
1724 if (response.pdata.hwme_get_cnf.status == MAC_SUCCESS) {
1725 *hw_attribute_length =
1726 response.pdata.hwme_get_cnf.hw_attribute_length;
1727 memcpy(
1728 hw_attribute_value,
1729 response.pdata.hwme_get_cnf.hw_attribute_value,
1730 *hw_attribute_length
1731 );
1732 }
1733
1734 return response.pdata.hwme_get_cnf.status;
1735}
1736
1737/* Network driver operation */
1738
1739/**
1740 * ca8210_async_xmit_complete() - Called to announce that an asynchronous
1741 * transmission has finished
1742 * @hw: ieee802154_hw of ca8210 that has finished exchange
1743 * @msduhandle: Identifier of transmission that has completed
1744 * @status: Returned 802.15.4 status code of the transmission
1745 *
1746 * Return: 0 or linux error code
1747 */
1748static int ca8210_async_xmit_complete(
1749 struct ieee802154_hw *hw,
1750 u8 msduhandle,
1751 u8 status)
1752{
1753 struct ca8210_priv *priv = hw->priv;
1754
1755 if (priv->nextmsduhandle != msduhandle) {
1756 dev_err(
1757 &priv->spi->dev,
1758 "Unexpected msdu_handle on data confirm, Expected %d, got %d\n",
1759 priv->nextmsduhandle,
1760 msduhandle
1761 );
1762 return -EIO;
1763 }
1764
1765 priv->async_tx_pending = false;
1766 priv->nextmsduhandle++;
1767
1768 if (status) {
1769 dev_err(
1770 &priv->spi->dev,
1771 "Link transmission unsuccessful, status = %d\n",
1772 status
1773 );
1774 if (status != MAC_TRANSACTION_OVERFLOW) {
1775 ieee802154_wake_queue(priv->hw);
1776 return 0;
1777 }
1778 }
1779 ieee802154_xmit_complete(priv->hw, priv->tx_skb, true);
1780
1781 return 0;
1782}
1783
1784/**
1785 * ca8210_skb_rx() - Contructs a properly framed socket buffer from a received
1786 * MCPS_DATA_indication
1787 * @hw: ieee802154_hw that MCPS_DATA_indication was received by
1788 * @len: length of MCPS_DATA_indication
1789 * @data_ind: Octet array of MCPS_DATA_indication
1790 *
1791 * Called by the spi driver whenever a SAP command is received, this function
1792 * will ascertain whether the command is of interest to the network driver and
1793 * take necessary action.
1794 *
1795 * Return: 0 or linux error code
1796 */
1797static int ca8210_skb_rx(
1798 struct ieee802154_hw *hw,
1799 size_t len,
1800 u8 *data_ind
1801)
1802{
1803 struct ieee802154_hdr hdr;
1804 int msdulen;
1805 int hlen;
1806 u8 mpdulinkquality = data_ind[23];
1807 struct sk_buff *skb;
1808 struct ca8210_priv *priv = hw->priv;
1809
1810 /* Allocate mtu size buffer for every rx packet */
1811 skb = dev_alloc_skb(IEEE802154_MTU + sizeof(hdr));
Markus Elfring3a21bf52017-05-22 08:03:17 +02001812 if (!skb)
Harry Morrisded845a2017-03-28 13:08:58 +01001813 return -ENOMEM;
Markus Elfring3a21bf52017-05-22 08:03:17 +02001814
Harry Morrisded845a2017-03-28 13:08:58 +01001815 skb_reserve(skb, sizeof(hdr));
1816
1817 msdulen = data_ind[22]; /* msdu_length */
1818 if (msdulen > IEEE802154_MTU) {
1819 dev_err(
1820 &priv->spi->dev,
1821 "received erroneously large msdu length!\n"
1822 );
1823 kfree_skb(skb);
1824 return -EMSGSIZE;
1825 }
1826 dev_dbg(&priv->spi->dev, "skb buffer length = %d\n", msdulen);
1827
1828 if (priv->promiscuous)
1829 goto copy_payload;
1830
1831 /* Populate hdr */
1832 hdr.sec.level = data_ind[29 + msdulen];
1833 dev_dbg(&priv->spi->dev, "security level: %#03x\n", hdr.sec.level);
1834 if (hdr.sec.level > 0) {
1835 hdr.sec.key_id_mode = data_ind[30 + msdulen];
1836 memcpy(&hdr.sec.extended_src, &data_ind[31 + msdulen], 8);
1837 hdr.sec.key_id = data_ind[39 + msdulen];
1838 }
1839 hdr.source.mode = data_ind[0];
1840 dev_dbg(&priv->spi->dev, "srcAddrMode: %#03x\n", hdr.source.mode);
1841 hdr.source.pan_id = *(u16 *)&data_ind[1];
1842 dev_dbg(&priv->spi->dev, "srcPanId: %#06x\n", hdr.source.pan_id);
1843 memcpy(&hdr.source.extended_addr, &data_ind[3], 8);
1844 hdr.dest.mode = data_ind[11];
1845 dev_dbg(&priv->spi->dev, "dstAddrMode: %#03x\n", hdr.dest.mode);
1846 hdr.dest.pan_id = *(u16 *)&data_ind[12];
1847 dev_dbg(&priv->spi->dev, "dstPanId: %#06x\n", hdr.dest.pan_id);
1848 memcpy(&hdr.dest.extended_addr, &data_ind[14], 8);
1849
1850 /* Fill in FC implicitly */
1851 hdr.fc.type = 1; /* Data frame */
1852 if (hdr.sec.level)
1853 hdr.fc.security_enabled = 1;
1854 else
1855 hdr.fc.security_enabled = 0;
1856 if (data_ind[1] != data_ind[12] || data_ind[2] != data_ind[13])
1857 hdr.fc.intra_pan = 1;
1858 else
1859 hdr.fc.intra_pan = 0;
1860 hdr.fc.dest_addr_mode = hdr.dest.mode;
1861 hdr.fc.source_addr_mode = hdr.source.mode;
1862
1863 /* Add hdr to front of buffer */
1864 hlen = ieee802154_hdr_push(skb, &hdr);
1865
1866 if (hlen < 0) {
1867 dev_crit(&priv->spi->dev, "failed to push mac hdr onto skb!\n");
1868 kfree_skb(skb);
1869 return hlen;
1870 }
1871
1872 skb_reset_mac_header(skb);
1873 skb->mac_len = hlen;
1874
1875copy_payload:
1876 /* Add <msdulen> bytes of space to the back of the buffer */
1877 /* Copy msdu to skb */
Johannes Berg59ae1d12017-06-16 14:29:20 +02001878 skb_put_data(skb, &data_ind[29], msdulen);
Harry Morrisded845a2017-03-28 13:08:58 +01001879
1880 ieee802154_rx_irqsafe(hw, skb, mpdulinkquality);
1881 return 0;
1882}
1883
1884/**
1885 * ca8210_net_rx() - Acts upon received SAP commands relevant to the network
1886 * driver
1887 * @hw: ieee802154_hw that command was received by
1888 * @command: Octet array of received command
1889 * @len: length of the received command
1890 *
1891 * Called by the spi driver whenever a SAP command is received, this function
1892 * will ascertain whether the command is of interest to the network driver and
1893 * take necessary action.
1894 *
1895 * Return: 0 or linux error code
1896 */
1897static int ca8210_net_rx(struct ieee802154_hw *hw, u8 *command, size_t len)
1898{
1899 struct ca8210_priv *priv = hw->priv;
1900 unsigned long flags;
1901 u8 status;
1902
1903 dev_dbg(&priv->spi->dev, "ca8210_net_rx(), CmdID = %d\n", command[0]);
1904
1905 if (command[0] == SPI_MCPS_DATA_INDICATION) {
1906 /* Received data */
1907 spin_lock_irqsave(&priv->lock, flags);
1908 if (command[26] == priv->last_dsn) {
1909 dev_dbg(
1910 &priv->spi->dev,
1911 "DSN %d resend received, ignoring...\n",
1912 command[26]
1913 );
1914 spin_unlock_irqrestore(&priv->lock, flags);
1915 return 0;
1916 }
1917 priv->last_dsn = command[26];
1918 spin_unlock_irqrestore(&priv->lock, flags);
1919 return ca8210_skb_rx(hw, len - 2, command + 2);
1920 } else if (command[0] == SPI_MCPS_DATA_CONFIRM) {
1921 status = command[3];
1922 if (priv->async_tx_pending) {
1923 return ca8210_async_xmit_complete(
1924 hw,
1925 command[2],
1926 status
1927 );
1928 }
1929 }
1930
1931 return 0;
1932}
1933
1934/**
1935 * ca8210_skb_tx() - Transmits a given socket buffer using the ca8210
1936 * @skb: Socket buffer to transmit
1937 * @msduhandle: Data identifier to pass to the 802.15.4 MAC
1938 * @priv: Pointer to private data section of target ca8210
1939 *
1940 * Return: 0 or linux error code
1941 */
1942static int ca8210_skb_tx(
1943 struct sk_buff *skb,
1944 u8 msduhandle,
1945 struct ca8210_priv *priv
1946)
1947{
1948 int status;
1949 struct ieee802154_hdr header = { 0 };
1950 struct secspec secspec;
1951 unsigned int mac_len;
1952
1953 dev_dbg(&priv->spi->dev, "ca8210_skb_tx() called\n");
1954
1955 /* Get addressing info from skb - ieee802154 layer creates a full
1956 * packet
1957 */
1958 mac_len = ieee802154_hdr_peek_addrs(skb, &header);
1959
1960 secspec.security_level = header.sec.level;
1961 secspec.key_id_mode = header.sec.key_id_mode;
1962 if (secspec.key_id_mode == 2)
1963 memcpy(secspec.key_source, &header.sec.short_src, 4);
1964 else if (secspec.key_id_mode == 3)
1965 memcpy(secspec.key_source, &header.sec.extended_src, 8);
1966 secspec.key_index = header.sec.key_id;
1967
1968 /* Pass to Cascoda API */
1969 status = mcps_data_request(
1970 header.source.mode,
1971 header.dest.mode,
1972 header.dest.pan_id,
1973 (union macaddr *)&header.dest.extended_addr,
1974 skb->len - mac_len,
1975 &skb->data[mac_len],
1976 msduhandle,
1977 header.fc.ack_request,
1978 &secspec,
1979 priv->spi
1980 );
1981 return link_to_linux_err(status);
1982}
1983
1984/**
1985 * ca8210_start() - Starts the network driver
1986 * @hw: ieee802154_hw of ca8210 being started
1987 *
1988 * Return: 0 or linux error code
1989 */
1990static int ca8210_start(struct ieee802154_hw *hw)
1991{
1992 int status;
1993 u8 rx_on_when_idle;
1994 u8 lqi_threshold = 0;
1995 struct ca8210_priv *priv = hw->priv;
1996
1997 priv->last_dsn = -1;
1998 /* Turn receiver on when idle for now just to test rx */
1999 rx_on_when_idle = 1;
2000 status = mlme_set_request_sync(
2001 MAC_RX_ON_WHEN_IDLE,
2002 0,
2003 1,
2004 &rx_on_when_idle,
2005 priv->spi
2006 );
2007 if (status) {
2008 dev_crit(
2009 &priv->spi->dev,
2010 "Setting rx_on_when_idle failed, status = %d\n",
2011 status
2012 );
2013 return link_to_linux_err(status);
2014 }
2015 status = hwme_set_request_sync(
2016 HWME_LQILIMIT,
2017 1,
2018 &lqi_threshold,
2019 priv->spi
2020 );
2021 if (status) {
2022 dev_crit(
2023 &priv->spi->dev,
2024 "Setting lqilimit failed, status = %d\n",
2025 status
2026 );
2027 return link_to_linux_err(status);
2028 }
2029
2030 return 0;
2031}
2032
2033/**
2034 * ca8210_stop() - Stops the network driver
2035 * @hw: ieee802154_hw of ca8210 being stopped
2036 *
2037 * Return: 0 or linux error code
2038 */
2039static void ca8210_stop(struct ieee802154_hw *hw)
2040{
2041}
2042
2043/**
2044 * ca8210_xmit_async() - Asynchronously transmits a given socket buffer using
2045 * the ca8210
2046 * @hw: ieee802154_hw of ca8210 to transmit from
2047 * @skb: Socket buffer to transmit
2048 *
2049 * Return: 0 or linux error code
2050 */
2051static int ca8210_xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb)
2052{
2053 struct ca8210_priv *priv = hw->priv;
2054 int status;
2055
2056 dev_dbg(&priv->spi->dev, "calling ca8210_xmit_async()\n");
2057
2058 priv->tx_skb = skb;
2059 priv->async_tx_pending = true;
2060 status = ca8210_skb_tx(skb, priv->nextmsduhandle, priv);
2061 return status;
2062}
2063
2064/**
2065 * ca8210_get_ed() - Returns the measured energy on the current channel at this
2066 * instant in time
2067 * @hw: ieee802154_hw of target ca8210
2068 * @level: Measured Energy Detect level
2069 *
2070 * Return: 0 or linux error code
2071 */
2072static int ca8210_get_ed(struct ieee802154_hw *hw, u8 *level)
2073{
2074 u8 lenvar;
2075 struct ca8210_priv *priv = hw->priv;
2076
2077 return link_to_linux_err(
2078 hwme_get_request_sync(HWME_EDVALUE, &lenvar, level, priv->spi)
2079 );
2080}
2081
2082/**
2083 * ca8210_set_channel() - Sets the current operating 802.15.4 channel of the
2084 * ca8210
2085 * @hw: ieee802154_hw of target ca8210
2086 * @page: Channel page to set
2087 * @channel: Channel number to set
2088 *
2089 * Return: 0 or linux error code
2090 */
2091static int ca8210_set_channel(
2092 struct ieee802154_hw *hw,
2093 u8 page,
2094 u8 channel
2095)
2096{
2097 u8 status;
2098 struct ca8210_priv *priv = hw->priv;
2099
2100 status = mlme_set_request_sync(
2101 PHY_CURRENT_CHANNEL,
2102 0,
2103 1,
2104 &channel,
2105 priv->spi
2106 );
2107 if (status) {
2108 dev_err(
2109 &priv->spi->dev,
2110 "error setting channel, MLME-SET.confirm status = %d\n",
2111 status
2112 );
2113 }
2114 return link_to_linux_err(status);
2115}
2116
2117/**
2118 * ca8210_set_hw_addr_filt() - Sets the address filtering parameters of the
2119 * ca8210
2120 * @hw: ieee802154_hw of target ca8210
2121 * @filt: Filtering parameters
2122 * @changed: Bitmap representing which parameters to change
2123 *
2124 * Effectively just sets the actual addressing information identifying this node
2125 * as all filtering is performed by the ca8210 as detailed in the IEEE 802.15.4
2126 * 2006 specification.
2127 *
2128 * Return: 0 or linux error code
2129 */
2130static int ca8210_set_hw_addr_filt(
2131 struct ieee802154_hw *hw,
2132 struct ieee802154_hw_addr_filt *filt,
2133 unsigned long changed
2134)
2135{
2136 u8 status = 0;
2137 struct ca8210_priv *priv = hw->priv;
2138
2139 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
2140 status = mlme_set_request_sync(
2141 MAC_PAN_ID,
2142 0,
2143 2,
2144 &filt->pan_id, priv->spi
2145 );
2146 if (status) {
2147 dev_err(
2148 &priv->spi->dev,
2149 "error setting pan id, MLME-SET.confirm status = %d",
2150 status
2151 );
2152 return link_to_linux_err(status);
2153 }
2154 }
2155 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
2156 status = mlme_set_request_sync(
2157 MAC_SHORT_ADDRESS,
2158 0,
2159 2,
2160 &filt->short_addr, priv->spi
2161 );
2162 if (status) {
2163 dev_err(
2164 &priv->spi->dev,
2165 "error setting short address, MLME-SET.confirm status = %d",
2166 status
2167 );
2168 return link_to_linux_err(status);
2169 }
2170 }
2171 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
2172 status = mlme_set_request_sync(
2173 NS_IEEE_ADDRESS,
2174 0,
2175 8,
2176 &filt->ieee_addr,
2177 priv->spi
2178 );
2179 if (status) {
2180 dev_err(
2181 &priv->spi->dev,
2182 "error setting ieee address, MLME-SET.confirm status = %d",
2183 status
2184 );
2185 return link_to_linux_err(status);
2186 }
2187 }
2188 /* TODO: Should use MLME_START to set coord bit? */
2189 return 0;
2190}
2191
2192/**
2193 * ca8210_set_tx_power() - Sets the transmit power of the ca8210
2194 * @hw: ieee802154_hw of target ca8210
2195 * @mbm: Transmit power in mBm (dBm*100)
2196 *
2197 * Return: 0 or linux error code
2198 */
2199static int ca8210_set_tx_power(struct ieee802154_hw *hw, s32 mbm)
2200{
2201 struct ca8210_priv *priv = hw->priv;
2202
2203 mbm /= 100;
2204 return link_to_linux_err(
2205 mlme_set_request_sync(PHY_TRANSMIT_POWER, 0, 1, &mbm, priv->spi)
2206 );
2207}
2208
2209/**
2210 * ca8210_set_cca_mode() - Sets the clear channel assessment mode of the ca8210
2211 * @hw: ieee802154_hw of target ca8210
2212 * @cca: CCA mode to set
2213 *
2214 * Return: 0 or linux error code
2215 */
2216static int ca8210_set_cca_mode(
2217 struct ieee802154_hw *hw,
2218 const struct wpan_phy_cca *cca
2219)
2220{
2221 u8 status;
2222 u8 cca_mode;
2223 struct ca8210_priv *priv = hw->priv;
2224
2225 cca_mode = cca->mode & 3;
2226 if (cca_mode == 3 && cca->opt == NL802154_CCA_OPT_ENERGY_CARRIER_OR) {
2227 /* cca_mode 0 == CS OR ED, 3 == CS AND ED */
2228 cca_mode = 0;
2229 }
2230 status = mlme_set_request_sync(
2231 PHY_CCA_MODE,
2232 0,
2233 1,
2234 &cca_mode,
2235 priv->spi
2236 );
2237 if (status) {
2238 dev_err(
2239 &priv->spi->dev,
2240 "error setting cca mode, MLME-SET.confirm status = %d",
2241 status
2242 );
2243 }
2244 return link_to_linux_err(status);
2245}
2246
2247/**
2248 * ca8210_set_cca_ed_level() - Sets the CCA ED level of the ca8210
2249 * @hw: ieee802154_hw of target ca8210
2250 * @level: ED level to set (in mbm)
2251 *
2252 * Sets the minimum threshold of measured energy above which the ca8210 will
2253 * back off and retry a transmission.
2254 *
2255 * Return: 0 or linux error code
2256 */
2257static int ca8210_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
2258{
2259 u8 status;
2260 u8 ed_threshold = (level / 100) * 2 + 256;
2261 struct ca8210_priv *priv = hw->priv;
2262
2263 status = hwme_set_request_sync(
2264 HWME_EDTHRESHOLD,
2265 1,
2266 &ed_threshold,
2267 priv->spi
2268 );
2269 if (status) {
2270 dev_err(
2271 &priv->spi->dev,
2272 "error setting ed threshold, HWME-SET.confirm status = %d",
2273 status
2274 );
2275 }
2276 return link_to_linux_err(status);
2277}
2278
2279/**
2280 * ca8210_set_csma_params() - Sets the CSMA parameters of the ca8210
2281 * @hw: ieee802154_hw of target ca8210
2282 * @min_be: Minimum backoff exponent when backing off a transmission
2283 * @max_be: Maximum backoff exponent when backing off a transmission
2284 * @retries: Number of times to retry after backing off
2285 *
2286 * Return: 0 or linux error code
2287 */
2288static int ca8210_set_csma_params(
2289 struct ieee802154_hw *hw,
2290 u8 min_be,
2291 u8 max_be,
2292 u8 retries
2293)
2294{
2295 u8 status;
2296 struct ca8210_priv *priv = hw->priv;
2297
2298 status = mlme_set_request_sync(MAC_MIN_BE, 0, 1, &min_be, priv->spi);
2299 if (status) {
2300 dev_err(
2301 &priv->spi->dev,
2302 "error setting min be, MLME-SET.confirm status = %d",
2303 status
2304 );
2305 return link_to_linux_err(status);
2306 }
2307 status = mlme_set_request_sync(MAC_MAX_BE, 0, 1, &max_be, priv->spi);
2308 if (status) {
2309 dev_err(
2310 &priv->spi->dev,
2311 "error setting max be, MLME-SET.confirm status = %d",
2312 status
2313 );
2314 return link_to_linux_err(status);
2315 }
2316 status = mlme_set_request_sync(
2317 MAC_MAX_CSMA_BACKOFFS,
2318 0,
2319 1,
2320 &retries,
2321 priv->spi
2322 );
2323 if (status) {
2324 dev_err(
2325 &priv->spi->dev,
2326 "error setting max csma backoffs, MLME-SET.confirm status = %d",
2327 status
2328 );
2329 }
2330 return link_to_linux_err(status);
2331}
2332
2333/**
2334 * ca8210_set_frame_retries() - Sets the maximum frame retries of the ca8210
2335 * @hw: ieee802154_hw of target ca8210
2336 * @retries: Number of retries
2337 *
2338 * Sets the number of times to retry a transmission if no acknowledgment was
2339 * was received from the other end when one was requested.
2340 *
2341 * Return: 0 or linux error code
2342 */
2343static int ca8210_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
2344{
2345 u8 status;
2346 struct ca8210_priv *priv = hw->priv;
2347
2348 status = mlme_set_request_sync(
2349 MAC_MAX_FRAME_RETRIES,
2350 0,
2351 1,
2352 &retries,
2353 priv->spi
2354 );
2355 if (status) {
2356 dev_err(
2357 &priv->spi->dev,
2358 "error setting frame retries, MLME-SET.confirm status = %d",
2359 status
2360 );
2361 }
2362 return link_to_linux_err(status);
2363}
2364
2365static int ca8210_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
2366{
2367 u8 status;
2368 struct ca8210_priv *priv = hw->priv;
2369
2370 status = mlme_set_request_sync(
2371 MAC_PROMISCUOUS_MODE,
2372 0,
2373 1,
2374 (const void*)&on,
2375 priv->spi
2376 );
2377 if (status) {
2378 dev_err(
2379 &priv->spi->dev,
2380 "error setting promiscuous mode, MLME-SET.confirm status = %d",
2381 status
2382 );
2383 } else {
2384 priv->promiscuous = on;
2385 }
2386 return link_to_linux_err(status);
2387}
2388
2389static const struct ieee802154_ops ca8210_phy_ops = {
2390 .start = ca8210_start,
2391 .stop = ca8210_stop,
2392 .xmit_async = ca8210_xmit_async,
2393 .ed = ca8210_get_ed,
2394 .set_channel = ca8210_set_channel,
2395 .set_hw_addr_filt = ca8210_set_hw_addr_filt,
2396 .set_txpower = ca8210_set_tx_power,
2397 .set_cca_mode = ca8210_set_cca_mode,
2398 .set_cca_ed_level = ca8210_set_cca_ed_level,
2399 .set_csma_params = ca8210_set_csma_params,
2400 .set_frame_retries = ca8210_set_frame_retries,
2401 .set_promiscuous_mode = ca8210_set_promiscuous_mode
2402};
2403
2404/* Test/EVBME Interface */
2405
2406/**
2407 * ca8210_test_int_open() - Opens the test interface to the userspace
2408 * @inodp: inode representation of file interface
2409 * @filp: file interface
2410 *
2411 * Return: 0 or linux error code
2412 */
2413static int ca8210_test_int_open(struct inode *inodp, struct file *filp)
2414{
2415 struct ca8210_priv *priv = inodp->i_private;
2416
2417 filp->private_data = priv;
2418 return 0;
2419}
2420
2421/**
2422 * ca8210_test_check_upstream() - Checks a command received from the upstream
2423 * testing interface for required action
2424 * @buf: Buffer containing command to check
2425 * @device_ref: Nondescript pointer to target device
2426 *
2427 * Return: 0 or linux error code
2428 */
2429static int ca8210_test_check_upstream(u8 *buf, void *device_ref)
2430{
2431 int ret;
2432 u8 response[CA8210_SPI_BUF_SIZE];
2433
2434 if (buf[0] == SPI_MLME_SET_REQUEST) {
2435 ret = tdme_checkpibattribute(buf[2], buf[4], buf + 5);
2436 if (ret) {
2437 response[0] = SPI_MLME_SET_CONFIRM;
2438 response[1] = 3;
2439 response[2] = MAC_INVALID_PARAMETER;
2440 response[3] = buf[2];
2441 response[4] = buf[3];
2442 if (cascoda_api_upstream)
2443 cascoda_api_upstream(response, 5, device_ref);
2444 return ret;
2445 }
2446 }
2447 if (buf[0] == SPI_MLME_ASSOCIATE_REQUEST) {
2448 return tdme_channelinit(buf[2], device_ref);
2449 } else if (buf[0] == SPI_MLME_START_REQUEST) {
2450 return tdme_channelinit(buf[4], device_ref);
2451 } else if (
2452 (buf[0] == SPI_MLME_SET_REQUEST) &&
2453 (buf[2] == PHY_CURRENT_CHANNEL)
2454 ) {
2455 return tdme_channelinit(buf[5], device_ref);
2456 } else if (
2457 (buf[0] == SPI_TDME_SET_REQUEST) &&
2458 (buf[2] == TDME_CHANNEL)
2459 ) {
2460 return tdme_channelinit(buf[4], device_ref);
2461 } else if (
2462 (CA8210_MAC_WORKAROUNDS) &&
2463 (buf[0] == SPI_MLME_RESET_REQUEST) &&
2464 (buf[2] == 1)
2465 ) {
2466 /* reset COORD Bit for Channel Filtering as Coordinator */
2467 return tdme_setsfr_request_sync(
2468 0,
2469 CA8210_SFR_MACCON,
2470 0,
2471 device_ref
2472 );
2473 }
2474 return 0;
2475} /* End of EVBMECheckSerialCommand() */
2476
2477/**
2478 * ca8210_test_int_user_write() - Called by a process in userspace to send a
2479 * message to the ca8210 drivers
2480 * @filp: file interface
2481 * @in_buf: Buffer containing message to write
2482 * @len: length of message
2483 * @off: file offset
2484 *
2485 * Return: 0 or linux error code
2486 */
2487static ssize_t ca8210_test_int_user_write(
2488 struct file *filp,
2489 const char __user *in_buf,
2490 size_t len,
2491 loff_t *off
2492)
2493{
2494 int ret;
2495 struct ca8210_priv *priv = filp->private_data;
2496 u8 command[CA8210_SPI_BUF_SIZE];
2497
2498 if (len > CA8210_SPI_BUF_SIZE) {
2499 dev_warn(
2500 &priv->spi->dev,
2501 "userspace requested erroneously long write (%zu)\n",
2502 len
2503 );
2504 return -EMSGSIZE;
2505 }
2506
2507 ret = copy_from_user(command, in_buf, len);
2508 if (ret) {
2509 dev_err(
2510 &priv->spi->dev,
2511 "%d bytes could not be copied from userspace\n",
2512 ret
2513 );
2514 return -EIO;
2515 }
2516
2517 ret = ca8210_test_check_upstream(command, priv->spi);
2518 if (ret == 0) {
2519 ret = ca8210_spi_exchange(
2520 command,
2521 command[1] + 2,
2522 NULL,
2523 priv->spi
2524 );
2525 if (ret < 0) {
2526 /* effectively 0 bytes were written successfully */
2527 dev_err(
2528 &priv->spi->dev,
2529 "spi exchange failed\n"
2530 );
2531 return ret;
2532 }
2533 if (command[0] & SPI_SYN)
2534 priv->sync_down++;
2535 }
2536
2537 return len;
2538}
2539
2540/**
2541 * ca8210_test_int_user_read() - Called by a process in userspace to read a
2542 * message from the ca8210 drivers
2543 * @filp: file interface
2544 * @buf: Buffer to write message to
2545 * @len: length of message to read (ignored)
2546 * @offp: file offset
2547 *
2548 * If the O_NONBLOCK flag was set when opening the file then this function will
2549 * not block, i.e. it will return if the fifo is empty. Otherwise the function
2550 * will block, i.e. wait until new data arrives.
2551 *
2552 * Return: number of bytes read
2553 */
2554static ssize_t ca8210_test_int_user_read(
2555 struct file *filp,
2556 char __user *buf,
2557 size_t len,
2558 loff_t *offp
2559)
2560{
2561 int i, cmdlen;
2562 struct ca8210_priv *priv = filp->private_data;
2563 unsigned char *fifo_buffer;
2564 unsigned long bytes_not_copied;
2565
2566 if (filp->f_flags & O_NONBLOCK) {
2567 /* Non-blocking mode */
2568 if (kfifo_is_empty(&priv->test.up_fifo))
2569 return 0;
2570 } else {
2571 /* Blocking mode */
2572 wait_event_interruptible(
2573 priv->test.readq,
2574 !kfifo_is_empty(&priv->test.up_fifo)
2575 );
2576 }
2577
2578 if (kfifo_out(&priv->test.up_fifo, &fifo_buffer, 4) != 4) {
2579 dev_err(
2580 &priv->spi->dev,
2581 "test_interface: Wrong number of elements popped from upstream fifo\n"
2582 );
2583 return 0;
2584 }
2585 cmdlen = fifo_buffer[1];
2586 bytes_not_copied = cmdlen + 2;
2587
2588 bytes_not_copied = copy_to_user(buf, fifo_buffer, bytes_not_copied);
2589 if (bytes_not_copied > 0) {
2590 dev_err(
2591 &priv->spi->dev,
2592 "%lu bytes could not be copied to user space!\n",
2593 bytes_not_copied
2594 );
2595 }
2596
2597 dev_dbg(&priv->spi->dev, "test_interface: Cmd len = %d\n", cmdlen);
2598
2599 dev_dbg(&priv->spi->dev, "test_interface: Read\n");
2600 for (i = 0; i < cmdlen + 2; i++)
2601 dev_dbg(&priv->spi->dev, "%#03x\n", fifo_buffer[i]);
2602
2603 kfree(fifo_buffer);
2604
2605 return cmdlen + 2;
2606}
2607
2608/**
2609 * ca8210_test_int_ioctl() - Called by a process in userspace to enact an
2610 * arbitrary action
2611 * @filp: file interface
2612 * @ioctl_num: which action to enact
2613 * @ioctl_param: arbitrary parameter for the action
2614 *
2615 * Return: status
2616 */
2617static long ca8210_test_int_ioctl(
2618 struct file *filp,
2619 unsigned int ioctl_num,
2620 unsigned long ioctl_param
2621)
2622{
2623 struct ca8210_priv *priv = filp->private_data;
2624
2625 switch (ioctl_num) {
2626 case CA8210_IOCTL_HARD_RESET:
2627 ca8210_reset_send(priv->spi, ioctl_param);
2628 break;
2629 default:
2630 break;
2631 }
2632 return 0;
2633}
2634
2635/**
2636 * ca8210_test_int_poll() - Called by a process in userspace to determine which
2637 * actions are currently possible for the file
2638 * @filp: file interface
2639 * @ptable: poll table
2640 *
2641 * Return: set of poll return flags
2642 */
2643static unsigned int ca8210_test_int_poll(
2644 struct file *filp,
2645 struct poll_table_struct *ptable
2646)
2647{
2648 unsigned int return_flags = 0;
2649 struct ca8210_priv *priv = filp->private_data;
2650
2651 poll_wait(filp, &priv->test.readq, ptable);
2652 if (!kfifo_is_empty(&priv->test.up_fifo))
2653 return_flags |= (POLLIN | POLLRDNORM);
2654 if (wait_event_interruptible(
2655 priv->test.readq,
2656 !kfifo_is_empty(&priv->test.up_fifo))) {
2657 return POLLERR;
2658 }
2659 return return_flags;
2660}
2661
2662static const struct file_operations test_int_fops = {
2663 .read = ca8210_test_int_user_read,
2664 .write = ca8210_test_int_user_write,
2665 .open = ca8210_test_int_open,
2666 .release = NULL,
2667 .unlocked_ioctl = ca8210_test_int_ioctl,
2668 .poll = ca8210_test_int_poll
2669};
2670
2671/* Init/Deinit */
2672
2673/**
2674 * ca8210_get_platform_data() - Populate a ca8210_platform_data object
2675 * @spi_device: Pointer to ca8210 spi device object to get data for
2676 * @pdata: Pointer to ca8210_platform_data object to populate
2677 *
2678 * Return: 0 or linux error code
2679 */
2680static int ca8210_get_platform_data(
2681 struct spi_device *spi_device,
2682 struct ca8210_platform_data *pdata
2683)
2684{
2685 int ret = 0;
2686
2687 if (!spi_device->dev.of_node)
2688 return -EINVAL;
2689
2690 pdata->extclockenable = of_property_read_bool(
2691 spi_device->dev.of_node,
2692 "extclock-enable"
2693 );
2694 if (pdata->extclockenable) {
2695 ret = of_property_read_u32(
2696 spi_device->dev.of_node,
2697 "extclock-freq",
2698 &pdata->extclockfreq
2699 );
2700 if (ret < 0)
2701 return ret;
2702
2703 ret = of_property_read_u32(
2704 spi_device->dev.of_node,
2705 "extclock-gpio",
2706 &pdata->extclockgpio
2707 );
2708 }
2709
2710 return ret;
2711}
2712
2713/**
2714 * ca8210_config_extern_clk() - Configure the external clock provided by the
2715 * ca8210
2716 * @pdata: Pointer to ca8210_platform_data containing clock parameters
2717 * @spi: Pointer to target ca8210 spi device
2718 * @on: True to turn the clock on, false to turn off
2719 *
2720 * The external clock is configured with a frequency and output pin taken from
2721 * the platform data.
2722 *
2723 * Return: 0 or linux error code
2724 */
2725static int ca8210_config_extern_clk(
2726 struct ca8210_platform_data *pdata,
2727 struct spi_device *spi,
2728 bool on
2729)
2730{
2731 u8 clkparam[2];
2732
2733 if (on) {
2734 dev_info(&spi->dev, "Switching external clock on\n");
2735 switch (pdata->extclockfreq) {
2736 case SIXTEEN_MHZ:
2737 clkparam[0] = 1;
2738 break;
2739 case EIGHT_MHZ:
2740 clkparam[0] = 2;
2741 break;
2742 case FOUR_MHZ:
2743 clkparam[0] = 3;
2744 break;
2745 case TWO_MHZ:
2746 clkparam[0] = 4;
2747 break;
2748 case ONE_MHZ:
2749 clkparam[0] = 5;
2750 break;
2751 default:
2752 dev_crit(&spi->dev, "Invalid extclock-freq\n");
2753 return -EINVAL;
2754 }
2755 clkparam[1] = pdata->extclockgpio;
2756 } else {
2757 dev_info(&spi->dev, "Switching external clock off\n");
2758 clkparam[0] = 0; /* off */
2759 clkparam[1] = 0;
2760 }
2761 return link_to_linux_err(
2762 hwme_set_request_sync(HWME_SYSCLKOUT, 2, clkparam, spi)
2763 );
2764}
2765
2766/**
2767 * ca8210_register_ext_clock() - Register ca8210's external clock with kernel
2768 * @spi: Pointer to target ca8210 spi device
2769 *
2770 * Return: 0 or linux error code
2771 */
2772static int ca8210_register_ext_clock(struct spi_device *spi)
2773{
2774 struct device_node *np = spi->dev.of_node;
2775 struct ca8210_priv *priv = spi_get_drvdata(spi);
2776 struct ca8210_platform_data *pdata = spi->dev.platform_data;
2777 int ret = 0;
2778
2779 if (!np)
2780 return -EFAULT;
2781
2782 priv->clk = clk_register_fixed_rate(
2783 &spi->dev,
2784 np->name,
2785 NULL,
2786 0,
2787 pdata->extclockfreq
2788 );
2789
2790 if (IS_ERR(priv->clk)) {
2791 dev_crit(&spi->dev, "Failed to register external clk\n");
2792 return PTR_ERR(priv->clk);
2793 }
2794 ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
2795 if (ret) {
2796 clk_unregister(priv->clk);
2797 dev_crit(
2798 &spi->dev,
2799 "Failed to register external clock as clock provider\n"
2800 );
2801 } else {
2802 dev_info(&spi->dev, "External clock set as clock provider\n");
2803 }
2804
2805 return ret;
2806}
2807
2808/**
2809 * ca8210_unregister_ext_clock() - Unregister ca8210's external clock with
2810 * kernel
2811 * @spi: Pointer to target ca8210 spi device
2812 */
2813static void ca8210_unregister_ext_clock(struct spi_device *spi)
2814{
2815 struct ca8210_priv *priv = spi_get_drvdata(spi);
2816
2817 if (!priv->clk)
2818 return
2819
2820 of_clk_del_provider(spi->dev.of_node);
2821 clk_unregister(priv->clk);
2822 dev_info(&spi->dev, "External clock unregistered\n");
2823}
2824
2825/**
2826 * ca8210_reset_init() - Initialise the reset input to the ca8210
2827 * @spi: Pointer to target ca8210 spi device
2828 *
2829 * Return: 0 or linux error code
2830 */
2831static int ca8210_reset_init(struct spi_device *spi)
2832{
2833 int ret;
2834 struct ca8210_platform_data *pdata = spi->dev.platform_data;
2835
2836 pdata->gpio_reset = of_get_named_gpio(
2837 spi->dev.of_node,
2838 "reset-gpio",
2839 0
2840 );
2841
2842 ret = gpio_direction_output(pdata->gpio_reset, 1);
2843 if (ret < 0) {
2844 dev_crit(
2845 &spi->dev,
2846 "Reset GPIO %d did not set to output mode\n",
2847 pdata->gpio_reset
2848 );
2849 }
2850
2851 return ret;
2852}
2853
2854/**
2855 * ca8210_interrupt_init() - Initialise the irq output from the ca8210
2856 * @spi: Pointer to target ca8210 spi device
2857 *
2858 * Return: 0 or linux error code
2859 */
2860static int ca8210_interrupt_init(struct spi_device *spi)
2861{
2862 int ret;
2863 struct ca8210_platform_data *pdata = spi->dev.platform_data;
2864
2865 pdata->gpio_irq = of_get_named_gpio(
2866 spi->dev.of_node,
2867 "irq-gpio",
2868 0
2869 );
2870
2871 pdata->irq_id = gpio_to_irq(pdata->gpio_irq);
2872 if (pdata->irq_id < 0) {
2873 dev_crit(
2874 &spi->dev,
2875 "Could not get irq for gpio pin %d\n",
2876 pdata->gpio_irq
2877 );
2878 gpio_free(pdata->gpio_irq);
2879 return pdata->irq_id;
2880 }
2881
2882 ret = request_irq(
2883 pdata->irq_id,
2884 ca8210_interrupt_handler,
2885 IRQF_TRIGGER_FALLING,
2886 "ca8210-irq",
2887 spi_get_drvdata(spi)
2888 );
2889 if (ret) {
2890 dev_crit(&spi->dev, "request_irq %d failed\n", pdata->irq_id);
2891 gpio_unexport(pdata->gpio_irq);
2892 gpio_free(pdata->gpio_irq);
2893 }
2894
2895 return ret;
2896}
2897
2898/**
2899 * ca8210_dev_com_init() - Initialise the spi communication component
2900 * @priv: Pointer to private data structure
2901 *
2902 * Return: 0 or linux error code
2903 */
2904static int ca8210_dev_com_init(struct ca8210_priv *priv)
2905{
2906 priv->mlme_workqueue = alloc_ordered_workqueue(
2907 "MLME work queue",
2908 WQ_UNBOUND
2909 );
2910 if (!priv->mlme_workqueue) {
2911 dev_crit(&priv->spi->dev, "alloc of mlme_workqueue failed!\n");
2912 return -ENOMEM;
2913 }
2914
2915 priv->irq_workqueue = alloc_ordered_workqueue(
2916 "ca8210 irq worker",
2917 WQ_UNBOUND
2918 );
2919 if (!priv->irq_workqueue) {
2920 dev_crit(&priv->spi->dev, "alloc of irq_workqueue failed!\n");
2921 return -ENOMEM;
2922 }
2923
2924 return 0;
2925}
2926
2927/**
2928 * ca8210_dev_com_clear() - Deinitialise the spi communication component
2929 * @priv: Pointer to private data structure
2930 */
2931static void ca8210_dev_com_clear(struct ca8210_priv *priv)
2932{
2933 flush_workqueue(priv->mlme_workqueue);
2934 destroy_workqueue(priv->mlme_workqueue);
2935 flush_workqueue(priv->irq_workqueue);
2936 destroy_workqueue(priv->irq_workqueue);
2937}
2938
2939#define CA8210_MAX_TX_POWERS (9)
2940static const s32 ca8210_tx_powers[CA8210_MAX_TX_POWERS] = {
2941 800, 700, 600, 500, 400, 300, 200, 100, 0
2942};
2943
2944#define CA8210_MAX_ED_LEVELS (21)
2945static const s32 ca8210_ed_levels[CA8210_MAX_ED_LEVELS] = {
2946 -10300, -10250, -10200, -10150, -10100, -10050, -10000, -9950, -9900,
2947 -9850, -9800, -9750, -9700, -9650, -9600, -9550, -9500, -9450, -9400,
2948 -9350, -9300
2949};
2950
2951/**
2952 * ca8210_hw_setup() - Populate the ieee802154_hw phy attributes with the
2953 * ca8210's defaults
2954 * @ca8210_hw: Pointer to ieee802154_hw to populate
2955 */
2956static void ca8210_hw_setup(struct ieee802154_hw *ca8210_hw)
2957{
2958 /* Support channels 11-26 */
2959 ca8210_hw->phy->supported.channels[0] = CA8210_VALID_CHANNELS;
2960 ca8210_hw->phy->supported.tx_powers_size = CA8210_MAX_TX_POWERS;
2961 ca8210_hw->phy->supported.tx_powers = ca8210_tx_powers;
2962 ca8210_hw->phy->supported.cca_ed_levels_size = CA8210_MAX_ED_LEVELS;
2963 ca8210_hw->phy->supported.cca_ed_levels = ca8210_ed_levels;
2964 ca8210_hw->phy->current_channel = 18;
2965 ca8210_hw->phy->current_page = 0;
2966 ca8210_hw->phy->transmit_power = 800;
2967 ca8210_hw->phy->cca.mode = NL802154_CCA_ENERGY_CARRIER;
2968 ca8210_hw->phy->cca.opt = NL802154_CCA_OPT_ENERGY_CARRIER_AND;
2969 ca8210_hw->phy->cca_ed_level = -9800;
2970 ca8210_hw->phy->symbol_duration = 16;
2971 ca8210_hw->phy->lifs_period = 40;
2972 ca8210_hw->phy->sifs_period = 12;
2973 ca8210_hw->flags =
2974 IEEE802154_HW_AFILT |
2975 IEEE802154_HW_OMIT_CKSUM |
2976 IEEE802154_HW_FRAME_RETRIES |
2977 IEEE802154_HW_PROMISCUOUS |
2978 IEEE802154_HW_CSMA_PARAMS;
2979 ca8210_hw->phy->flags =
2980 WPAN_PHY_FLAG_TXPOWER |
2981 WPAN_PHY_FLAG_CCA_ED_LEVEL |
2982 WPAN_PHY_FLAG_CCA_MODE;
2983}
2984
2985/**
2986 * ca8210_test_interface_init() - Initialise the test file interface
2987 * @priv: Pointer to private data structure
2988 *
2989 * Provided as an alternative to the standard linux network interface, the test
2990 * interface exposes a file in the filesystem (ca8210_test) that allows
2991 * 802.15.4 SAP Commands and Cascoda EVBME commands to be sent directly to
2992 * the stack.
2993 *
2994 * Return: 0 or linux error code
2995 */
2996static int ca8210_test_interface_init(struct ca8210_priv *priv)
2997{
2998 struct ca8210_test *test = &priv->test;
2999 char node_name[32];
3000
3001 snprintf(
3002 node_name,
3003 sizeof(node_name),
3004 "ca8210@%d_%d",
3005 priv->spi->master->bus_num,
3006 priv->spi->chip_select
3007 );
3008
3009 test->ca8210_dfs_spi_int = debugfs_create_file(
3010 node_name,
3011 0600, /* S_IRUSR | S_IWUSR */
3012 NULL,
3013 priv,
3014 &test_int_fops
3015 );
3016 if (IS_ERR(test->ca8210_dfs_spi_int)) {
3017 dev_err(
3018 &priv->spi->dev,
3019 "Error %ld when creating debugfs node\n",
3020 PTR_ERR(test->ca8210_dfs_spi_int)
3021 );
3022 return PTR_ERR(test->ca8210_dfs_spi_int);
3023 }
3024 debugfs_create_symlink("ca8210", NULL, node_name);
3025 init_waitqueue_head(&test->readq);
3026 return kfifo_alloc(
3027 &test->up_fifo,
3028 CA8210_TEST_INT_FIFO_SIZE,
3029 GFP_KERNEL
3030 );
3031}
3032
3033/**
3034 * ca8210_test_interface_clear() - Deinitialise the test file interface
3035 * @priv: Pointer to private data structure
3036 */
3037static void ca8210_test_interface_clear(struct ca8210_priv *priv)
3038{
3039 struct ca8210_test *test = &priv->test;
3040
3041 if (!IS_ERR(test->ca8210_dfs_spi_int))
3042 debugfs_remove(test->ca8210_dfs_spi_int);
3043 kfifo_free(&test->up_fifo);
3044 dev_info(&priv->spi->dev, "Test interface removed\n");
3045}
3046
3047/**
3048 * ca8210_remove() - Shut down a ca8210 upon being disconnected
3049 * @priv: Pointer to private data structure
3050 *
3051 * Return: 0 or linux error code
3052 */
3053static int ca8210_remove(struct spi_device *spi_device)
3054{
3055 struct ca8210_priv *priv;
3056 struct ca8210_platform_data *pdata;
3057
3058 dev_info(&spi_device->dev, "Removing ca8210\n");
3059
3060 pdata = spi_device->dev.platform_data;
3061 if (pdata) {
3062 if (pdata->extclockenable) {
3063 ca8210_unregister_ext_clock(spi_device);
3064 ca8210_config_extern_clk(pdata, spi_device, 0);
3065 }
3066 free_irq(pdata->irq_id, spi_device->dev.driver_data);
3067 kfree(pdata);
3068 spi_device->dev.platform_data = NULL;
3069 }
3070 /* get spi_device private data */
3071 priv = spi_get_drvdata(spi_device);
3072 if (priv) {
3073 dev_info(
3074 &spi_device->dev,
3075 "sync_down = %d, sync_up = %d\n",
3076 priv->sync_down,
3077 priv->sync_up
3078 );
3079 ca8210_dev_com_clear(spi_device->dev.driver_data);
3080 if (priv->hw) {
3081 if (priv->hw_registered)
3082 ieee802154_unregister_hw(priv->hw);
3083 ieee802154_free_hw(priv->hw);
3084 priv->hw = NULL;
3085 dev_info(
3086 &spi_device->dev,
3087 "Unregistered & freed ieee802154_hw.\n"
3088 );
3089 }
3090 if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS))
3091 ca8210_test_interface_clear(priv);
3092 }
3093
3094 return 0;
3095}
3096
3097/**
3098 * ca8210_probe() - Set up a connected ca8210 upon being detected by the system
3099 * @priv: Pointer to private data structure
3100 *
3101 * Return: 0 or linux error code
3102 */
3103static int ca8210_probe(struct spi_device *spi_device)
3104{
3105 struct ca8210_priv *priv;
3106 struct ieee802154_hw *hw;
3107 struct ca8210_platform_data *pdata;
3108 int ret;
3109
3110 dev_info(&spi_device->dev, "Inserting ca8210\n");
3111
3112 /* allocate ieee802154_hw and private data */
3113 hw = ieee802154_alloc_hw(sizeof(struct ca8210_priv), &ca8210_phy_ops);
3114 if (!hw) {
3115 dev_crit(&spi_device->dev, "ieee802154_alloc_hw failed\n");
3116 ret = -ENOMEM;
3117 goto error;
3118 }
3119
3120 priv = hw->priv;
3121 priv->hw = hw;
3122 priv->spi = spi_device;
3123 hw->parent = &spi_device->dev;
3124 spin_lock_init(&priv->lock);
3125 priv->async_tx_pending = false;
3126 priv->hw_registered = false;
3127 priv->sync_up = 0;
3128 priv->sync_down = 0;
3129 priv->promiscuous = false;
3130 priv->retries = 0;
3131 init_completion(&priv->ca8210_is_awake);
3132 init_completion(&priv->spi_transfer_complete);
3133 init_completion(&priv->sync_exchange_complete);
3134 spi_set_drvdata(priv->spi, priv);
3135 if (IS_ENABLED(CONFIG_IEEE802154_CA8210_DEBUGFS)) {
3136 cascoda_api_upstream = ca8210_test_int_driver_write;
3137 ca8210_test_interface_init(priv);
3138 } else {
3139 cascoda_api_upstream = NULL;
3140 }
3141 ca8210_hw_setup(hw);
3142 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
3143
3144 pdata = kmalloc(sizeof(*pdata), GFP_KERNEL);
3145 if (!pdata) {
Harry Morrisded845a2017-03-28 13:08:58 +01003146 ret = -ENOMEM;
3147 goto error;
3148 }
3149
3150 ret = ca8210_get_platform_data(priv->spi, pdata);
3151 if (ret) {
3152 dev_crit(&spi_device->dev, "ca8210_get_platform_data failed\n");
3153 goto error;
3154 }
3155 priv->spi->dev.platform_data = pdata;
3156
3157 ret = ca8210_dev_com_init(priv);
3158 if (ret) {
3159 dev_crit(&spi_device->dev, "ca8210_dev_com_init failed\n");
3160 goto error;
3161 }
3162 ret = ca8210_reset_init(priv->spi);
3163 if (ret) {
3164 dev_crit(&spi_device->dev, "ca8210_reset_init failed\n");
3165 goto error;
3166 }
3167
3168 ret = ca8210_interrupt_init(priv->spi);
3169 if (ret) {
3170 dev_crit(&spi_device->dev, "ca8210_interrupt_init failed\n");
3171 goto error;
3172 }
3173
3174 msleep(100);
3175
3176 ca8210_reset_send(priv->spi, 1);
3177
3178 ret = tdme_chipinit(priv->spi);
3179 if (ret) {
3180 dev_crit(&spi_device->dev, "tdme_chipinit failed\n");
3181 goto error;
3182 }
3183
3184 if (pdata->extclockenable) {
3185 ret = ca8210_config_extern_clk(pdata, priv->spi, 1);
3186 if (ret) {
3187 dev_crit(
3188 &spi_device->dev,
3189 "ca8210_config_extern_clk failed\n"
3190 );
3191 goto error;
3192 }
3193 ret = ca8210_register_ext_clock(priv->spi);
3194 if (ret) {
3195 dev_crit(
3196 &spi_device->dev,
3197 "ca8210_register_ext_clock failed\n"
3198 );
3199 goto error;
3200 }
3201 }
3202
3203 ret = ieee802154_register_hw(hw);
3204 if (ret) {
3205 dev_crit(&spi_device->dev, "ieee802154_register_hw failed\n");
3206 goto error;
3207 }
3208 priv->hw_registered = true;
3209
3210 return 0;
3211error:
3212 msleep(100); /* wait for pending spi transfers to complete */
3213 ca8210_remove(spi_device);
3214 return link_to_linux_err(ret);
3215}
3216
3217static const struct of_device_id ca8210_of_ids[] = {
3218 {.compatible = "cascoda,ca8210", },
3219 {},
3220};
3221MODULE_DEVICE_TABLE(of, ca8210_of_ids);
3222
3223static struct spi_driver ca8210_spi_driver = {
3224 .driver = {
3225 .name = DRIVER_NAME,
3226 .owner = THIS_MODULE,
3227 .of_match_table = of_match_ptr(ca8210_of_ids),
3228 },
3229 .probe = ca8210_probe,
3230 .remove = ca8210_remove
3231};
3232
3233module_spi_driver(ca8210_spi_driver);
3234
3235MODULE_AUTHOR("Harry Morris <h.morris@cascoda.com>");
3236MODULE_DESCRIPTION("CA-8210 SoftMAC driver");
3237MODULE_LICENSE("Dual BSD/GPL");
3238MODULE_VERSION("1.0");