| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 1 | # |
| 2 | # Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
| 3 | # |
| 4 | # This program is free software; you can redistribute it and/or modify |
| 5 | # it under the terms of the GNU General Public License version 2 as |
| 6 | # published by the Free Software Foundation. |
| 7 | # |
| 8 | |
| Vineet Gupta | 93ad700 | 2013-01-22 16:51:50 +0530 | [diff] [blame] | 9 | menuconfig ARC_PLAT_FPGA_LEGACY |
| 10 | bool "\"Legacy\" ARC FPGA dev Boards" |
| 11 | select ISS_SMP_EXTN if SMP |
| 12 | help |
| 13 | Support for ARC development boards, provided by Synopsys. |
| 14 | These are based on FPGA or ISS. e.g. |
| 15 | - ARCAngel4 |
| 16 | - ML509 |
| 17 | - MetaWare ISS |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 18 | |
| Vineet Gupta | 93ad700 | 2013-01-22 16:51:50 +0530 | [diff] [blame] | 19 | if ARC_PLAT_FPGA_LEGACY |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 20 | |
| 21 | config ARC_BOARD_ANGEL4 |
| 22 | bool "ARC Angel4" |
| Vineet Gupta | 93ad700 | 2013-01-22 16:51:50 +0530 | [diff] [blame] | 23 | default y |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 24 | help |
| 25 | ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based) |
| 26 | |
| 27 | config ARC_BOARD_ML509 |
| 28 | bool "ML509" |
| 29 | help |
| 30 | ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based) |
| 31 | |
| Vineet Gupta | 41195d2 | 2013-01-18 15:12:23 +0530 | [diff] [blame] | 32 | config ISS_SMP_EXTN |
| 33 | bool "ARC SMP Extensions (ISS Models only)" |
| 34 | default n |
| 35 | depends on SMP |
| 36 | select ARC_HAS_COH_RTSC |
| 37 | help |
| 38 | SMP Extensions to ARC700, in a "simulation only" Model, supported in |
| 39 | ARC ISS (Instruction Set Simulator). |
| 40 | The SMP extensions include: |
| 41 | -IDU (Interrupt Distribution Unit) |
| 42 | -XTL (To enable CPU start/stop/set-PC for another CPU) |
| 43 | It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND) |
| 44 | |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 45 | config ARC_SERIAL_BAUD |
| 46 | int "UART Baud rate" |
| 47 | default "115200" |
| 48 | depends on SERIAL_ARC || SERIAL_ARC_CONSOLE |
| 49 | help |
| 50 | Baud rate for the ARC UART |
| 51 | |
| Vineet Gupta | 7fadc1e | 2013-01-18 15:12:24 +0530 | [diff] [blame] | 52 | menuconfig ARC_HAS_BVCI_LAT_UNIT |
| 53 | bool "BVCI Bus Latency Unit" |
| 54 | depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4 |
| 55 | help |
| 56 | IP to add artifical latency to BVCI Bus Based FPGA builds. |
| 57 | The default latency (even worst case) for FPGA is non-realistic |
| 58 | (~10 SDRAM, ~5 SSRAM). |
| 59 | |
| 60 | config BVCI_LAT_UNITS |
| 61 | hex "Latency Unit(s) Bitmap" |
| 62 | default "0x0" |
| 63 | depends on ARC_HAS_BVCI_LAT_UNIT |
| 64 | help |
| 65 | There are multiple Latency Units corresponding to the many |
| 66 | interfaces of the system bus arbiter (both CPU side as well as |
| 67 | the peripheral side). |
| 68 | To add latency to ALL memory transaction, choose Unit 0, otherwise |
| 69 | for finer grainer - interface wise latency, specify a bitmap (1 bit |
| 70 | per unit) of all units. e.g. 1,2,12 will be 0x1003 |
| 71 | |
| 72 | Unit 0 - System Arb and Mem Controller |
| 73 | Unit 1 - I$ and System Bus |
| 74 | Unit 2 - D$ and System Bus |
| 75 | .. |
| 76 | Unit 12 - IDE Disk controller and System Bus |
| 77 | |
| 78 | config BVCI_LAT_CYCLES |
| 79 | int "Latency Value in cycles" |
| 80 | range 0 63 |
| 81 | default "30" |
| 82 | depends on ARC_HAS_BVCI_LAT_UNIT |
| 83 | |
| Vineet Gupta | cfdbc2e | 2013-01-18 15:12:20 +0530 | [diff] [blame] | 84 | endif |