Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 2 | #include "tegra186.dtsi" |
| 3 | |
Thierry Reding | 02df3f0 | 2017-02-23 18:30:48 +0100 | [diff] [blame] | 4 | #include <dt-bindings/mfd/max77620.h> |
| 5 | |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 6 | / { |
| 7 | model = "NVIDIA Tegra186 P3310 Processor Module"; |
| 8 | compatible = "nvidia,p3310", "nvidia,tegra186"; |
| 9 | |
| 10 | aliases { |
Thierry Reding | 80fdf7b | 2017-02-23 18:30:49 +0100 | [diff] [blame] | 11 | sdhci0 = "/sdhci@3460000"; |
| 12 | sdhci1 = "/sdhci@3400000"; |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 13 | serial0 = &uarta; |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 14 | i2c0 = "/bpmp/i2c"; |
| 15 | i2c1 = "/i2c@3160000"; |
| 16 | i2c2 = "/i2c@c240000"; |
| 17 | i2c3 = "/i2c@3180000"; |
| 18 | i2c4 = "/i2c@3190000"; |
| 19 | i2c5 = "/i2c@31c0000"; |
| 20 | i2c6 = "/i2c@c250000"; |
| 21 | i2c7 = "/i2c@31e0000"; |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 22 | }; |
| 23 | |
| 24 | chosen { |
| 25 | bootargs = "earlycon console=ttyS0,115200n8"; |
| 26 | stdout-path = "serial0:115200n8"; |
| 27 | }; |
| 28 | |
| 29 | memory { |
| 30 | device_type = "memory"; |
| 31 | reg = <0x0 0x80000000 0x2 0x00000000>; |
| 32 | }; |
| 33 | |
Thierry Reding | 24975b8 | 2017-02-23 18:30:47 +0100 | [diff] [blame] | 34 | ethernet@2490000 { |
| 35 | status = "okay"; |
| 36 | |
| 37 | phy-reset-gpios = <&gpio TEGRA_MAIN_GPIO(M, 4) GPIO_ACTIVE_LOW>; |
| 38 | phy-handle = <&phy>; |
| 39 | phy-mode = "rgmii"; |
| 40 | |
| 41 | mdio { |
| 42 | #address-cells = <1>; |
| 43 | #size-cells = <0>; |
| 44 | |
| 45 | phy: phy@0 { |
| 46 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 47 | reg = <0x0>; |
| 48 | interrupt-parent = <&gpio>; |
Bhadram Varka | 9df50ba | 2018-05-02 20:44:40 +0530 | [diff] [blame] | 49 | interrupts = <TEGRA_MAIN_GPIO(M, 5) IRQ_TYPE_LEVEL_LOW>; |
Thierry Reding | 24975b8 | 2017-02-23 18:30:47 +0100 | [diff] [blame] | 50 | }; |
| 51 | }; |
| 52 | }; |
| 53 | |
Thierry Reding | 301f12d | 2017-03-28 15:15:44 +0200 | [diff] [blame] | 54 | memory-controller@2c00000 { |
| 55 | status = "okay"; |
| 56 | }; |
| 57 | |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 58 | serial@3100000 { |
| 59 | status = "okay"; |
| 60 | }; |
| 61 | |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 62 | i2c@3160000 { |
| 63 | status = "okay"; |
Thierry Reding | b64994d | 2017-02-23 18:30:50 +0100 | [diff] [blame] | 64 | |
| 65 | power-monitor@40 { |
| 66 | compatible = "ti,ina3221"; |
| 67 | reg = <0x40>; |
| 68 | }; |
| 69 | |
| 70 | power-monitor@41 { |
| 71 | compatible = "ti,ina3221"; |
| 72 | reg = <0x41>; |
| 73 | }; |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | i2c@3180000 { |
| 77 | status = "okay"; |
| 78 | }; |
| 79 | |
Thierry Reding | 5bb88b7a | 2017-03-28 15:16:52 +0200 | [diff] [blame] | 80 | ddc: i2c@3190000 { |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 81 | status = "okay"; |
| 82 | }; |
| 83 | |
| 84 | i2c@31c0000 { |
| 85 | status = "okay"; |
| 86 | }; |
| 87 | |
| 88 | i2c@31e0000 { |
| 89 | status = "okay"; |
| 90 | }; |
| 91 | |
Thierry Reding | 80fdf7b | 2017-02-23 18:30:49 +0100 | [diff] [blame] | 92 | /* SDMMC1 (SD/MMC) */ |
| 93 | sdhci@3400000 { |
| 94 | cd-gpios = <&gpio TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; |
Thierry Reding | 102ca26 | 2017-11-01 15:26:00 +0100 | [diff] [blame] | 95 | wp-gpios = <&gpio TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; |
Thierry Reding | 80fdf7b | 2017-02-23 18:30:49 +0100 | [diff] [blame] | 96 | |
| 97 | vqmmc-supply = <&vddio_sdmmc1>; |
| 98 | }; |
| 99 | |
| 100 | /* SDMMC3 (SDIO) */ |
| 101 | sdhci@3440000 { |
| 102 | status = "okay"; |
| 103 | }; |
| 104 | |
| 105 | /* SDMMC4 (eMMC) */ |
| 106 | sdhci@3460000 { |
| 107 | status = "okay"; |
| 108 | bus-width = <8>; |
| 109 | non-removable; |
| 110 | |
| 111 | vqmmc-supply = <&vdd_1v8_ap>; |
| 112 | vmmc-supply = <&vdd_3v3_sys>; |
| 113 | }; |
| 114 | |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 115 | hsp@3c00000 { |
| 116 | status = "okay"; |
| 117 | }; |
| 118 | |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 119 | i2c@c240000 { |
| 120 | status = "okay"; |
| 121 | }; |
| 122 | |
| 123 | i2c@c250000 { |
| 124 | status = "okay"; |
| 125 | }; |
| 126 | |
Thierry Reding | 93dbb44 | 2017-02-23 18:30:45 +0100 | [diff] [blame] | 127 | pmc@c360000 { |
| 128 | nvidia,invert-interrupt; |
| 129 | }; |
| 130 | |
Thierry Reding | 0dfde13 | 2016-11-17 17:36:56 +0100 | [diff] [blame] | 131 | cpus { |
| 132 | cpu@0 { |
| 133 | enable-method = "psci"; |
| 134 | }; |
| 135 | |
| 136 | cpu@1 { |
| 137 | enable-method = "psci"; |
| 138 | }; |
| 139 | |
| 140 | cpu@2 { |
| 141 | enable-method = "psci"; |
| 142 | }; |
| 143 | |
| 144 | cpu@3 { |
| 145 | enable-method = "psci"; |
| 146 | }; |
| 147 | |
| 148 | cpu@4 { |
| 149 | enable-method = "psci"; |
| 150 | }; |
| 151 | |
| 152 | cpu@5 { |
| 153 | enable-method = "psci"; |
| 154 | }; |
| 155 | }; |
| 156 | |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 157 | bpmp { |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 158 | i2c { |
| 159 | status = "okay"; |
Thierry Reding | 02df3f0 | 2017-02-23 18:30:48 +0100 | [diff] [blame] | 160 | |
| 161 | pmic: pmic@3c { |
| 162 | compatible = "maxim,max77620"; |
| 163 | reg = <0x3c>; |
| 164 | |
| 165 | interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
| 166 | #interrupt-cells = <2>; |
| 167 | interrupt-controller; |
| 168 | |
| 169 | #gpio-cells = <2>; |
| 170 | gpio-controller; |
| 171 | |
| 172 | pinctrl-names = "default"; |
| 173 | pinctrl-0 = <&max77620_default>; |
| 174 | |
| 175 | max77620_default: pinmux { |
| 176 | gpio0 { |
| 177 | pins = "gpio0"; |
| 178 | function = "gpio"; |
| 179 | }; |
| 180 | |
| 181 | gpio1 { |
| 182 | pins = "gpio1"; |
| 183 | function = "fps-out"; |
| 184 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
| 185 | }; |
| 186 | |
| 187 | gpio2 { |
| 188 | pins = "gpio2"; |
| 189 | function = "fps-out"; |
| 190 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 191 | }; |
| 192 | |
| 193 | gpio3 { |
| 194 | pins = "gpio3"; |
| 195 | function = "fps-out"; |
| 196 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; |
| 197 | }; |
| 198 | |
| 199 | gpio4 { |
| 200 | pins = "gpio4"; |
| 201 | function = "32k-out1"; |
| 202 | drive-push-pull = <1>; |
| 203 | }; |
| 204 | |
| 205 | gpio5 { |
| 206 | pins = "gpio5"; |
| 207 | function = "gpio"; |
| 208 | drive-push-pull = <0>; |
| 209 | }; |
| 210 | |
| 211 | gpio6 { |
| 212 | pins = "gpio6"; |
| 213 | function = "gpio"; |
| 214 | drive-push-pull = <1>; |
| 215 | }; |
| 216 | |
| 217 | gpio7 { |
| 218 | pins = "gpio7"; |
| 219 | function = "gpio"; |
| 220 | drive-push-pull = <0>; |
| 221 | }; |
| 222 | }; |
| 223 | |
| 224 | fps { |
| 225 | fps0 { |
| 226 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| 227 | maxim,shutdown-fps-time-period-us = <640>; |
| 228 | }; |
| 229 | |
| 230 | fps1 { |
| 231 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; |
| 232 | maxim,shutdown-fps-time-period-us = <640>; |
| 233 | }; |
| 234 | |
| 235 | fps2 { |
| 236 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; |
| 237 | maxim,shutdown-fps-time-period-us = <640>; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | regulators { |
| 242 | in-sd0-supply = <&vdd_5v0_sys>; |
| 243 | in-sd1-supply = <&vdd_5v0_sys>; |
| 244 | in-sd2-supply = <&vdd_5v0_sys>; |
| 245 | in-sd3-supply = <&vdd_5v0_sys>; |
| 246 | |
| 247 | in-ldo0-1-supply = <&vdd_5v0_sys>; |
| 248 | in-ldo2-supply = <&vdd_5v0_sys>; |
| 249 | in-ldo3-5-supply = <&vdd_5v0_sys>; |
| 250 | in-ldo4-6-supply = <&vdd_1v8>; |
| 251 | in-ldo7-8-supply = <&avdd_dsi_csi>; |
| 252 | |
| 253 | sd0 { |
| 254 | regulator-name = "VDD_DDR_1V1_PMIC"; |
| 255 | regulator-min-microvolt = <1100000>; |
| 256 | regulator-max-microvolt = <1100000>; |
| 257 | regulator-always-on; |
| 258 | regulator-boot-on; |
| 259 | }; |
| 260 | |
| 261 | avdd_dsi_csi: sd1 { |
| 262 | regulator-name = "AVDD_DSI_CSI_1V2"; |
| 263 | regulator-min-microvolt = <1200000>; |
| 264 | regulator-max-microvolt = <1200000>; |
| 265 | /* XXX */ |
| 266 | regulator-always-on; |
| 267 | regulator-boot-on; |
| 268 | }; |
| 269 | |
| 270 | vdd_1v8: sd2 { |
| 271 | regulator-name = "VDD_1V8"; |
| 272 | regulator-min-microvolt = <1800000>; |
| 273 | regulator-max-microvolt = <1800000>; |
| 274 | /* XXX */ |
| 275 | regulator-always-on; |
| 276 | regulator-boot-on; |
| 277 | }; |
| 278 | |
| 279 | vdd_3v3_sys: sd3 { |
| 280 | regulator-name = "VDD_3V3_SYS"; |
| 281 | regulator-min-microvolt = <3300000>; |
| 282 | regulator-max-microvolt = <3300000>; |
| 283 | /* XXX */ |
| 284 | regulator-always-on; |
| 285 | regulator-boot-on; |
| 286 | }; |
| 287 | |
| 288 | ldo0 { |
| 289 | regulator-name = "VDD_1V8_AP_PLL"; |
| 290 | regulator-min-microvolt = <1800000>; |
| 291 | regulator-max-microvolt = <1800000>; |
| 292 | /* XXX */ |
| 293 | regulator-always-on; |
| 294 | regulator-boot-on; |
| 295 | }; |
| 296 | |
| 297 | ldo2 { |
| 298 | regulator-name = "VDDIO_3V3_AOHV"; |
| 299 | regulator-min-microvolt = <3300000>; |
| 300 | regulator-max-microvolt = <3300000>; |
| 301 | /* XXX */ |
| 302 | regulator-always-on; |
| 303 | regulator-boot-on; |
| 304 | }; |
| 305 | |
| 306 | vddio_sdmmc1: ldo3 { |
| 307 | regulator-name = "VDDIO_SDMMC1_AP"; |
| 308 | regulator-min-microvolt = <1800000>; |
| 309 | regulator-max-microvolt = <3300000>; |
| 310 | }; |
| 311 | |
| 312 | ldo4 { |
| 313 | regulator-name = "VDD_RTC"; |
| 314 | regulator-min-microvolt = <1000000>; |
| 315 | regulator-max-microvolt = <1000000>; |
| 316 | }; |
| 317 | |
| 318 | vddio_sdmmc3: ldo5 { |
| 319 | regulator-name = "VDDIO_SDMMC3_AP"; |
| 320 | regulator-min-microvolt = <2800000>; |
| 321 | regulator-max-microvolt = <2800000>; |
| 322 | }; |
| 323 | |
Thierry Reding | 3632850 | 2017-03-28 15:18:11 +0200 | [diff] [blame] | 324 | vdd_hdmi_1v05: ldo7 { |
Thierry Reding | 02df3f0 | 2017-02-23 18:30:48 +0100 | [diff] [blame] | 325 | regulator-name = "VDD_HDMI_1V05"; |
| 326 | regulator-min-microvolt = <1050000>; |
| 327 | regulator-max-microvolt = <1050000>; |
| 328 | /* XXX */ |
| 329 | regulator-always-on; |
| 330 | regulator-boot-on; |
| 331 | }; |
| 332 | |
| 333 | vdd_pex: ldo8 { |
| 334 | regulator-name = "VDD_PEX_1V05"; |
| 335 | regulator-min-microvolt = <1050000>; |
| 336 | regulator-max-microvolt = <1050000>; |
| 337 | /* XXX */ |
| 338 | regulator-always-on; |
| 339 | regulator-boot-on; |
| 340 | }; |
| 341 | }; |
| 342 | }; |
Thierry Reding | a4c7aab | 2017-02-23 18:30:46 +0100 | [diff] [blame] | 343 | }; |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 344 | }; |
Thierry Reding | 0dfde13 | 2016-11-17 17:36:56 +0100 | [diff] [blame] | 345 | |
| 346 | psci { |
| 347 | compatible = "arm,psci-1.0"; |
| 348 | status = "okay"; |
| 349 | method = "smc"; |
| 350 | }; |
Thierry Reding | 02df3f0 | 2017-02-23 18:30:48 +0100 | [diff] [blame] | 351 | |
| 352 | regulators { |
| 353 | compatible = "simple-bus"; |
| 354 | #address-cells = <1>; |
| 355 | #size-cells = <0>; |
| 356 | |
| 357 | vdd_5v0_sys: regulator@0 { |
| 358 | compatible = "regulator-fixed"; |
| 359 | reg = <0>; |
| 360 | |
| 361 | regulator-name = "VDD_5V0_SYS"; |
| 362 | regulator-min-microvolt = <5000000>; |
| 363 | regulator-max-microvolt = <5000000>; |
| 364 | regulator-always-on; |
| 365 | regulator-boot-on; |
| 366 | }; |
| 367 | |
| 368 | vdd_1v8_ap: regulator@1 { |
| 369 | compatible = "regulator-fixed"; |
| 370 | reg = <1>; |
| 371 | |
| 372 | regulator-name = "VDD_1V8_AP"; |
| 373 | regulator-min-microvolt = <1800000>; |
| 374 | regulator-max-microvolt = <1800000>; |
| 375 | |
| 376 | /* XXX */ |
| 377 | regulator-always-on; |
| 378 | regulator-boot-on; |
| 379 | |
| 380 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 381 | enable-active-high; |
| 382 | |
| 383 | vin-supply = <&vdd_1v8>; |
| 384 | }; |
| 385 | }; |
Joseph Lo | df205de | 2016-07-05 17:04:30 +0800 | [diff] [blame] | 386 | }; |