Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "dra72x.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "TI DRA722"; |
| 14 | compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; |
| 15 | |
| 16 | memory { |
| 17 | device_type = "memory"; |
| 18 | reg = <0x80000000 0x40000000>; /* 1024 MB */ |
| 19 | }; |
Nishanth Menon | 5b434d7 | 2014-10-21 09:35:56 -0500 | [diff] [blame^] | 20 | |
| 21 | evm_3v3: fixedregulator-evm_3v3 { |
| 22 | compatible = "regulator-fixed"; |
| 23 | regulator-name = "evm_3v3"; |
| 24 | regulator-min-microvolt = <3300000>; |
| 25 | regulator-max-microvolt = <3300000>; |
| 26 | }; |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 27 | }; |
| 28 | |
Keerthy J | 7e9711a | 2014-07-28 11:48:53 +0530 | [diff] [blame] | 29 | &dra7_pmx_core { |
| 30 | i2c1_pins: pinmux_i2c1_pins { |
| 31 | pinctrl-single,pins = < |
| 32 | 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ |
| 33 | 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ |
| 34 | >; |
| 35 | }; |
Roger Quadros | 09d4993 | 2014-10-21 13:41:17 +0300 | [diff] [blame] | 36 | |
| 37 | nand_default: nand_default { |
| 38 | pinctrl-single,pins = < |
| 39 | 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ |
| 40 | 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ |
| 41 | 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ |
| 42 | 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ |
| 43 | 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ |
| 44 | 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ |
| 45 | 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ |
| 46 | 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ |
| 47 | 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ |
| 48 | 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ |
| 49 | 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ |
| 50 | 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ |
| 51 | 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ |
| 52 | 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ |
| 53 | 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ |
| 54 | 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ |
| 55 | 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ |
| 56 | 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ |
| 57 | 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ |
| 58 | 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ |
| 59 | 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ |
| 60 | 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ |
| 61 | >; |
| 62 | }; |
George Cherian | 95cc6af | 2014-10-21 13:41:19 +0300 | [diff] [blame] | 63 | |
| 64 | usb1_pins: pinmux_usb1_pins { |
| 65 | pinctrl-single,pins = < |
| 66 | 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ |
| 67 | >; |
| 68 | }; |
| 69 | |
| 70 | usb2_pins: pinmux_usb2_pins { |
| 71 | pinctrl-single,pins = < |
| 72 | 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ |
| 73 | >; |
| 74 | }; |
Nishanth Menon | 829acd0 | 2014-10-21 09:30:46 -0500 | [diff] [blame] | 75 | |
| 76 | tps65917_pins_default: tps65917_pins_default { |
| 77 | pinctrl-single,pins = < |
| 78 | 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ |
| 79 | >; |
| 80 | }; |
Nishanth Menon | 5b434d7 | 2014-10-21 09:35:56 -0500 | [diff] [blame^] | 81 | |
| 82 | mmc1_pins_default: mmc1_pins_default { |
| 83 | pinctrl-single,pins = < |
| 84 | 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ |
| 85 | 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ |
| 86 | 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ |
| 87 | 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ |
| 88 | 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ |
| 89 | 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ |
| 90 | 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ |
| 91 | >; |
| 92 | }; |
| 93 | |
| 94 | mmc2_pins_default: mmc2_pins_default { |
| 95 | pinctrl-single,pins = < |
| 96 | 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ |
| 97 | 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ |
| 98 | 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ |
| 99 | 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ |
| 100 | 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ |
| 101 | 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ |
| 102 | 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ |
| 103 | 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ |
| 104 | 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ |
| 105 | 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ |
| 106 | >; |
| 107 | }; |
Keerthy J | 7e9711a | 2014-07-28 11:48:53 +0530 | [diff] [blame] | 108 | }; |
| 109 | |
| 110 | &i2c1 { |
| 111 | status = "okay"; |
| 112 | pinctrl-names = "default"; |
| 113 | pinctrl-0 = <&i2c1_pins>; |
| 114 | clock-frequency = <400000>; |
Keerthy J | b359c42 | 2014-07-28 11:48:54 +0530 | [diff] [blame] | 115 | |
| 116 | tps65917: tps65917@58 { |
| 117 | compatible = "ti,tps65917"; |
| 118 | reg = <0x58>; |
| 119 | |
Nishanth Menon | 829acd0 | 2014-10-21 09:30:46 -0500 | [diff] [blame] | 120 | pinctrl-names = "default"; |
| 121 | pinctrl-0 = <&tps65917_pins_default>; |
| 122 | |
Keerthy J | b359c42 | 2014-07-28 11:48:54 +0530 | [diff] [blame] | 123 | interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 124 | interrupt-parent = <&gic>; |
| 125 | interrupt-controller; |
| 126 | #interrupt-cells = <2>; |
| 127 | |
| 128 | ti,system-power-controller; |
| 129 | |
| 130 | tps65917_pmic { |
| 131 | compatible = "ti,tps65917-pmic"; |
| 132 | |
| 133 | regulators { |
| 134 | smps1_reg: smps1 { |
| 135 | /* VDD_MPU */ |
| 136 | regulator-name = "smps1"; |
| 137 | regulator-min-microvolt = <850000>; |
| 138 | regulator-max-microvolt = <1250000>; |
| 139 | regulator-always-on; |
| 140 | regulator-boot-on; |
| 141 | }; |
| 142 | |
| 143 | smps2_reg: smps2 { |
| 144 | /* VDD_CORE */ |
| 145 | regulator-name = "smps2"; |
| 146 | regulator-min-microvolt = <850000>; |
| 147 | regulator-max-microvolt = <1030000>; |
| 148 | regulator-boot-on; |
| 149 | regulator-always-on; |
| 150 | }; |
| 151 | |
| 152 | smps3_reg: smps3 { |
| 153 | /* VDD_GPU IVA DSPEVE */ |
| 154 | regulator-name = "smps3"; |
| 155 | regulator-min-microvolt = <850000>; |
| 156 | regulator-max-microvolt = <1250000>; |
| 157 | regulator-boot-on; |
| 158 | regulator-always-on; |
| 159 | }; |
| 160 | |
| 161 | smps4_reg: smps4 { |
| 162 | /* VDDS1V8 */ |
| 163 | regulator-name = "smps4"; |
| 164 | regulator-min-microvolt = <1800000>; |
| 165 | regulator-max-microvolt = <1800000>; |
| 166 | regulator-always-on; |
| 167 | regulator-boot-on; |
| 168 | }; |
| 169 | |
| 170 | smps5_reg: smps5 { |
| 171 | /* VDD_DDR */ |
| 172 | regulator-name = "smps5"; |
| 173 | regulator-min-microvolt = <1350000>; |
| 174 | regulator-max-microvolt = <1350000>; |
| 175 | regulator-boot-on; |
| 176 | regulator-always-on; |
| 177 | }; |
| 178 | |
| 179 | ldo1_reg: ldo1 { |
| 180 | /* LDO1_OUT --> SDIO */ |
| 181 | regulator-name = "ldo1"; |
| 182 | regulator-min-microvolt = <1800000>; |
| 183 | regulator-max-microvolt = <3300000>; |
| 184 | regulator-boot-on; |
| 185 | }; |
| 186 | |
| 187 | ldo2_reg: ldo2 { |
| 188 | /* LDO2_OUT --> TP1017 (UNUSED) */ |
| 189 | regulator-name = "ldo2"; |
| 190 | regulator-min-microvolt = <1800000>; |
| 191 | regulator-max-microvolt = <3300000>; |
| 192 | }; |
| 193 | |
| 194 | ldo3_reg: ldo3 { |
| 195 | /* VDDA_1V8_PHY */ |
| 196 | regulator-name = "ldo3"; |
| 197 | regulator-min-microvolt = <1800000>; |
| 198 | regulator-max-microvolt = <1800000>; |
| 199 | regulator-boot-on; |
| 200 | regulator-always-on; |
| 201 | }; |
| 202 | |
| 203 | ldo5_reg: ldo5 { |
| 204 | /* VDDA_1V8_PLL */ |
| 205 | regulator-name = "ldo5"; |
| 206 | regulator-min-microvolt = <1800000>; |
| 207 | regulator-max-microvolt = <1800000>; |
| 208 | regulator-always-on; |
| 209 | regulator-boot-on; |
| 210 | }; |
| 211 | |
| 212 | ldo4_reg: ldo4 { |
| 213 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
| 214 | regulator-name = "ldo4"; |
| 215 | regulator-min-microvolt = <3300000>; |
| 216 | regulator-max-microvolt = <3300000>; |
| 217 | regulator-boot-on; |
| 218 | }; |
| 219 | }; |
| 220 | }; |
Nishanth Menon | ab1d3c8 | 2014-10-21 09:30:47 -0500 | [diff] [blame] | 221 | |
| 222 | tps65917_power_button { |
| 223 | compatible = "ti,palmas-pwrbutton"; |
| 224 | interrupt-parent = <&tps65917>; |
| 225 | interrupts = <1 IRQ_TYPE_NONE>; |
| 226 | wakeup-source; |
| 227 | ti,palmas-long-press-seconds = <6>; |
| 228 | }; |
Keerthy J | b359c42 | 2014-07-28 11:48:54 +0530 | [diff] [blame] | 229 | }; |
Keerthy J | 7e9711a | 2014-07-28 11:48:53 +0530 | [diff] [blame] | 230 | }; |
| 231 | |
Rajendra Nayak | 38b248d | 2014-04-29 16:35:10 +0530 | [diff] [blame] | 232 | &uart1 { |
| 233 | status = "okay"; |
| 234 | }; |
Roger Quadros | 09d4993 | 2014-10-21 13:41:17 +0300 | [diff] [blame] | 235 | |
| 236 | &elm { |
| 237 | status = "okay"; |
| 238 | }; |
| 239 | |
| 240 | &gpmc { |
| 241 | status = "okay"; |
| 242 | pinctrl-names = "default"; |
| 243 | pinctrl-0 = <&nand_default>; |
| 244 | ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ |
| 245 | nand@0,0 { |
| 246 | /* To use NAND, DIP switch SW5 must be set like so: |
| 247 | * SW5.1 (NAND_SELn) = ON (LOW) |
| 248 | * SW5.9 (GPMC_WPN) = OFF (HIGH) |
| 249 | */ |
| 250 | reg = <0 0 4>; /* device IO registers */ |
| 251 | ti,nand-ecc-opt = "bch8"; |
| 252 | ti,elm-id = <&elm>; |
| 253 | nand-bus-width = <16>; |
| 254 | gpmc,device-width = <2>; |
| 255 | gpmc,sync-clk-ps = <0>; |
| 256 | gpmc,cs-on-ns = <0>; |
| 257 | gpmc,cs-rd-off-ns = <80>; |
| 258 | gpmc,cs-wr-off-ns = <80>; |
| 259 | gpmc,adv-on-ns = <0>; |
| 260 | gpmc,adv-rd-off-ns = <60>; |
| 261 | gpmc,adv-wr-off-ns = <60>; |
| 262 | gpmc,we-on-ns = <10>; |
| 263 | gpmc,we-off-ns = <50>; |
| 264 | gpmc,oe-on-ns = <4>; |
| 265 | gpmc,oe-off-ns = <40>; |
| 266 | gpmc,access-ns = <40>; |
| 267 | gpmc,wr-access-ns = <80>; |
| 268 | gpmc,rd-cycle-ns = <80>; |
| 269 | gpmc,wr-cycle-ns = <80>; |
| 270 | gpmc,bus-turnaround-ns = <0>; |
| 271 | gpmc,cycle2cycle-delay-ns = <0>; |
| 272 | gpmc,clk-activation-ns = <0>; |
| 273 | gpmc,wait-monitoring-ns = <0>; |
| 274 | gpmc,wr-data-mux-bus-ns = <0>; |
| 275 | /* MTD partition table */ |
| 276 | /* All SPL-* partitions are sized to minimal length |
| 277 | * which can be independently programmable. For |
| 278 | * NAND flash this is equal to size of erase-block */ |
| 279 | #address-cells = <1>; |
| 280 | #size-cells = <1>; |
| 281 | partition@0 { |
| 282 | label = "NAND.SPL"; |
| 283 | reg = <0x00000000 0x000020000>; |
| 284 | }; |
| 285 | partition@1 { |
| 286 | label = "NAND.SPL.backup1"; |
| 287 | reg = <0x00020000 0x00020000>; |
| 288 | }; |
| 289 | partition@2 { |
| 290 | label = "NAND.SPL.backup2"; |
| 291 | reg = <0x00040000 0x00020000>; |
| 292 | }; |
| 293 | partition@3 { |
| 294 | label = "NAND.SPL.backup3"; |
| 295 | reg = <0x00060000 0x00020000>; |
| 296 | }; |
| 297 | partition@4 { |
| 298 | label = "NAND.u-boot-spl-os"; |
| 299 | reg = <0x00080000 0x00040000>; |
| 300 | }; |
| 301 | partition@5 { |
| 302 | label = "NAND.u-boot"; |
| 303 | reg = <0x000c0000 0x00100000>; |
| 304 | }; |
| 305 | partition@6 { |
| 306 | label = "NAND.u-boot-env"; |
| 307 | reg = <0x001c0000 0x00020000>; |
| 308 | }; |
| 309 | partition@7 { |
| 310 | label = "NAND.u-boot-env.backup1"; |
| 311 | reg = <0x001e0000 0x00020000>; |
| 312 | }; |
| 313 | partition@8 { |
| 314 | label = "NAND.kernel"; |
| 315 | reg = <0x00200000 0x00800000>; |
| 316 | }; |
| 317 | partition@9 { |
| 318 | label = "NAND.file-system"; |
| 319 | reg = <0x00a00000 0x0f600000>; |
| 320 | }; |
| 321 | }; |
| 322 | }; |
George Cherian | 95cc6af | 2014-10-21 13:41:19 +0300 | [diff] [blame] | 323 | |
Roger Quadros | 7a15c8e | 2014-10-21 13:41:20 +0300 | [diff] [blame] | 324 | &usb2_phy1 { |
| 325 | phy-supply = <&ldo4_reg>; |
| 326 | }; |
| 327 | |
| 328 | &usb2_phy2 { |
| 329 | phy-supply = <&ldo4_reg>; |
| 330 | }; |
| 331 | |
George Cherian | 95cc6af | 2014-10-21 13:41:19 +0300 | [diff] [blame] | 332 | &usb1 { |
| 333 | dr_mode = "peripheral"; |
| 334 | pinctrl-names = "default"; |
| 335 | pinctrl-0 = <&usb1_pins>; |
| 336 | }; |
| 337 | |
| 338 | &usb2 { |
| 339 | dr_mode = "host"; |
| 340 | pinctrl-names = "default"; |
| 341 | pinctrl-0 = <&usb2_pins>; |
| 342 | }; |
Nishanth Menon | 5b434d7 | 2014-10-21 09:35:56 -0500 | [diff] [blame^] | 343 | |
| 344 | &mmc1 { |
| 345 | status = "okay"; |
| 346 | pinctrl-names = "default"; |
| 347 | pinctrl-0 = <&mmc1_pins_default>; |
| 348 | |
| 349 | vmmc-supply = <&ldo1_reg>; |
| 350 | bus-width = <4>; |
| 351 | /* |
| 352 | * SDCD signal is not being used here - using the fact that GPIO mode |
| 353 | * is a viable alternative |
| 354 | */ |
| 355 | cd-gpios = <&gpio6 27 0>; |
| 356 | }; |
| 357 | |
| 358 | &mmc2 { |
| 359 | /* SW5-3 in ON position */ |
| 360 | status = "okay"; |
| 361 | pinctrl-names = "default"; |
| 362 | pinctrl-0 = <&mmc2_pins_default>; |
| 363 | |
| 364 | vmmc-supply = <&evm_3v3>; |
| 365 | bus-width = <8>; |
| 366 | ti,non-removable; |
| 367 | }; |