Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Zhi Wang <zhi.a.wang@intel.com> |
| 25 | * Zhenyu Wang <zhenyuw@linux.intel.com> |
| 26 | * Xiao Zheng <xiao.zheng@intel.com> |
| 27 | * |
| 28 | * Contributors: |
| 29 | * Min He <min.he@intel.com> |
| 30 | * Bing Niu <bing.niu@intel.com> |
| 31 | * |
| 32 | */ |
| 33 | |
| 34 | #ifndef _GVT_GTT_H_ |
| 35 | #define _GVT_GTT_H_ |
| 36 | |
Zhi Wang | 9556e11 | 2017-10-10 13:51:32 +0800 | [diff] [blame] | 37 | #define I915_GTT_PAGE_SHIFT 12 |
| 38 | #define I915_GTT_PAGE_MASK (~(I915_GTT_PAGE_SIZE - 1)) |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 39 | |
| 40 | struct intel_vgpu_mm; |
| 41 | |
| 42 | #define INTEL_GVT_GTT_HASH_BITS 8 |
| 43 | #define INTEL_GVT_INVALID_ADDR (~0UL) |
| 44 | |
| 45 | struct intel_gvt_gtt_entry { |
| 46 | u64 val64; |
| 47 | int type; |
| 48 | }; |
| 49 | |
| 50 | struct intel_gvt_gtt_pte_ops { |
Changbin Du | 4b2dbbc | 2017-08-02 15:06:37 +0800 | [diff] [blame] | 51 | int (*get_entry)(void *pt, |
| 52 | struct intel_gvt_gtt_entry *e, |
| 53 | unsigned long index, |
| 54 | bool hypervisor_access, |
| 55 | unsigned long gpa, |
| 56 | struct intel_vgpu *vgpu); |
| 57 | int (*set_entry)(void *pt, |
| 58 | struct intel_gvt_gtt_entry *e, |
| 59 | unsigned long index, |
| 60 | bool hypervisor_access, |
| 61 | unsigned long gpa, |
| 62 | struct intel_vgpu *vgpu); |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 63 | bool (*test_present)(struct intel_gvt_gtt_entry *e); |
| 64 | void (*clear_present)(struct intel_gvt_gtt_entry *e); |
Zhi Wang | 655c64e | 2017-10-10 17:24:26 +0800 | [diff] [blame] | 65 | void (*set_present)(struct intel_gvt_gtt_entry *e); |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 66 | bool (*test_pse)(struct intel_gvt_gtt_entry *e); |
| 67 | void (*set_pfn)(struct intel_gvt_gtt_entry *e, unsigned long pfn); |
| 68 | unsigned long (*get_pfn)(struct intel_gvt_gtt_entry *e); |
| 69 | }; |
| 70 | |
| 71 | struct intel_gvt_gtt_gma_ops { |
| 72 | unsigned long (*gma_to_ggtt_pte_index)(unsigned long gma); |
| 73 | unsigned long (*gma_to_pte_index)(unsigned long gma); |
| 74 | unsigned long (*gma_to_pde_index)(unsigned long gma); |
| 75 | unsigned long (*gma_to_l3_pdp_index)(unsigned long gma); |
| 76 | unsigned long (*gma_to_l4_pdp_index)(unsigned long gma); |
| 77 | unsigned long (*gma_to_pml4_index)(unsigned long gma); |
| 78 | }; |
| 79 | |
| 80 | struct intel_gvt_gtt { |
| 81 | struct intel_gvt_gtt_pte_ops *pte_ops; |
| 82 | struct intel_gvt_gtt_gma_ops *gma_ops; |
| 83 | int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm); |
| 84 | void (*mm_free_page_table)(struct intel_vgpu_mm *mm); |
| 85 | struct list_head oos_page_use_list_head; |
| 86 | struct list_head oos_page_free_list_head; |
| 87 | struct list_head mm_lru_list_head; |
Ping Gao | d650ac0 | 2016-12-08 10:14:48 +0800 | [diff] [blame] | 88 | |
Zhi Wang | 22115ce | 2017-10-10 14:34:11 +0800 | [diff] [blame] | 89 | struct page *scratch_page; |
| 90 | unsigned long scratch_mfn; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | enum { |
| 94 | INTEL_GVT_MM_GGTT = 0, |
| 95 | INTEL_GVT_MM_PPGTT, |
| 96 | }; |
| 97 | |
Ping Gao | 3b6411c | 2016-11-04 13:47:35 +0800 | [diff] [blame] | 98 | typedef enum { |
| 99 | GTT_TYPE_INVALID = -1, |
| 100 | |
| 101 | GTT_TYPE_GGTT_PTE, |
| 102 | |
| 103 | GTT_TYPE_PPGTT_PTE_4K_ENTRY, |
| 104 | GTT_TYPE_PPGTT_PTE_2M_ENTRY, |
| 105 | GTT_TYPE_PPGTT_PTE_1G_ENTRY, |
| 106 | |
| 107 | GTT_TYPE_PPGTT_PTE_ENTRY, |
| 108 | |
| 109 | GTT_TYPE_PPGTT_PDE_ENTRY, |
| 110 | GTT_TYPE_PPGTT_PDP_ENTRY, |
| 111 | GTT_TYPE_PPGTT_PML4_ENTRY, |
| 112 | |
| 113 | GTT_TYPE_PPGTT_ROOT_ENTRY, |
| 114 | |
| 115 | GTT_TYPE_PPGTT_ROOT_L3_ENTRY, |
| 116 | GTT_TYPE_PPGTT_ROOT_L4_ENTRY, |
| 117 | |
| 118 | GTT_TYPE_PPGTT_ENTRY, |
| 119 | |
| 120 | GTT_TYPE_PPGTT_PTE_PT, |
| 121 | GTT_TYPE_PPGTT_PDE_PT, |
| 122 | GTT_TYPE_PPGTT_PDP_PT, |
| 123 | GTT_TYPE_PPGTT_PML4_PT, |
| 124 | |
| 125 | GTT_TYPE_MAX, |
| 126 | } intel_gvt_gtt_type_t; |
| 127 | |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 128 | struct intel_vgpu_mm { |
| 129 | int type; |
| 130 | bool initialized; |
| 131 | bool shadowed; |
| 132 | |
| 133 | int page_table_entry_type; |
| 134 | u32 page_table_entry_size; |
| 135 | u32 page_table_entry_cnt; |
| 136 | void *virtual_page_table; |
| 137 | void *shadow_page_table; |
| 138 | |
| 139 | int page_table_level; |
| 140 | bool has_shadow_page_table; |
| 141 | u32 pde_base_index; |
| 142 | |
| 143 | struct list_head list; |
| 144 | struct kref ref; |
| 145 | atomic_t pincount; |
| 146 | struct list_head lru_list; |
| 147 | struct intel_vgpu *vgpu; |
| 148 | }; |
| 149 | |
Changbin Du | 4b2dbbc | 2017-08-02 15:06:37 +0800 | [diff] [blame] | 150 | extern int intel_vgpu_mm_get_entry( |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 151 | struct intel_vgpu_mm *mm, |
| 152 | void *page_table, struct intel_gvt_gtt_entry *e, |
| 153 | unsigned long index); |
| 154 | |
Changbin Du | 4b2dbbc | 2017-08-02 15:06:37 +0800 | [diff] [blame] | 155 | extern int intel_vgpu_mm_set_entry( |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 156 | struct intel_vgpu_mm *mm, |
| 157 | void *page_table, struct intel_gvt_gtt_entry *e, |
| 158 | unsigned long index); |
| 159 | |
| 160 | #define ggtt_get_guest_entry(mm, e, index) \ |
| 161 | intel_vgpu_mm_get_entry(mm, mm->virtual_page_table, e, index) |
| 162 | |
| 163 | #define ggtt_set_guest_entry(mm, e, index) \ |
| 164 | intel_vgpu_mm_set_entry(mm, mm->virtual_page_table, e, index) |
| 165 | |
| 166 | #define ggtt_get_shadow_entry(mm, e, index) \ |
| 167 | intel_vgpu_mm_get_entry(mm, mm->shadow_page_table, e, index) |
| 168 | |
| 169 | #define ggtt_set_shadow_entry(mm, e, index) \ |
| 170 | intel_vgpu_mm_set_entry(mm, mm->shadow_page_table, e, index) |
| 171 | |
| 172 | #define ppgtt_get_guest_root_entry(mm, e, index) \ |
| 173 | intel_vgpu_mm_get_entry(mm, mm->virtual_page_table, e, index) |
| 174 | |
| 175 | #define ppgtt_set_guest_root_entry(mm, e, index) \ |
| 176 | intel_vgpu_mm_set_entry(mm, mm->virtual_page_table, e, index) |
| 177 | |
| 178 | #define ppgtt_get_shadow_root_entry(mm, e, index) \ |
| 179 | intel_vgpu_mm_get_entry(mm, mm->shadow_page_table, e, index) |
| 180 | |
| 181 | #define ppgtt_set_shadow_root_entry(mm, e, index) \ |
| 182 | intel_vgpu_mm_set_entry(mm, mm->shadow_page_table, e, index) |
| 183 | |
| 184 | extern struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu, |
| 185 | int mm_type, void *virtual_page_table, int page_table_level, |
| 186 | u32 pde_base_index); |
| 187 | extern void intel_vgpu_destroy_mm(struct kref *mm_ref); |
| 188 | |
| 189 | struct intel_vgpu_guest_page; |
| 190 | |
Zhenyu Wang | 5c35258 | 2017-11-02 17:44:52 +0800 | [diff] [blame^] | 191 | struct intel_vgpu_scratch_pt { |
Ping Gao | 3b6411c | 2016-11-04 13:47:35 +0800 | [diff] [blame] | 192 | struct page *page; |
Zhenyu Wang | 5c35258 | 2017-11-02 17:44:52 +0800 | [diff] [blame^] | 193 | unsigned long page_mfn; |
Ping Gao | 3b6411c | 2016-11-04 13:47:35 +0800 | [diff] [blame] | 194 | }; |
| 195 | |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 196 | struct intel_vgpu_gtt { |
| 197 | struct intel_vgpu_mm *ggtt_mm; |
| 198 | unsigned long active_ppgtt_mm_bitmap; |
| 199 | struct list_head mm_list_head; |
| 200 | DECLARE_HASHTABLE(shadow_page_hash_table, INTEL_GVT_GTT_HASH_BITS); |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 201 | DECLARE_HASHTABLE(tracked_guest_page_hash_table, INTEL_GVT_GTT_HASH_BITS); |
| 202 | atomic_t n_tracked_guest_page; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 203 | struct list_head oos_page_list_head; |
| 204 | struct list_head post_shadow_list_head; |
Zhenyu Wang | 5c35258 | 2017-11-02 17:44:52 +0800 | [diff] [blame^] | 205 | struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX]; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 206 | }; |
| 207 | |
| 208 | extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu); |
| 209 | extern void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu); |
Ping Gao | d650ac0 | 2016-12-08 10:14:48 +0800 | [diff] [blame] | 210 | void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu); |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 211 | |
| 212 | extern int intel_gvt_init_gtt(struct intel_gvt *gvt); |
Chuanxiao Dong | 4d3e67b | 2017-08-04 13:08:59 +0800 | [diff] [blame] | 213 | void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 214 | extern void intel_gvt_clean_gtt(struct intel_gvt *gvt); |
| 215 | |
| 216 | extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, |
| 217 | int page_table_level, void *root_entry); |
| 218 | |
| 219 | struct intel_vgpu_oos_page; |
| 220 | |
Zhenyu Wang | 5c35258 | 2017-11-02 17:44:52 +0800 | [diff] [blame^] | 221 | struct intel_vgpu_shadow_page { |
| 222 | void *vaddr; |
| 223 | struct page *page; |
| 224 | int type; |
| 225 | struct hlist_node node; |
| 226 | unsigned long mfn; |
| 227 | }; |
| 228 | |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 229 | struct intel_vgpu_page_track { |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 230 | struct hlist_node node; |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 231 | bool tracked; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 232 | unsigned long gfn; |
| 233 | int (*handler)(void *, u64, void *, int); |
| 234 | void *data; |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 235 | }; |
| 236 | |
| 237 | struct intel_vgpu_guest_page { |
| 238 | struct intel_vgpu_page_track track; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 239 | unsigned long write_cnt; |
| 240 | struct intel_vgpu_oos_page *oos_page; |
| 241 | }; |
| 242 | |
| 243 | struct intel_vgpu_oos_page { |
| 244 | struct intel_vgpu_guest_page *guest_page; |
| 245 | struct list_head list; |
| 246 | struct list_head vm_list; |
| 247 | int id; |
Zhi Wang | 9556e11 | 2017-10-10 13:51:32 +0800 | [diff] [blame] | 248 | unsigned char mem[I915_GTT_PAGE_SIZE]; |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 249 | }; |
| 250 | |
| 251 | #define GTT_ENTRY_NUM_IN_ONE_PAGE 512 |
| 252 | |
| 253 | struct intel_vgpu_ppgtt_spt { |
| 254 | struct intel_vgpu_shadow_page shadow_page; |
| 255 | struct intel_vgpu_guest_page guest_page; |
| 256 | int guest_page_type; |
| 257 | atomic_t refcount; |
| 258 | struct intel_vgpu *vgpu; |
| 259 | DECLARE_BITMAP(post_shadow_bitmap, GTT_ENTRY_NUM_IN_ONE_PAGE); |
| 260 | struct list_head post_shadow_list; |
| 261 | }; |
| 262 | |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 263 | int intel_vgpu_init_page_track(struct intel_vgpu *vgpu, |
| 264 | struct intel_vgpu_page_track *t, |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 265 | unsigned long gfn, |
| 266 | int (*handler)(void *gp, u64, void *, int), |
| 267 | void *data); |
| 268 | |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 269 | void intel_vgpu_clean_page_track(struct intel_vgpu *vgpu, |
| 270 | struct intel_vgpu_page_track *t); |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 271 | |
Zhi Wang | 7d1e5cd | 2017-09-29 02:47:55 +0800 | [diff] [blame] | 272 | struct intel_vgpu_page_track *intel_vgpu_find_tracked_page( |
Zhi Wang | 2707e44 | 2016-03-28 23:23:16 +0800 | [diff] [blame] | 273 | struct intel_vgpu *vgpu, unsigned long gfn); |
| 274 | |
| 275 | int intel_vgpu_sync_oos_pages(struct intel_vgpu *vgpu); |
| 276 | |
| 277 | int intel_vgpu_flush_post_shadow(struct intel_vgpu *vgpu); |
| 278 | |
| 279 | static inline void intel_gvt_mm_reference(struct intel_vgpu_mm *mm) |
| 280 | { |
| 281 | kref_get(&mm->ref); |
| 282 | } |
| 283 | |
| 284 | static inline void intel_gvt_mm_unreference(struct intel_vgpu_mm *mm) |
| 285 | { |
| 286 | kref_put(&mm->ref, intel_vgpu_destroy_mm); |
| 287 | } |
| 288 | |
| 289 | int intel_vgpu_pin_mm(struct intel_vgpu_mm *mm); |
| 290 | |
| 291 | void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm); |
| 292 | |
| 293 | unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, |
| 294 | unsigned long gma); |
| 295 | |
| 296 | struct intel_vgpu_mm *intel_vgpu_find_ppgtt_mm(struct intel_vgpu *vgpu, |
| 297 | int page_table_level, void *root_entry); |
| 298 | |
| 299 | int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu *vgpu, |
| 300 | int page_table_level); |
| 301 | |
| 302 | int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu, |
| 303 | int page_table_level); |
| 304 | |
| 305 | int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu *vgpu, |
| 306 | unsigned int off, void *p_data, unsigned int bytes); |
| 307 | |
| 308 | int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu *vgpu, |
| 309 | unsigned int off, void *p_data, unsigned int bytes); |
| 310 | |
| 311 | #endif /* _GVT_GTT_H_ */ |