Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | |
| 24 | #include <linux/firmware.h> |
| 25 | #include "drmP.h" |
| 26 | #include "amdgpu.h" |
Jammy Zhou | dbd29f0 | 2015-10-21 17:15:45 +0800 | [diff] [blame] | 27 | #include "tonga_smum.h" |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 28 | |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 29 | MODULE_FIRMWARE("amdgpu/tonga_smc.bin"); |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 30 | |
| 31 | static void tonga_dpm_set_funcs(struct amdgpu_device *adev); |
| 32 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 33 | static int tonga_dpm_early_init(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 34 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 35 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 36 | |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 37 | tonga_dpm_set_funcs(adev); |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | static int tonga_dpm_init_microcode(struct amdgpu_device *adev) |
| 43 | { |
Jammy Zhou | c65444f | 2015-05-13 22:49:04 +0800 | [diff] [blame] | 44 | char fw_name[30] = "amdgpu/tonga_smc.bin"; |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 45 | int err; |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 46 | err = request_firmware(&adev->pm.fw, fw_name, adev->dev); |
| 47 | if (err) |
| 48 | goto out; |
| 49 | err = amdgpu_ucode_validate(adev->pm.fw); |
| 50 | |
| 51 | out: |
| 52 | if (err) { |
| 53 | DRM_ERROR("Failed to load firmware \"%s\"", fw_name); |
| 54 | release_firmware(adev->pm.fw); |
| 55 | adev->pm.fw = NULL; |
| 56 | } |
| 57 | return err; |
| 58 | } |
| 59 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 60 | static int tonga_dpm_sw_init(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 61 | { |
| 62 | int ret; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 63 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 64 | |
| 65 | ret = tonga_dpm_init_microcode(adev); |
| 66 | if (ret) |
| 67 | return ret; |
| 68 | |
| 69 | return 0; |
| 70 | } |
| 71 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 72 | static int tonga_dpm_sw_fini(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 73 | { |
| 74 | return 0; |
| 75 | } |
| 76 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 77 | static int tonga_dpm_hw_init(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 78 | { |
| 79 | int ret; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 80 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 81 | |
| 82 | mutex_lock(&adev->pm.mutex); |
| 83 | |
Alex Deucher | aaf4ee3 | 2015-06-09 17:42:10 -0400 | [diff] [blame] | 84 | /* smu init only needs to be called at startup, not resume. |
| 85 | * It should be in sw_init, but requires the fw info gathered |
| 86 | * in sw_init from other IP modules. |
| 87 | */ |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 88 | ret = tonga_smu_init(adev); |
| 89 | if (ret) { |
| 90 | DRM_ERROR("SMU initialization failed\n"); |
| 91 | goto fail; |
| 92 | } |
| 93 | |
| 94 | ret = tonga_smu_start(adev); |
| 95 | if (ret) { |
| 96 | DRM_ERROR("SMU start failed\n"); |
| 97 | goto fail; |
| 98 | } |
| 99 | |
| 100 | mutex_unlock(&adev->pm.mutex); |
| 101 | return 0; |
| 102 | |
| 103 | fail: |
| 104 | adev->firmware.smu_load = false; |
| 105 | mutex_unlock(&adev->pm.mutex); |
| 106 | return -EINVAL; |
| 107 | } |
| 108 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 109 | static int tonga_dpm_hw_fini(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 110 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 111 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 112 | |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 113 | mutex_lock(&adev->pm.mutex); |
Alex Deucher | aaf4ee3 | 2015-06-09 17:42:10 -0400 | [diff] [blame] | 114 | /* smu fini only needs to be called at teardown, not suspend. |
| 115 | * It should be in sw_fini, but we put it here for symmetry |
| 116 | * with smu init. |
| 117 | */ |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 118 | tonga_smu_fini(adev); |
| 119 | mutex_unlock(&adev->pm.mutex); |
| 120 | return 0; |
| 121 | } |
| 122 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 123 | static int tonga_dpm_suspend(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 124 | { |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 125 | return 0; |
| 126 | } |
| 127 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 128 | static int tonga_dpm_resume(void *handle) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 129 | { |
Alex Deucher | aaf4ee3 | 2015-06-09 17:42:10 -0400 | [diff] [blame] | 130 | int ret; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 131 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 132 | |
Alex Deucher | aaf4ee3 | 2015-06-09 17:42:10 -0400 | [diff] [blame] | 133 | mutex_lock(&adev->pm.mutex); |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 134 | |
Alex Deucher | aaf4ee3 | 2015-06-09 17:42:10 -0400 | [diff] [blame] | 135 | ret = tonga_smu_start(adev); |
| 136 | if (ret) { |
| 137 | DRM_ERROR("SMU start failed\n"); |
| 138 | goto fail; |
| 139 | } |
| 140 | |
| 141 | fail: |
| 142 | mutex_unlock(&adev->pm.mutex); |
| 143 | return ret; |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 144 | } |
| 145 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 146 | static int tonga_dpm_set_clockgating_state(void *handle, |
| 147 | enum amd_clockgating_state state) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 148 | { |
| 149 | return 0; |
| 150 | } |
| 151 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 152 | static int tonga_dpm_set_powergating_state(void *handle, |
| 153 | enum amd_powergating_state state) |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 154 | { |
| 155 | return 0; |
| 156 | } |
| 157 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 158 | const struct amd_ip_funcs tonga_dpm_ip_funcs = { |
Alex Deucher | aaa36a9 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 159 | .early_init = tonga_dpm_early_init, |
| 160 | .late_init = NULL, |
| 161 | .sw_init = tonga_dpm_sw_init, |
| 162 | .sw_fini = tonga_dpm_sw_fini, |
| 163 | .hw_init = tonga_dpm_hw_init, |
| 164 | .hw_fini = tonga_dpm_hw_fini, |
| 165 | .suspend = tonga_dpm_suspend, |
| 166 | .resume = tonga_dpm_resume, |
| 167 | .is_idle = NULL, |
| 168 | .wait_for_idle = NULL, |
| 169 | .soft_reset = NULL, |
| 170 | .print_status = NULL, |
| 171 | .set_clockgating_state = tonga_dpm_set_clockgating_state, |
| 172 | .set_powergating_state = tonga_dpm_set_powergating_state, |
| 173 | }; |
| 174 | |
| 175 | static const struct amdgpu_dpm_funcs tonga_dpm_funcs = { |
| 176 | .get_temperature = NULL, |
| 177 | .pre_set_power_state = NULL, |
| 178 | .set_power_state = NULL, |
| 179 | .post_set_power_state = NULL, |
| 180 | .display_configuration_changed = NULL, |
| 181 | .get_sclk = NULL, |
| 182 | .get_mclk = NULL, |
| 183 | .print_power_state = NULL, |
| 184 | .debugfs_print_current_performance_level = NULL, |
| 185 | .force_performance_level = NULL, |
| 186 | .vblank_too_short = NULL, |
| 187 | .powergate_uvd = NULL, |
| 188 | }; |
| 189 | |
| 190 | static void tonga_dpm_set_funcs(struct amdgpu_device *adev) |
| 191 | { |
| 192 | if (NULL == adev->pm.funcs) |
| 193 | adev->pm.funcs = &tonga_dpm_funcs; |
| 194 | } |