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gerrit-public.fairphone.software / kernel / msm-5.4 / 5d964837c6a743193c63c8912f98834c7457ba5c / . / drivers / scsi / qla2xxx / qla_nx2.h
blob: 83c1b7e17c80f1affa2a5857118f44a6549d832a [file] [log] [blame]
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]1/*
2 * QLogic Fibre Channel HBA Driver
Armen Baloyanbd21eaf2014-04-11 16:54:24 -0400[diff] [blame]3 * Copyright (c) 2003-2014 QLogic Corporation
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7
8#ifndef __QLA_NX2_H
9#define __QLA_NX2_H
10
11#define QSNT_ACK_TOV 30
12#define INTENT_TO_RECOVER 0x01
13#define PROCEED_TO_RECOVER 0x02
14#define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
15#define IDC_LOCK_RECOVERY_STATE_MASK 0x3
16#define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS 2
17
18#define QLA8044_DRV_LOCK_MSLEEP 200
19#define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
20#define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
21
22#define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
23#define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
24#define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
25#define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
26#define MD_MIU_TEST_AGT_RDDATA_LO 0x410000A8
27#define MD_MIU_TEST_AGT_RDDATA_HI 0x410000AC
28#define MD_MIU_TEST_AGT_RDDATA_ULO 0x410000B8
29#define MD_MIU_TEST_AGT_RDDATA_UHI 0x410000BC
30
31/* MIU_TEST_AGT_CTRL flags. work for SIU as well */
32#define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
33#define MIU_TA_CTL_WRITE_START (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
34 MIU_TA_CTL_START)
35#define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
36
37/* Imbus address bit used to indicate a host address. This bit is
38 * eliminated by the pcie bar and bar select before presentation
39 * over pcie. */
40/* host memory via IMBUS */
41#define QLA8044_P2_ADDR_PCIE (0x0000000800000000ULL)
42#define QLA8044_P3_ADDR_PCIE (0x0000008000000000ULL)
43#define QLA8044_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
44#define QLA8044_ADDR_OCM0 (0x0000000200000000ULL)
45#define QLA8044_ADDR_OCM0_MAX (0x00000002000fffffULL)
46#define QLA8044_ADDR_OCM1 (0x0000000200400000ULL)
47#define QLA8044_ADDR_OCM1_MAX (0x00000002004fffffULL)
48#define QLA8044_ADDR_QDR_NET (0x0000000300000000ULL)
49#define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
50#define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
51#define QLA8044_ADDR_QDR_NET_MAX (0x0000000307ffffffULL)
52#define QLA8044_PCI_CRBSPACE ((unsigned long)0x06000000)
53#define QLA8044_PCI_DIRECT_CRB ((unsigned long)0x04400000)
54#define QLA8044_PCI_CAMQM ((unsigned long)0x04800000)
55#define QLA8044_PCI_CAMQM_MAX ((unsigned long)0x04ffffff)
56#define QLA8044_PCI_DDR_NET ((unsigned long)0x00000000)
57#define QLA8044_PCI_QDR_NET ((unsigned long)0x04000000)
58#define QLA8044_PCI_QDR_NET_MAX ((unsigned long)0x043fffff)
59
60/* PCI Windowing for DDR regions. */
Bart Van Asschedf3f4cd2015-07-09 07:23:46 -0700[diff] [blame]61static inline bool addr_in_range(u64 addr, u64 low, u64 high)
62{
63 return addr <= high && addr >= low;
64}
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]65
66/* Indirectly Mapped Registers */
67#define QLA8044_FLASH_SPI_STATUS 0x2808E010
68#define QLA8044_FLASH_SPI_CONTROL 0x2808E014
69#define QLA8044_FLASH_STATUS 0x42100004
70#define QLA8044_FLASH_CONTROL 0x42110004
71#define QLA8044_FLASH_ADDR 0x42110008
72#define QLA8044_FLASH_WRDATA 0x4211000C
73#define QLA8044_FLASH_RDDATA 0x42110018
74#define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
75#define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
76
77/* Flash access regs */
78#define QLA8044_FLASH_LOCK 0x3850
79#define QLA8044_FLASH_UNLOCK 0x3854
80#define QLA8044_FLASH_LOCK_ID 0x3500
81
82/* Driver Lock regs */
83#define QLA8044_DRV_LOCK 0x3868
84#define QLA8044_DRV_UNLOCK 0x386C
85#define QLA8044_DRV_LOCK_ID 0x3504
86#define QLA8044_DRV_LOCKRECOVERY 0x379C
87
88/* IDC version */
89#define QLA8044_IDC_VER_MAJ_VALUE 0x1
90#define QLA8044_IDC_VER_MIN_VALUE 0x0
91
92/* IDC Registers : Driver Coexistence Defines */
93#define QLA8044_CRB_IDC_VER_MAJOR 0x3780
94#define QLA8044_CRB_IDC_VER_MINOR 0x3798
95#define QLA8044_IDC_DRV_AUDIT 0x3794
96#define QLA8044_SRE_SHIM_CONTROL 0x0D200284
97#define QLA8044_PORT0_RXB_PAUSE_THRS 0x0B2003A4
98#define QLA8044_PORT1_RXB_PAUSE_THRS 0x0B2013A4
99#define QLA8044_PORT0_RXB_TC_MAX_CELL 0x0B200388
100#define QLA8044_PORT1_RXB_TC_MAX_CELL 0x0B201388
101#define QLA8044_PORT0_RXB_TC_STATS 0x0B20039C
102#define QLA8044_PORT1_RXB_TC_STATS 0x0B20139C
103#define QLA8044_PORT2_IFB_PAUSE_THRS 0x0B200704
104#define QLA8044_PORT3_IFB_PAUSE_THRS 0x0B201704
105
106/* set value to pause threshold value */
107#define QLA8044_SET_PAUSE_VAL 0x0
108#define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
109#define QLA8044_PEG_HALT_STATUS1 0x34A8
110#define QLA8044_PEG_HALT_STATUS2 0x34AC
111#define QLA8044_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
112#define QLA8044_FW_CAPABILITIES 0x3528
113#define QLA8044_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
114#define QLA8044_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
115#define QLA8044_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
116#define QLA8044_CRB_DRV_SCRATCH 0x3548
117#define QLA8044_CRB_DEV_PART_INFO1 0x37E0
118#define QLA8044_CRB_DEV_PART_INFO2 0x37E4
119#define QLA8044_FW_VER_MAJOR 0x3550
120#define QLA8044_FW_VER_MINOR 0x3554
121#define QLA8044_FW_VER_SUB 0x3558
122#define QLA8044_NPAR_STATE 0x359C
123#define QLA8044_FW_IMAGE_VALID 0x35FC
124#define QLA8044_CMDPEG_STATE 0x3650
125#define QLA8044_ASIC_TEMP 0x37B4
126#define QLA8044_FW_API 0x356C
127#define QLA8044_DRV_OP_MODE 0x3570
128#define QLA8044_CRB_WIN_BASE 0x3800
129#define QLA8044_CRB_WIN_FUNC(f) (QLA8044_CRB_WIN_BASE+((f)*4))
130#define QLA8044_SEM_LOCK_BASE 0x3840
131#define QLA8044_SEM_UNLOCK_BASE 0x3844
132#define QLA8044_SEM_LOCK_FUNC(f) (QLA8044_SEM_LOCK_BASE+((f)*8))
133#define QLA8044_SEM_UNLOCK_FUNC(f) (QLA8044_SEM_UNLOCK_BASE+((f)*8))
134#define QLA8044_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
135#define QLA8044_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
136#define QLA8044_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
137#define QLA8044_LINK_SPEED_FACTOR 10
Hiral Patela018d8f2014-04-11 16:54:34 -0400[diff] [blame]138#define QLA8044_FUN7_ACTIVE_INDEX 0x80
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]139
140/* FLASH API Defines */
141#define QLA8044_FLASH_MAX_WAIT_USEC 100
142#define QLA8044_FLASH_LOCK_TIMEOUT 10000
143#define QLA8044_FLASH_SECTOR_SIZE 65536
144#define QLA8044_DRV_LOCK_TIMEOUT 2000
145#define QLA8044_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
146#define QLA8044_FLASH_WRITE_CMD 0xdacdacda
147#define QLA8044_FLASH_BUFFER_WRITE_CMD 0xcadcadca
148#define QLA8044_FLASH_READ_RETRY_COUNT 2000
149#define QLA8044_FLASH_STATUS_READY 0x6
150#define QLA8044_FLASH_BUFFER_WRITE_MIN 2
151#define QLA8044_FLASH_BUFFER_WRITE_MAX 64
152#define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
153#define QLA8044_ERASE_MODE 1
154#define QLA8044_WRITE_MODE 2
155#define QLA8044_DWORD_WRITE_MODE 3
156#define QLA8044_GLOBAL_RESET 0x38CC
157#define QLA8044_WILDCARD 0x38F0
158#define QLA8044_INFORMANT 0x38FC
159#define QLA8044_HOST_MBX_CTRL 0x3038
160#define QLA8044_FW_MBX_CTRL 0x303C
161#define QLA8044_BOOTLOADER_ADDR 0x355C
162#define QLA8044_BOOTLOADER_SIZE 0x3560
163#define QLA8044_FW_IMAGE_ADDR 0x3564
164#define QLA8044_MBX_INTR_ENABLE 0x1000
165#define QLA8044_MBX_INTR_MASK 0x1200
166
167/* IDC Control Register bit defines */
168#define DONTRESET_BIT0 0x1
169#define GRACEFUL_RESET_BIT1 0x2
170
171/* ISP8044 PEG_HALT_STATUS1 bits */
172#define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
173#define QLA8044_HALT_STATUS_FW_RESET (0x2 << 29)
174#define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
175
176/* Firmware image definitions */
177#define QLA8044_BOOTLOADER_FLASH_ADDR 0x10000
178#define QLA8044_BOOT_FROM_FLASH 0
179#define QLA8044_IDC_PARAM_ADDR 0x3e8020
180
181/* FLASH related definitions */
182#define QLA8044_OPTROM_BURST_SIZE 0x100
183#define QLA8044_MAX_OPTROM_BURST_DWORDS (QLA8044_OPTROM_BURST_SIZE / 4)
184#define QLA8044_MIN_OPTROM_BURST_DWORDS 2
185#define QLA8044_SECTOR_SIZE (64 * 1024)
186
187#define QLA8044_FLASH_SPI_CTL 0x4
188#define QLA8044_FLASH_FIRST_TEMP_VAL 0x00800000
189#define QLA8044_FLASH_SECOND_TEMP_VAL 0x00800001
190#define QLA8044_FLASH_FIRST_MS_PATTERN 0x43
191#define QLA8044_FLASH_SECOND_MS_PATTERN 0x7F
192#define QLA8044_FLASH_LAST_MS_PATTERN 0x7D
193#define QLA8044_FLASH_STATUS_WRITE_DEF_SIG 0xFD0100
194#define QLA8044_FLASH_SECOND_ERASE_MS_VAL 0x5
195#define QLA8044_FLASH_ERASE_SIG 0xFD0300
196#define QLA8044_FLASH_LAST_ERASE_MS_VAL 0x3D
197
198/* Reset template definitions */
199#define QLA8044_MAX_RESET_SEQ_ENTRIES 16
200#define QLA8044_RESTART_TEMPLATE_SIZE 0x2000
201#define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
202#define QLA8044_RESET_SEQ_VERSION 0x0101
203
204/* Reset template entry opcodes */
205#define OPCODE_NOP 0x0000
206#define OPCODE_WRITE_LIST 0x0001
207#define OPCODE_READ_WRITE_LIST 0x0002
208#define OPCODE_POLL_LIST 0x0004
209#define OPCODE_POLL_WRITE_LIST 0x0008
210#define OPCODE_READ_MODIFY_WRITE 0x0010
211#define OPCODE_SEQ_PAUSE 0x0020
212#define OPCODE_SEQ_END 0x0040
213#define OPCODE_TMPL_END 0x0080
214#define OPCODE_POLL_READ_LIST 0x0100
215
216/* Template Header */
217#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
218#define QLA8044_IDC_DRV_CTRL 0x3790
219#define AF_8044_NO_FW_DUMP 27 /* 0x08000000 */
220
221#define MINIDUMP_SIZE_36K 36864
222
223struct qla8044_reset_template_hdr {
224 uint16_t version;
225 uint16_t signature;
226 uint16_t size;
227 uint16_t entries;
228 uint16_t hdr_size;
229 uint16_t checksum;
230 uint16_t init_seq_offset;
231 uint16_t start_seq_offset;
232} __packed;
233
234/* Common Entry Header. */
235struct qla8044_reset_entry_hdr {
236 uint16_t cmd;
237 uint16_t size;
238 uint16_t count;
239 uint16_t delay;
240} __packed;
241
242/* Generic poll entry type. */
243struct qla8044_poll {
244 uint32_t test_mask;
245 uint32_t test_value;
246} __packed;
247
248/* Read modify write entry type. */
249struct qla8044_rmw {
250 uint32_t test_mask;
251 uint32_t xor_value;
252 uint32_t or_value;
253 uint8_t shl;
254 uint8_t shr;
255 uint8_t index_a;
256 uint8_t rsvd;
257} __packed;
258
259/* Generic Entry Item with 2 DWords. */
260struct qla8044_entry {
261 uint32_t arg1;
262 uint32_t arg2;
263} __packed;
264
265/* Generic Entry Item with 4 DWords.*/
266struct qla8044_quad_entry {
267 uint32_t dr_addr;
268 uint32_t dr_value;
269 uint32_t ar_addr;
270 uint32_t ar_value;
271} __packed;
272
273struct qla8044_reset_template {
274 int seq_index;
275 int seq_error;
276 int array_index;
277 uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
278 uint8_t *buff;
279 uint8_t *stop_offset;
280 uint8_t *start_offset;
281 uint8_t *init_offset;
282 struct qla8044_reset_template_hdr *hdr;
283 uint8_t seq_end;
284 uint8_t template_end;
285};
286
287/* Driver_code is for driver to write some info about the entry
288 * currently not used.
289 */
290struct qla8044_minidump_entry_hdr {
291 uint32_t entry_type;
292 uint32_t entry_size;
293 uint32_t entry_capture_size;
294 struct {
295 uint8_t entry_capture_mask;
296 uint8_t entry_code;
297 uint8_t driver_code;
298 uint8_t driver_flags;
299 } d_ctrl;
300} __packed;
301
302/* Read CRB entry header */
303struct qla8044_minidump_entry_crb {
304 struct qla8044_minidump_entry_hdr h;
305 uint32_t addr;
306 struct {
307 uint8_t addr_stride;
308 uint8_t state_index_a;
309 uint16_t poll_timeout;
310 } crb_strd;
311 uint32_t data_size;
312 uint32_t op_count;
313
314 struct {
315 uint8_t opcode;
316 uint8_t state_index_v;
317 uint8_t shl;
318 uint8_t shr;
319 } crb_ctrl;
320
321 uint32_t value_1;
322 uint32_t value_2;
323 uint32_t value_3;
324} __packed;
325
326struct qla8044_minidump_entry_cache {
327 struct qla8044_minidump_entry_hdr h;
328 uint32_t tag_reg_addr;
329 struct {
330 uint16_t tag_value_stride;
331 uint16_t init_tag_value;
332 } addr_ctrl;
333 uint32_t data_size;
334 uint32_t op_count;
335 uint32_t control_addr;
336 struct {
337 uint16_t write_value;
338 uint8_t poll_mask;
339 uint8_t poll_wait;
340 } cache_ctrl;
341 uint32_t read_addr;
342 struct {
343 uint8_t read_addr_stride;
344 uint8_t read_addr_cnt;
345 uint16_t rsvd_1;
346 } read_ctrl;
347} __packed;
348
349/* Read OCM */
350struct qla8044_minidump_entry_rdocm {
351 struct qla8044_minidump_entry_hdr h;
352 uint32_t rsvd_0;
353 uint32_t rsvd_1;
354 uint32_t data_size;
355 uint32_t op_count;
356 uint32_t rsvd_2;
357 uint32_t rsvd_3;
358 uint32_t read_addr;
359 uint32_t read_addr_stride;
360} __packed;
361
362/* Read Memory */
363struct qla8044_minidump_entry_rdmem {
364 struct qla8044_minidump_entry_hdr h;
365 uint32_t rsvd[6];
366 uint32_t read_addr;
367 uint32_t read_data_size;
368};
369
370/* Read Memory: For Pex-DMA */
371struct qla8044_minidump_entry_rdmem_pex_dma {
372 struct qla8044_minidump_entry_hdr h;
373 uint32_t desc_card_addr;
374 uint16_t dma_desc_cmd;
375 uint8_t rsvd[2];
376 uint32_t start_dma_cmd;
377 uint8_t rsvd2[12];
378 uint32_t read_addr;
379 uint32_t read_data_size;
380} __packed;
381
382/* Read ROM */
383struct qla8044_minidump_entry_rdrom {
384 struct qla8044_minidump_entry_hdr h;
385 uint32_t rsvd[6];
386 uint32_t read_addr;
387 uint32_t read_data_size;
388} __packed;
389
390/* Mux entry */
391struct qla8044_minidump_entry_mux {
392 struct qla8044_minidump_entry_hdr h;
393 uint32_t select_addr;
394 uint32_t rsvd_0;
395 uint32_t data_size;
396 uint32_t op_count;
397 uint32_t select_value;
398 uint32_t select_value_stride;
399 uint32_t read_addr;
400 uint32_t rsvd_1;
401} __packed;
402
403/* Queue entry */
404struct qla8044_minidump_entry_queue {
405 struct qla8044_minidump_entry_hdr h;
406 uint32_t select_addr;
407 struct {
408 uint16_t queue_id_stride;
409 uint16_t rsvd_0;
410 } q_strd;
411 uint32_t data_size;
412 uint32_t op_count;
413 uint32_t rsvd_1;
414 uint32_t rsvd_2;
415 uint32_t read_addr;
416 struct {
417 uint8_t read_addr_stride;
418 uint8_t read_addr_cnt;
419 uint16_t rsvd_3;
420 } rd_strd;
421} __packed;
422
423/* POLLRD Entry */
424struct qla8044_minidump_entry_pollrd {
425 struct qla8044_minidump_entry_hdr h;
426 uint32_t select_addr;
427 uint32_t read_addr;
428 uint32_t select_value;
429 uint16_t select_value_stride;
430 uint16_t op_count;
431 uint32_t poll_wait;
432 uint32_t poll_mask;
433 uint32_t data_size;
434 uint32_t rsvd_1;
435} __packed;
436
Pratik Mohanty804df802014-04-11 16:54:15 -0400[diff] [blame]437struct qla8044_minidump_entry_rddfe {
438 struct qla8044_minidump_entry_hdr h;
439 uint32_t addr_1;
440 uint32_t value;
441 uint8_t stride;
442 uint8_t stride2;
443 uint16_t count;
444 uint32_t poll;
445 uint32_t mask;
446 uint32_t modify_mask;
447 uint32_t data_size;
448 uint32_t rsvd;
449
450} __packed;
451
452struct qla8044_minidump_entry_rdmdio {
453 struct qla8044_minidump_entry_hdr h;
454
455 uint32_t addr_1;
456 uint32_t addr_2;
457 uint32_t value_1;
458 uint8_t stride_1;
459 uint8_t stride_2;
460 uint16_t count;
461 uint32_t poll;
462 uint32_t mask;
463 uint32_t value_2;
464 uint32_t data_size;
465
466} __packed;
467
468struct qla8044_minidump_entry_pollwr {
469 struct qla8044_minidump_entry_hdr h;
470 uint32_t addr_1;
471 uint32_t addr_2;
472 uint32_t value_1;
473 uint32_t value_2;
474 uint32_t poll;
475 uint32_t mask;
476 uint32_t data_size;
477 uint32_t rsvd;
478
479} __packed;
480
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]481/* RDMUX2 Entry */
482struct qla8044_minidump_entry_rdmux2 {
483 struct qla8044_minidump_entry_hdr h;
484 uint32_t select_addr_1;
485 uint32_t select_addr_2;
486 uint32_t select_value_1;
487 uint32_t select_value_2;
488 uint32_t op_count;
489 uint32_t select_value_mask;
490 uint32_t read_addr;
491 uint8_t select_value_stride;
492 uint8_t data_size;
493 uint8_t rsvd[2];
494} __packed;
495
496/* POLLRDMWR Entry */
497struct qla8044_minidump_entry_pollrdmwr {
498 struct qla8044_minidump_entry_hdr h;
499 uint32_t addr_1;
500 uint32_t addr_2;
501 uint32_t value_1;
502 uint32_t value_2;
503 uint32_t poll_wait;
504 uint32_t poll_mask;
505 uint32_t modify_mask;
506 uint32_t data_size;
507} __packed;
508
509/* IDC additional information */
510struct qla8044_idc_information {
511 uint32_t request_desc; /* IDC request descriptor */
512 uint32_t info1; /* IDC additional info */
513 uint32_t info2; /* IDC additional info */
514 uint32_t info3; /* IDC additional info */
515} __packed;
516
517enum qla_regs {
518 QLA8044_PEG_HALT_STATUS1_INDEX = 0,
519 QLA8044_PEG_HALT_STATUS2_INDEX,
520 QLA8044_PEG_ALIVE_COUNTER_INDEX,
521 QLA8044_CRB_DRV_ACTIVE_INDEX,
522 QLA8044_CRB_DEV_STATE_INDEX,
523 QLA8044_CRB_DRV_STATE_INDEX,
524 QLA8044_CRB_DRV_SCRATCH_INDEX,
525 QLA8044_CRB_DEV_PART_INFO_INDEX,
526 QLA8044_CRB_DRV_IDC_VERSION_INDEX,
527 QLA8044_FW_VERSION_MAJOR_INDEX,
528 QLA8044_FW_VERSION_MINOR_INDEX,
529 QLA8044_FW_VERSION_SUB_INDEX,
530 QLA8044_CRB_CMDPEG_STATE_INDEX,
531 QLA8044_CRB_TEMP_STATE_INDEX,
532} __packed;
533
534#define CRB_REG_INDEX_MAX 14
535#define CRB_CMDPEG_CHECK_RETRY_COUNT 60
536#define CRB_CMDPEG_CHECK_DELAY 500
537
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]538/* MiniDump Structures */
539
540/* Driver_code is for driver to write some info about the entry
541 * currently not used.
542 */
543#define QLA8044_SS_OCM_WNDREG_INDEX 3
544#define QLA8044_DBG_STATE_ARRAY_LEN 16
545#define QLA8044_DBG_CAP_SIZE_ARRAY_LEN 8
546#define QLA8044_DBG_RSVD_ARRAY_LEN 8
547#define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN 16
548#define QLA8044_SS_PCI_INDEX 0
Pratik Mohanty804df802014-04-11 16:54:15 -0400[diff] [blame]549#define QLA8044_RDDFE 38
550#define QLA8044_RDMDIO 39
551#define QLA8044_POLLWR 40
Atul Deshmukh7ec0eff2013-08-27 01:37:28 -0400[diff] [blame]552
553struct qla8044_minidump_template_hdr {
554 uint32_t entry_type;
555 uint32_t first_entry_offset;
556 uint32_t size_of_template;
557 uint32_t capture_debug_level;
558 uint32_t num_of_entries;
559 uint32_t version;
560 uint32_t driver_timestamp;
561 uint32_t checksum;
562
563 uint32_t driver_capture_mask;
564 uint32_t driver_info_word2;
565 uint32_t driver_info_word3;
566 uint32_t driver_info_word4;
567
568 uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
569 uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
570 uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
571};
572
573struct qla8044_pex_dma_descriptor {
574 struct {
575 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
576 uint8_t rsvd[2];
577 uint16_t dma_desc_cmd;
578 } cmd;
579 uint64_t src_addr;
580 uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
581 uint8_t rsvd[24];
582} __packed;
583
584#endif