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Qipeng Zhafdca4f12015-12-11 22:45:00 +08001/*
2 * Driver for the Intel P-Unit Mailbox IPC mechanism
3 *
4 * (C) Copyright 2015 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * The heart of the P-Unit is the Foxton microcontroller and its firmware,
11 * which provide mailbox interface for power management usage.
12 */
13
Qipeng Zhafdca4f12015-12-11 22:45:00 +080014#include <linux/acpi.h>
Qipeng Zhafdca4f12015-12-11 22:45:00 +080015#include <linux/bitops.h>
Andy Shevchenko5e66d082018-09-26 18:27:14 +030016#include <linux/delay.h>
Qipeng Zhafdca4f12015-12-11 22:45:00 +080017#include <linux/device.h>
18#include <linux/interrupt.h>
Randy Dunlap340fd4c2018-08-15 09:12:07 -070019#include <linux/io.h>
Andy Shevchenko5e66d082018-09-26 18:27:14 +030020#include <linux/mod_devicetable.h>
21#include <linux/module.h>
Qipeng Zhafdca4f12015-12-11 22:45:00 +080022#include <linux/platform_device.h>
Andy Shevchenko5e66d082018-09-26 18:27:14 +030023
Qipeng Zhafdca4f12015-12-11 22:45:00 +080024#include <asm/intel_punit_ipc.h>
25
26/* IPC Mailbox registers */
27#define OFFSET_DATA_LOW 0x0
28#define OFFSET_DATA_HIGH 0x4
29/* bit field of interface register */
30#define CMD_RUN BIT(31)
31#define CMD_ERRCODE_MASK GENMASK(7, 0)
32#define CMD_PARA1_SHIFT 8
33#define CMD_PARA2_SHIFT 16
34
35#define CMD_TIMEOUT_SECONDS 1
36
37enum {
38 BASE_DATA = 0,
39 BASE_IFACE,
40 BASE_MAX,
41};
42
43typedef struct {
44 struct device *dev;
45 struct mutex lock;
46 int irq;
47 struct completion cmd_complete;
48 /* base of interface and data registers */
49 void __iomem *base[RESERVED_IPC][BASE_MAX];
50 IPC_TYPE type;
51} IPC_DEV;
52
53static IPC_DEV *punit_ipcdev;
54
55static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type)
56{
57 return readl(ipcdev->base[type][BASE_IFACE]);
58}
59
60static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd)
61{
62 writel(cmd, ipcdev->base[type][BASE_IFACE]);
63}
64
65static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type)
66{
67 return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
68}
69
70static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type)
71{
72 return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
73}
74
75static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
76{
77 writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
78}
79
80static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
81{
82 writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
83}
84
85static const char *ipc_err_string(int error)
86{
87 if (error == IPC_PUNIT_ERR_SUCCESS)
88 return "no error";
89 else if (error == IPC_PUNIT_ERR_INVALID_CMD)
90 return "invalid command";
91 else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER)
92 return "invalid parameter";
93 else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT)
94 return "command timeout";
95 else if (error == IPC_PUNIT_ERR_CMD_LOCKED)
96 return "command locked";
97 else if (error == IPC_PUNIT_ERR_INVALID_VR_ID)
98 return "invalid vr id";
99 else if (error == IPC_PUNIT_ERR_VR_ERR)
100 return "vr error";
101 else
102 return "unknown error";
103}
104
105static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type)
106{
107 int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC;
108 int errcode;
109 int status;
110
111 if (ipcdev->irq) {
112 if (!wait_for_completion_timeout(&ipcdev->cmd_complete,
113 CMD_TIMEOUT_SECONDS * HZ)) {
114 dev_err(ipcdev->dev, "IPC timed out\n");
115 return -ETIMEDOUT;
116 }
117 } else {
118 while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops)
119 udelay(1);
120 if (!loops) {
121 dev_err(ipcdev->dev, "IPC timed out\n");
122 return -ETIMEDOUT;
123 }
124 }
125
126 status = ipc_read_status(ipcdev, type);
127 errcode = status & CMD_ERRCODE_MASK;
128 if (errcode) {
129 dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n",
130 ipc_err_string(errcode), status);
131 return -EIO;
132 }
133
134 return 0;
135}
136
137/**
138 * intel_punit_ipc_simple_command() - Simple IPC command
139 * @cmd: IPC command code.
140 * @para1: First 8bit parameter, set 0 if not used.
141 * @para2: Second 8bit parameter, set 0 if not used.
142 *
143 * Send a IPC command to P-Unit when there is no data transaction
144 *
145 * Return: IPC error code or 0 on success.
146 */
147int intel_punit_ipc_simple_command(int cmd, int para1, int para2)
148{
149 IPC_DEV *ipcdev = punit_ipcdev;
150 IPC_TYPE type;
151 u32 val;
152 int ret;
153
154 mutex_lock(&ipcdev->lock);
155
156 reinit_completion(&ipcdev->cmd_complete);
157 type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
158
159 val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
160 val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
161 ipc_write_cmd(ipcdev, type, val);
162 ret = intel_punit_ipc_check_status(ipcdev, type);
163
164 mutex_unlock(&ipcdev->lock);
165
166 return ret;
167}
168EXPORT_SYMBOL(intel_punit_ipc_simple_command);
169
170/**
171 * intel_punit_ipc_command() - IPC command with data and pointers
172 * @cmd: IPC command code.
173 * @para1: First 8bit parameter, set 0 if not used.
174 * @para2: Second 8bit parameter, set 0 if not used.
175 * @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD.
176 * @out: Output data.
177 *
178 * Send a IPC command to P-Unit with data transaction
179 *
180 * Return: IPC error code or 0 on success.
181 */
182int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out)
183{
184 IPC_DEV *ipcdev = punit_ipcdev;
185 IPC_TYPE type;
186 u32 val;
187 int ret;
188
189 mutex_lock(&ipcdev->lock);
190
191 reinit_completion(&ipcdev->cmd_complete);
192 type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800193
Qipeng Zha3fae7572016-01-08 18:32:27 +0800194 if (in) {
195 ipc_write_data_low(ipcdev, type, *in);
196 if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
197 ipc_write_data_high(ipcdev, type, *++in);
198 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800199
200 val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
201 val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
202 ipc_write_cmd(ipcdev, type, val);
203
204 ret = intel_punit_ipc_check_status(ipcdev, type);
205 if (ret)
206 goto out;
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800207
Qipeng Zha3fae7572016-01-08 18:32:27 +0800208 if (out) {
209 *out = ipc_read_data_low(ipcdev, type);
210 if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
211 *++out = ipc_read_data_high(ipcdev, type);
212 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800213
214out:
215 mutex_unlock(&ipcdev->lock);
216 return ret;
217}
218EXPORT_SYMBOL_GPL(intel_punit_ipc_command);
219
220static irqreturn_t intel_punit_ioc(int irq, void *dev_id)
221{
222 IPC_DEV *ipcdev = dev_id;
223
224 complete(&ipcdev->cmd_complete);
225 return IRQ_HANDLED;
226}
227
228static int intel_punit_get_bars(struct platform_device *pdev)
229{
230 struct resource *res;
231 void __iomem *addr;
232
Aubrey Li5d071632016-03-31 14:28:09 -0500233 /*
234 * The following resources are required
235 * - BIOS_IPC BASE_DATA
236 * - BIOS_IPC BASE_IFACE
237 */
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239 addr = devm_ioremap_resource(&pdev->dev, res);
240 if (IS_ERR(addr))
241 return PTR_ERR(addr);
242 punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr;
243
244 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
245 addr = devm_ioremap_resource(&pdev->dev, res);
246 if (IS_ERR(addr))
247 return PTR_ERR(addr);
248 punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr;
249
Aubrey Li5d071632016-03-31 14:28:09 -0500250 /*
251 * The following resources are optional
252 * - ISPDRIVER_IPC BASE_DATA
253 * - ISPDRIVER_IPC BASE_IFACE
254 * - GTDRIVER_IPC BASE_DATA
255 * - GTDRIVER_IPC BASE_IFACE
256 */
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800257 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
Kuppuswamy Sathyanarayanan6cc8cbb2017-10-29 02:49:54 -0700258 if (res && resource_size(res) > 1) {
Aubrey Li5d071632016-03-31 14:28:09 -0500259 addr = devm_ioremap_resource(&pdev->dev, res);
260 if (!IS_ERR(addr))
261 punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr;
262 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800263
264 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
Kuppuswamy Sathyanarayanan6cc8cbb2017-10-29 02:49:54 -0700265 if (res && resource_size(res) > 1) {
Aubrey Li5d071632016-03-31 14:28:09 -0500266 addr = devm_ioremap_resource(&pdev->dev, res);
267 if (!IS_ERR(addr))
268 punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr;
269 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800270
271 res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
Kuppuswamy Sathyanarayanan6cc8cbb2017-10-29 02:49:54 -0700272 if (res && resource_size(res) > 1) {
Aubrey Li5d071632016-03-31 14:28:09 -0500273 addr = devm_ioremap_resource(&pdev->dev, res);
274 if (!IS_ERR(addr))
275 punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr;
276 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800277
278 res = platform_get_resource(pdev, IORESOURCE_MEM, 5);
Kuppuswamy Sathyanarayanan6cc8cbb2017-10-29 02:49:54 -0700279 if (res && resource_size(res) > 1) {
Aubrey Li5d071632016-03-31 14:28:09 -0500280 addr = devm_ioremap_resource(&pdev->dev, res);
281 if (!IS_ERR(addr))
282 punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr;
283 }
Qipeng Zhafdca4f12015-12-11 22:45:00 +0800284
285 return 0;
286}
287
288static int intel_punit_ipc_probe(struct platform_device *pdev)
289{
290 int irq, ret;
291
292 punit_ipcdev = devm_kzalloc(&pdev->dev,
293 sizeof(*punit_ipcdev), GFP_KERNEL);
294 if (!punit_ipcdev)
295 return -ENOMEM;
296
297 platform_set_drvdata(pdev, punit_ipcdev);
298
299 irq = platform_get_irq(pdev, 0);
300 if (irq < 0) {
301 punit_ipcdev->irq = 0;
302 dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n");
303 } else {
304 ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
305 IRQF_NO_SUSPEND, "intel_punit_ipc",
306 &punit_ipcdev);
307 if (ret) {
308 dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
309 return ret;
310 }
311 punit_ipcdev->irq = irq;
312 }
313
314 ret = intel_punit_get_bars(pdev);
315 if (ret)
316 goto out;
317
318 punit_ipcdev->dev = &pdev->dev;
319 mutex_init(&punit_ipcdev->lock);
320 init_completion(&punit_ipcdev->cmd_complete);
321
322out:
323 return ret;
324}
325
326static int intel_punit_ipc_remove(struct platform_device *pdev)
327{
328 return 0;
329}
330
331static const struct acpi_device_id punit_ipc_acpi_ids[] = {
332 { "INT34D4", 0 },
333 { }
334};
335
336static struct platform_driver intel_punit_ipc_driver = {
337 .probe = intel_punit_ipc_probe,
338 .remove = intel_punit_ipc_remove,
339 .driver = {
340 .name = "intel_punit_ipc",
341 .acpi_match_table = ACPI_PTR(punit_ipc_acpi_ids),
342 },
343};
344
345static int __init intel_punit_ipc_init(void)
346{
347 return platform_driver_register(&intel_punit_ipc_driver);
348}
349
350static void __exit intel_punit_ipc_exit(void)
351{
352 platform_driver_unregister(&intel_punit_ipc_driver);
353}
354
355MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
356MODULE_DESCRIPTION("Intel P-Unit IPC driver");
357MODULE_LICENSE("GPL v2");
358
359/* Some modules are dependent on this, so init earlier */
360fs_initcall(intel_punit_ipc_init);
361module_exit(intel_punit_ipc_exit);