| Vinod Koul | b3c567e | 2010-07-21 13:28:10 +0530 | [diff] [blame] | 1 | /* |
| 2 | * intel_mid_dma.h - Intel MID DMA Drivers |
| 3 | * |
| 4 | * Copyright (C) 2008-10 Intel Corp |
| 5 | * Author: Vinod Koul <vinod.koul@intel.com> |
| 6 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but |
| 13 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 19 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
| 20 | * |
| 21 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 22 | * |
| 23 | * |
| 24 | */ |
| 25 | #ifndef __INTEL_MID_DMA_H__ |
| 26 | #define __INTEL_MID_DMA_H__ |
| 27 | |
| 28 | #include <linux/dmaengine.h> |
| 29 | |
| 30 | /*DMA transaction width, src and dstn width would be same |
| 31 | The DMA length must be width aligned, |
| 32 | for 32 bit width the length must be 32 bit (4bytes) aligned only*/ |
| 33 | enum intel_mid_dma_width { |
| 34 | LNW_DMA_WIDTH_8BIT = 0x0, |
| 35 | LNW_DMA_WIDTH_16BIT = 0x1, |
| 36 | LNW_DMA_WIDTH_32BIT = 0x2, |
| 37 | }; |
| 38 | |
| 39 | /*DMA mode configurations*/ |
| 40 | enum intel_mid_dma_mode { |
| 41 | LNW_DMA_PER_TO_MEM = 0, /*periphral to memory configuration*/ |
| 42 | LNW_DMA_MEM_TO_PER, /*memory to periphral configuration*/ |
| 43 | LNW_DMA_MEM_TO_MEM, /*mem to mem confg (testing only)*/ |
| 44 | }; |
| 45 | |
| 46 | /*DMA handshaking*/ |
| 47 | enum intel_mid_dma_hs_mode { |
| 48 | LNW_DMA_HW_HS = 0, /*HW Handshaking only*/ |
| 49 | LNW_DMA_SW_HS = 1, /*SW Handshaking not recommended*/ |
| 50 | }; |
| 51 | |
| 52 | /*Burst size configuration*/ |
| 53 | enum intel_mid_dma_msize { |
| 54 | LNW_DMA_MSIZE_1 = 0x0, |
| 55 | LNW_DMA_MSIZE_4 = 0x1, |
| 56 | LNW_DMA_MSIZE_8 = 0x2, |
| 57 | LNW_DMA_MSIZE_16 = 0x3, |
| 58 | LNW_DMA_MSIZE_32 = 0x4, |
| 59 | LNW_DMA_MSIZE_64 = 0x5, |
| 60 | }; |
| 61 | |
| 62 | /** |
| 63 | * struct intel_mid_dma_slave - DMA slave structure |
| 64 | * |
| 65 | * @dirn: DMA trf direction |
| 66 | * @src_width: tx register width |
| 67 | * @dst_width: rx register width |
| 68 | * @hs_mode: HW/SW handshaking mode |
| 69 | * @cfg_mode: DMA data transfer mode (per-per/mem-per/mem-mem) |
| 70 | * @src_msize: Source DMA burst size |
| 71 | * @dst_msize: Dst DMA burst size |
| 72 | * @device_instance: DMA peripheral device instance, we can have multiple |
| 73 | * peripheral device connected to single DMAC |
| 74 | */ |
| 75 | struct intel_mid_dma_slave { |
| 76 | enum dma_data_direction dirn; |
| 77 | enum intel_mid_dma_width src_width; /*width of DMA src txn*/ |
| 78 | enum intel_mid_dma_width dst_width; /*width of DMA dst txn*/ |
| 79 | enum intel_mid_dma_hs_mode hs_mode; /*handshaking*/ |
| 80 | enum intel_mid_dma_mode cfg_mode; /*mode configuration*/ |
| 81 | enum intel_mid_dma_msize src_msize; /*size if src burst*/ |
| 82 | enum intel_mid_dma_msize dst_msize; /*size of dst burst*/ |
| 83 | unsigned int device_instance; /*0, 1 for periphral instance*/ |
| 84 | }; |
| 85 | |
| 86 | #endif /*__INTEL_MID_DMA_H__*/ |