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gerrit-public.fairphone.software / kernel / msm-5.4 / 61cd2ebb35dcf1990f66af76649260a79ae4cb15 / . / drivers / net / dsa / bcm_sf2.h
blob: 260bab313e585d0608fb334e877b63cac32da8a2 [file] [log] [blame]
Florian Fainelli246d7f72014-08-27 17:04:56 -0700[diff] [blame]1/*
2 * Broadcom Starfighter2 private context
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __BCM_SF2_H
13#define __BCM_SF2_H
14
15#include <linux/platform_device.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/mutex.h>
20#include <linux/mii.h>
21
22#include <net/dsa.h>
23
24#include "bcm_sf2_regs.h"
25
26struct bcm_sf2_hw_params {
27 u16 top_rev;
28 u16 core_rev;
29 u32 num_gphy;
30 u8 num_acb_queue;
31 u8 num_rgmii;
32 u8 num_ports;
33 u8 fcb_pause_override:1;
34 u8 acb_packets_inflight:1;
35};
36
37#define BCM_SF2_REGS_NAME {\
38 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
39}
40
41#define BCM_SF2_REGS_NUM 6
42
43struct bcm_sf2_port_status {
44 unsigned int link;
45};
46
47struct bcm_sf2_priv {
48 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
49 void __iomem *core;
50 void __iomem *reg;
51 void __iomem *intrl2_0;
52 void __iomem *intrl2_1;
53 void __iomem *fcb;
54 void __iomem *acb;
55
56 /* spinlock protecting access to the indirect registers */
57 spinlock_t indir_lock;
58
59 int irq0;
60 int irq1;
61 u32 irq0_stat;
62 u32 irq0_mask;
63 u32 irq1_stat;
64 u32 irq1_mask;
65
66 /* Mutex protecting access to the MIB counters */
67 struct mutex stats_mutex;
68
69 struct bcm_sf2_hw_params hw_params;
70
71 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
72};
73
74struct bcm_sf2_hw_stats {
75 const char *string;
76 u16 reg;
77 u8 sizeof_stat;
78};
79
80#define SF2_IO_MACRO(name) \
81static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
82{ \
83 return __raw_readl(priv->name + off); \
84} \
85static inline void name##_writel(struct bcm_sf2_priv *priv, \
86 u32 val, u32 off) \
87{ \
88 __raw_writel(val, priv->name + off); \
89} \
90
91/* Accesses to 64-bits register requires us to latch the hi/lo pairs
92 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
93 * spinlock is automatically grabbed and released to provide relative
94 * atomiticy with latched reads/writes.
95 */
96#define SF2_IO64_MACRO(name) \
97static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
98{ \
99 u32 indir, dir; \
100 spin_lock(&priv->indir_lock); \
101 indir = reg_readl(priv, REG_DIR_DATA_READ); \
102 dir = __raw_readl(priv->name + off); \
103 spin_unlock(&priv->indir_lock); \
104 return (u64)indir << 32 | dir; \
105} \
106static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off, \
107 u64 val) \
108{ \
109 spin_lock(&priv->indir_lock); \
110 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
111 __raw_writel(lower_32_bits(val), priv->name + off); \
112 spin_unlock(&priv->indir_lock); \
113}
114
115#define SWITCH_INTR_L2(which) \
116static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
117 u32 mask) \
118{ \
119 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
120 priv->irq##which##_mask &= ~(mask); \
121} \
122static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
123 u32 mask) \
124{ \
125 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
126 priv->irq##which##_mask |= (mask); \
127} \
128
129SF2_IO_MACRO(core);
130SF2_IO_MACRO(reg);
131SF2_IO64_MACRO(core);
132SF2_IO_MACRO(intrl2_0);
133SF2_IO_MACRO(intrl2_1);
134SF2_IO_MACRO(fcb);
135SF2_IO_MACRO(acb);
136
137SWITCH_INTR_L2(0);
138SWITCH_INTR_L2(1);
139
140#endif /* __BCM_SF2_H */