blob: 9826ac6a7596fd6948b19f96bbfd5ea2cb6d7899 [file] [log] [blame]
Geert Uytterhoeven80978a42017-04-24 16:54:14 +02001config CLK_RENESAS
2 bool "Renesas SoC clock support" if COMPILE_TEST && !ARCH_RENESAS
3 default y if ARCH_RENESAS
4 select CLK_EMEV2 if ARCH_EMEV2
5 select CLK_RZA1 if ARCH_R7S72100
6 select CLK_R8A73A4 if ARCH_R8A73A4
7 select CLK_R8A7740 if ARCH_R8A7740
8 select CLK_R8A7743 if ARCH_R8A7743
9 select CLK_R8A7745 if ARCH_R8A7745
10 select CLK_R8A7778 if ARCH_R8A7778
11 select CLK_R8A7779 if ARCH_R8A7779
12 select CLK_R8A7790 if ARCH_R8A7790
13 select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
14 select CLK_R8A7792 if ARCH_R8A7792
15 select CLK_R8A7794 if ARCH_R8A7794
16 select CLK_R8A7795 if ARCH_R8A7795
17 select CLK_R8A7796 if ARCH_R8A7796
18 select CLK_SH73A0 if ARCH_SH73A0
19
20if CLK_RENESAS
21
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010022config CLK_RENESAS_LEGACY
23 bool "Legacy DT clock support"
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +020024 depends on CLK_R8A7790 || CLK_R8A7791
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010025 default y
26 help
27 Enable backward compatibility with old device trees describing a
28 hierarchical representation of the various CPG and MSTP clocks.
29
30 Say Y if you want your kernel to work with old DTBs.
31
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020032# SoC
33config CLK_EMEV2
34 bool "Emma Mobile EV2 clock support" if COMPILE_TEST
35
36config CLK_RZA1
37 bool
38 select CLK_RENESAS_CPG_MSTP
39
40config CLK_R8A73A4
41 bool
42 select CLK_RENESAS_CPG_MSTP
43 select CLK_RENESAS_DIV6
44
45config CLK_R8A7740
46 bool
47 select CLK_RENESAS_CPG_MSTP
48 select CLK_RENESAS_DIV6
49
50config CLK_R8A7743
51 bool
52 select CLK_RCAR_GEN2_CPG
53
54config CLK_R8A7745
55 bool
56 select CLK_RCAR_GEN2_CPG
57
58config CLK_R8A7778
59 bool
60 select CLK_RENESAS_CPG_MSTP
61
62config CLK_R8A7779
63 bool
64 select CLK_RENESAS_CPG_MSTP
65
66config CLK_R8A7790
67 bool
Geert Uytterhoevend4e59f12017-03-19 18:05:42 +010068 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
69 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020070 select CLK_RENESAS_DIV6
71
72config CLK_R8A7791
73 bool
Geert Uytterhoeven6449ab82015-10-16 11:41:19 +020074 select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
75 select CLK_RCAR_GEN2_CPG
Geert Uytterhoeven80978a42017-04-24 16:54:14 +020076 select CLK_RENESAS_DIV6
77
78config CLK_R8A7792
79 bool
80 select CLK_RCAR_GEN2
81
82config CLK_R8A7794
83 bool
84 select CLK_RCAR_GEN2
85 select CLK_RENESAS_DIV6
86
87config CLK_R8A7795
88 bool
89 select CLK_RCAR_GEN3_CPG
90
91config CLK_R8A7796
92 bool
93 select CLK_RCAR_GEN3_CPG
94
95config CLK_SH73A0
96 bool
97 select CLK_RENESAS_CPG_MSTP
98 select CLK_RENESAS_DIV6
99
100
101# Family
102config CLK_RCAR_GEN2
103 bool
104 select CLK_RENESAS_CPG_MSTP
105 select CLK_RENESAS_DIV6
106
107config CLK_RCAR_GEN2_CPG
108 bool
109 select CLK_RENESAS_CPG_MSSR
110
111config CLK_RCAR_GEN3_CPG
112 bool
113 select CLK_RENESAS_CPG_MSSR
114
115
116# Generic
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200117config CLK_RENESAS_CPG_MSSR
118 bool
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200119 select CLK_RENESAS_DIV6
Geert Uytterhoevena5bd7f72016-04-13 11:08:42 +0200120
121config CLK_RENESAS_CPG_MSTP
122 bool
Geert Uytterhoeven80978a42017-04-24 16:54:14 +0200123
124config CLK_RENESAS_DIV6
125 bool "DIV6 clock support" if COMPILE_TEST
126
127endif # CLK_RENESAS