blob: 4e0abbd9d6553e71d6881b074196d62dea4ac04b [file] [log] [blame]
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +08001/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08004 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +08005 *
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08006 * Licensed under GPLv2.
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +08007 */
8
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +08009#include "at91sam9260.dtsi"
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +080010
11/ {
12 model = "Atmel AT91SAM9G20 family SoC";
13 compatible = "atmel,at91sam9g20";
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +080014
Ludovic Desrochesdcce6ce2012-04-02 20:44:20 +020015 memory {
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +080016 reg = <0x20000000 0x08000000>;
17 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +020018
19 ahb {
20 apb {
Ludovic Desroches05dcd362012-09-12 08:42:16 +020021 i2c0: i2c@fffac000 {
22 compatible = "atmel,at91sam9g20-i2c";
23 };
24
Nicolas Ferre73d68d92012-05-16 17:37:06 +020025 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>;
27 };
Alexandre Belloni09d773c2014-06-16 19:22:40 +020028
29 pmc: pmc@fffffc00 {
30 plla: pllack {
31 atmel,clk-input-range = <2000000 32000000>;
32 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
33 <695000000 750000000 1 0>,
34 <645000000 700000000 2 0>,
35 <595000000 650000000 3 0>,
36 <545000000 600000000 0 1>,
37 <495000000 550000000 1 1>,
38 <445000000 500000000 2 1>,
39 <400000000 450000000 3 1>;
40 };
41
42 pllb: pllbck {
Gaƫl PORTAY650ca012014-09-01 23:29:46 +020043 compatible = "atmel,at91sam9g20-clk-pllb";
Alexandre Belloni09d773c2014-06-16 19:22:40 +020044 atmel,clk-input-range = <2000000 32000000>;
45 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
46 };
47
48 mck: masterck {
49 atmel,clk-output-range = <0 133000000>;
50 atmel,clk-divisors = <1 2 4 6>;
51 };
52 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +020053 };
54 };
Jean-Christophe PLAGNIOL-VILLARDfea31582011-10-14 09:40:52 +080055};