Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * The OPP code in function cpu0_set_target() is reused from |
| 5 | * drivers/cpufreq/omap-cpufreq.c |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 13 | |
| 14 | #include <linux/clk.h> |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 15 | #include <linux/cpu.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 16 | #include <linux/cpufreq.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/of.h> |
Nishanth Menon | e4db1c7 | 2013-09-19 16:03:52 -0500 | [diff] [blame] | 20 | #include <linux/pm_opp.h> |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 21 | #include <linux/platform_device.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 22 | #include <linux/regulator/consumer.h> |
| 23 | #include <linux/slab.h> |
| 24 | |
| 25 | static unsigned int transition_latency; |
| 26 | static unsigned int voltage_tolerance; /* in percentage */ |
| 27 | |
| 28 | static struct device *cpu_dev; |
| 29 | static struct clk *cpu_clk; |
| 30 | static struct regulator *cpu_reg; |
| 31 | static struct cpufreq_frequency_table *freq_table; |
| 32 | |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 33 | static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 34 | { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 35 | struct dev_pm_opp *opp; |
jhbird.choi@samsung.com | 5df6055 | 2013-03-18 08:09:42 +0000 | [diff] [blame] | 36 | unsigned long volt = 0, volt_old = 0, tol = 0; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 37 | unsigned int old_freq, new_freq; |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 38 | long freq_Hz, freq_exact; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 39 | int ret; |
| 40 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 41 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
Paul Walmsley | 2209b0c | 2013-11-25 18:01:18 -0800 | [diff] [blame] | 42 | if (freq_Hz <= 0) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 43 | freq_Hz = freq_table[index].frequency * 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 44 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 45 | freq_exact = freq_Hz; |
| 46 | new_freq = freq_Hz / 1000; |
| 47 | old_freq = clk_get_rate(cpu_clk) / 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 48 | |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 49 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 50 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 51 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 52 | if (IS_ERR(opp)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 53 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 54 | pr_err("failed to find OPP for %ld\n", freq_Hz); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 55 | return PTR_ERR(opp); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 56 | } |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 57 | volt = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 58 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 59 | tol = volt * voltage_tolerance / 100; |
| 60 | volt_old = regulator_get_voltage(cpu_reg); |
| 61 | } |
| 62 | |
| 63 | pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 64 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
| 65 | new_freq / 1000, volt ? volt / 1000 : -1); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 66 | |
| 67 | /* scaling up? scale voltage before frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 68 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 69 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 70 | if (ret) { |
| 71 | pr_err("failed to scale voltage up: %d\n", ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 72 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 73 | } |
| 74 | } |
| 75 | |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 76 | ret = clk_set_rate(cpu_clk, freq_exact); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 77 | if (ret) { |
| 78 | pr_err("failed to set clock rate: %d\n", ret); |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 79 | if (!IS_ERR(cpu_reg)) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 80 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 81 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | /* scaling down? scale voltage after frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 85 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 86 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 87 | if (ret) { |
| 88 | pr_err("failed to scale voltage down: %d\n", ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 89 | clk_set_rate(cpu_clk, old_freq * 1000); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 90 | } |
| 91 | } |
| 92 | |
Viresh Kumar | fd143b4 | 2013-04-01 12:57:44 +0000 | [diff] [blame] | 93 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 94 | } |
| 95 | |
| 96 | static int cpu0_cpufreq_init(struct cpufreq_policy *policy) |
| 97 | { |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame^] | 98 | policy->clk = cpu_clk; |
Viresh Kumar | 78b3d10 | 2013-10-03 20:29:09 +0530 | [diff] [blame] | 99 | return cpufreq_generic_init(policy, freq_table, transition_latency); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 100 | } |
| 101 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 102 | static struct cpufreq_driver cpu0_cpufreq_driver = { |
| 103 | .flags = CPUFREQ_STICKY, |
Viresh Kumar | f793d79 | 2013-10-03 20:28:00 +0530 | [diff] [blame] | 104 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 105 | .target_index = cpu0_set_target, |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame^] | 106 | .get = cpufreq_generic_get, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 107 | .init = cpu0_cpufreq_init, |
Viresh Kumar | f793d79 | 2013-10-03 20:28:00 +0530 | [diff] [blame] | 108 | .exit = cpufreq_generic_exit, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 109 | .name = "generic_cpu0", |
Viresh Kumar | f793d79 | 2013-10-03 20:28:00 +0530 | [diff] [blame] | 110 | .attr = cpufreq_generic_attr, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 111 | }; |
| 112 | |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 113 | static int cpu0_cpufreq_probe(struct platform_device *pdev) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 114 | { |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 115 | struct device_node *np; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 116 | int ret; |
| 117 | |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 118 | cpu_dev = get_cpu_device(0); |
| 119 | if (!cpu_dev) { |
| 120 | pr_err("failed to get cpu0 device\n"); |
| 121 | return -ENODEV; |
| 122 | } |
Paolo Pisati | f5c3ef2 | 2013-03-28 09:24:29 +0000 | [diff] [blame] | 123 | |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 124 | np = of_node_get(cpu_dev->of_node); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 125 | if (!np) { |
| 126 | pr_err("failed to find cpu0 node\n"); |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 127 | return -ENOENT; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 128 | } |
| 129 | |
Mark Brown | 7d74897 | 2013-08-09 19:07:12 +0100 | [diff] [blame] | 130 | cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0"); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 131 | if (IS_ERR(cpu_reg)) { |
| 132 | /* |
| 133 | * If cpu0 regulator supply node is present, but regulator is |
| 134 | * not yet registered, we should try defering probe. |
| 135 | */ |
| 136 | if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { |
| 137 | dev_err(cpu_dev, "cpu0 regulator not ready, retry\n"); |
| 138 | ret = -EPROBE_DEFER; |
| 139 | goto out_put_node; |
| 140 | } |
| 141 | pr_warn("failed to get cpu0 regulator: %ld\n", |
| 142 | PTR_ERR(cpu_reg)); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 143 | } |
| 144 | |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 145 | cpu_clk = devm_clk_get(cpu_dev, NULL); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 146 | if (IS_ERR(cpu_clk)) { |
| 147 | ret = PTR_ERR(cpu_clk); |
| 148 | pr_err("failed to get cpu0 clock: %d\n", ret); |
| 149 | goto out_put_node; |
| 150 | } |
| 151 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 152 | ret = of_init_opp_table(cpu_dev); |
| 153 | if (ret) { |
| 154 | pr_err("failed to init OPP table: %d\n", ret); |
| 155 | goto out_put_node; |
| 156 | } |
| 157 | |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 158 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 159 | if (ret) { |
| 160 | pr_err("failed to init cpufreq table: %d\n", ret); |
| 161 | goto out_put_node; |
| 162 | } |
| 163 | |
| 164 | of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); |
| 165 | |
| 166 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) |
| 167 | transition_latency = CPUFREQ_ETERNAL; |
| 168 | |
Philipp Zabel | 43c638e | 2013-09-26 11:19:37 +0200 | [diff] [blame] | 169 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 170 | struct dev_pm_opp *opp; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 171 | unsigned long min_uV, max_uV; |
| 172 | int i; |
| 173 | |
| 174 | /* |
| 175 | * OPP is maintained in order of increasing frequency, and |
| 176 | * freq_table initialised from OPP is therefore sorted in the |
| 177 | * same order. |
| 178 | */ |
| 179 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) |
| 180 | ; |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 181 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 182 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 183 | freq_table[0].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 184 | min_uV = dev_pm_opp_get_voltage(opp); |
| 185 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 186 | freq_table[i-1].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 187 | max_uV = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 188 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 189 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
| 190 | if (ret > 0) |
| 191 | transition_latency += ret * 1000; |
| 192 | } |
| 193 | |
| 194 | ret = cpufreq_register_driver(&cpu0_cpufreq_driver); |
| 195 | if (ret) { |
| 196 | pr_err("failed register driver: %d\n", ret); |
| 197 | goto out_free_table; |
| 198 | } |
| 199 | |
| 200 | of_node_put(np); |
| 201 | return 0; |
| 202 | |
| 203 | out_free_table: |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 204 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 205 | out_put_node: |
| 206 | of_node_put(np); |
| 207 | return ret; |
| 208 | } |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 209 | |
| 210 | static int cpu0_cpufreq_remove(struct platform_device *pdev) |
| 211 | { |
| 212 | cpufreq_unregister_driver(&cpu0_cpufreq_driver); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 213 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 214 | |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | static struct platform_driver cpu0_cpufreq_platdrv = { |
| 219 | .driver = { |
| 220 | .name = "cpufreq-cpu0", |
| 221 | .owner = THIS_MODULE, |
| 222 | }, |
| 223 | .probe = cpu0_cpufreq_probe, |
| 224 | .remove = cpu0_cpufreq_remove, |
| 225 | }; |
| 226 | module_platform_driver(cpu0_cpufreq_platdrv); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 227 | |
| 228 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
| 229 | MODULE_DESCRIPTION("Generic CPU0 cpufreq driver"); |
| 230 | MODULE_LICENSE("GPL"); |