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Russell King96f60e32012-08-15 13:59:49 +01001/*
2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <drm/drmP.h>
Russell King98fb74f2015-06-15 10:17:57 +010010#include <drm/drm_plane_helper.h>
Russell King96f60e32012-08-15 13:59:49 +010011#include "armada_crtc.h"
12#include "armada_drm.h"
13#include "armada_fb.h"
14#include "armada_gem.h"
15#include "armada_hw.h"
16#include <drm/armada_drm.h>
17#include "armada_ioctlP.h"
18
Russell King28a2aeb2015-07-15 18:11:23 +010019struct armada_ovl_plane_properties {
Russell King96f60e32012-08-15 13:59:49 +010020 uint32_t colorkey_yr;
21 uint32_t colorkey_ug;
22 uint32_t colorkey_vb;
23#define K2R(val) (((val) >> 0) & 0xff)
24#define K2G(val) (((val) >> 8) & 0xff)
25#define K2B(val) (((val) >> 16) & 0xff)
26 int16_t brightness;
27 uint16_t contrast;
28 uint16_t saturation;
29 uint32_t colorkey_mode;
30};
31
Russell King28a2aeb2015-07-15 18:11:23 +010032struct armada_ovl_plane {
Russell King96f60e32012-08-15 13:59:49 +010033 struct drm_plane base;
Russell King96f60e32012-08-15 13:59:49 +010034 struct drm_framebuffer *old_fb;
35 uint32_t src_hw;
36 uint32_t dst_hw;
37 uint32_t dst_yx;
38 uint32_t ctrl0;
39 struct {
40 struct armada_vbl_event update;
41 struct armada_regs regs[13];
42 wait_queue_head_t wait;
43 } vbl;
Russell King28a2aeb2015-07-15 18:11:23 +010044 struct armada_ovl_plane_properties prop;
Russell King96f60e32012-08-15 13:59:49 +010045};
Russell King28a2aeb2015-07-15 18:11:23 +010046#define drm_to_armada_ovl_plane(p) container_of(p, struct armada_ovl_plane, base)
Russell King96f60e32012-08-15 13:59:49 +010047
48
49static void
Russell King28a2aeb2015-07-15 18:11:23 +010050armada_ovl_update_attr(struct armada_ovl_plane_properties *prop,
Russell King96f60e32012-08-15 13:59:49 +010051 struct armada_crtc *dcrtc)
52{
53 writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
54 writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
55 writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
56
57 writel_relaxed(prop->brightness << 16 | prop->contrast,
58 dcrtc->base + LCD_SPU_CONTRAST);
59 /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
60 writel_relaxed(prop->saturation << 16,
61 dcrtc->base + LCD_SPU_SATURATION);
62 writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
63
64 spin_lock_irq(&dcrtc->irq_lock);
65 armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
66 CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
67 dcrtc->base + LCD_SPU_DMA_CTRL1);
68
69 armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
70 spin_unlock_irq(&dcrtc->irq_lock);
71}
72
Russell Kingfecfdb22015-07-15 18:11:24 +010073static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane,
74 struct drm_framebuffer *fb)
75{
76 struct drm_framebuffer *old_fb;
77
Russell King66377ef2015-07-15 18:11:24 +010078 old_fb = xchg(&dplane->old_fb, fb);
Russell Kingfecfdb22015-07-15 18:11:24 +010079
80 if (old_fb)
81 armada_drm_queue_unref_work(dplane->base.dev, old_fb);
82}
83
Russell King96f60e32012-08-15 13:59:49 +010084/* === Plane support === */
Russell King28a2aeb2015-07-15 18:11:23 +010085static void armada_ovl_plane_vbl(struct armada_crtc *dcrtc, void *data)
Russell King96f60e32012-08-15 13:59:49 +010086{
Russell King28a2aeb2015-07-15 18:11:23 +010087 struct armada_ovl_plane *dplane = data;
Russell King96f60e32012-08-15 13:59:49 +010088
89 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
Russell Kingfecfdb22015-07-15 18:11:24 +010090 armada_ovl_retire_fb(dplane, NULL);
Russell King070f3f62015-06-15 10:13:29 +010091
92 wake_up(&dplane->vbl.wait);
Russell King96f60e32012-08-15 13:59:49 +010093}
94
Russell King96f60e32012-08-15 13:59:49 +010095static int
Russell King28a2aeb2015-07-15 18:11:23 +010096armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
Russell King96f60e32012-08-15 13:59:49 +010097 struct drm_framebuffer *fb,
98 int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
99 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
100{
Russell King28a2aeb2015-07-15 18:11:23 +0100101 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100102 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
Russell King98fb74f2015-06-15 10:17:57 +0100103 struct drm_rect src = {
104 .x1 = src_x,
105 .y1 = src_y,
106 .x2 = src_x + src_w,
107 .y2 = src_y + src_h,
108 };
109 struct drm_rect dest = {
110 .x1 = crtc_x,
111 .y1 = crtc_y,
112 .x2 = crtc_x + crtc_w,
113 .y2 = crtc_y + crtc_h,
114 };
115 const struct drm_rect clip = {
116 .x2 = crtc->mode.hdisplay,
117 .y2 = crtc->mode.vdisplay,
118 };
Russell King96f60e32012-08-15 13:59:49 +0100119 uint32_t val, ctrl0;
120 unsigned idx = 0;
Russell King98fb74f2015-06-15 10:17:57 +0100121 bool visible;
Russell King96f60e32012-08-15 13:59:49 +0100122 int ret;
123
Russell King98fb74f2015-06-15 10:17:57 +0100124 ret = drm_plane_helper_check_update(plane, crtc, fb, &src, &dest, &clip,
125 0, INT_MAX, true, false, &visible);
126 if (ret)
127 return ret;
128
Russell King96f60e32012-08-15 13:59:49 +0100129 ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
130 CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
131 CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
132
133 /* Does the position/size result in nothing to display? */
Russell King98fb74f2015-06-15 10:17:57 +0100134 if (!visible)
Russell King96f60e32012-08-15 13:59:49 +0100135 ctrl0 &= ~CFG_DMA_ENA;
Russell King96f60e32012-08-15 13:59:49 +0100136
137 if (!dcrtc->plane) {
138 dcrtc->plane = plane;
139 armada_ovl_update_attr(&dplane->prop, dcrtc);
140 }
141
142 /* FIXME: overlay on an interlaced display */
143 /* Just updating the position/size? */
144 if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
Russell King98fb74f2015-06-15 10:17:57 +0100145 val = (drm_rect_height(&src) & 0xffff0000) |
146 drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100147 dplane->src_hw = val;
148 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100149
150 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100151 dplane->dst_hw = val;
152 writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100153
154 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100155 dplane->dst_yx = val;
156 writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
Russell King98fb74f2015-06-15 10:17:57 +0100157
Russell King96f60e32012-08-15 13:59:49 +0100158 return 0;
159 } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
160 /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
161 armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
162 dcrtc->base + LCD_SPU_SRAM_PARA1);
163 }
164
Russell King070f3f62015-06-15 10:13:29 +0100165 wait_event_timeout(dplane->vbl.wait,
166 list_empty(&dplane->vbl.update.node),
167 HZ/25);
Russell King96f60e32012-08-15 13:59:49 +0100168
169 if (plane->fb != fb) {
170 struct armada_gem_object *obj = drm_fb_obj(fb);
Russell King73068ce2015-06-15 10:18:02 +0100171 uint32_t addr[3], pixel_format;
172 int i, num_planes, hsub;
Russell King96f60e32012-08-15 13:59:49 +0100173
174 /*
175 * Take a reference on the new framebuffer - we want to
176 * hold on to it while the hardware is displaying it.
177 */
178 drm_framebuffer_reference(fb);
179
Russell Kingfecfdb22015-07-15 18:11:24 +0100180 if (plane->fb)
181 armada_ovl_retire_fb(dplane, plane->fb);
Russell King96f60e32012-08-15 13:59:49 +0100182
Russell King98fb74f2015-06-15 10:17:57 +0100183 src_y = src.y1 >> 16;
184 src_x = src.x1 >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100185
Russell King73068ce2015-06-15 10:18:02 +0100186 pixel_format = fb->pixel_format;
187 hsub = drm_format_horz_chroma_subsampling(pixel_format);
188 num_planes = drm_format_num_planes(pixel_format);
189
190 /*
191 * Annoyingly, shifting a YUYV-format image by one pixel
192 * causes the U/V planes to toggle. Toggle the UV swap.
193 * (Unfortunately, this causes momentary colour flickering.)
194 */
195 if (src_x & (hsub - 1) && num_planes == 1)
196 ctrl0 ^= CFG_DMA_MOD(CFG_SWAPUV);
197
198 for (i = 0; i < num_planes; i++)
199 addr[i] = obj->dev_addr + fb->offsets[i] +
200 src_y * fb->pitches[i] +
201 src_x * drm_format_plane_cpp(pixel_format, i);
202 for (; i < ARRAY_SIZE(addr); i++)
203 addr[i] = 0;
204
205 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100206 LCD_SPU_DMA_START_ADDR_Y0);
Russell King73068ce2015-06-15 10:18:02 +0100207 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100208 LCD_SPU_DMA_START_ADDR_U0);
Russell King73068ce2015-06-15 10:18:02 +0100209 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100210 LCD_SPU_DMA_START_ADDR_V0);
Russell King73068ce2015-06-15 10:18:02 +0100211 armada_reg_queue_set(dplane->vbl.regs, idx, addr[0],
Russell King96f60e32012-08-15 13:59:49 +0100212 LCD_SPU_DMA_START_ADDR_Y1);
Russell King73068ce2015-06-15 10:18:02 +0100213 armada_reg_queue_set(dplane->vbl.regs, idx, addr[1],
Russell King96f60e32012-08-15 13:59:49 +0100214 LCD_SPU_DMA_START_ADDR_U1);
Russell King73068ce2015-06-15 10:18:02 +0100215 armada_reg_queue_set(dplane->vbl.regs, idx, addr[2],
Russell King96f60e32012-08-15 13:59:49 +0100216 LCD_SPU_DMA_START_ADDR_V1);
217
218 val = fb->pitches[0] << 16 | fb->pitches[0];
219 armada_reg_queue_set(dplane->vbl.regs, idx, val,
220 LCD_SPU_DMA_PITCH_YC);
221 val = fb->pitches[1] << 16 | fb->pitches[2];
222 armada_reg_queue_set(dplane->vbl.regs, idx, val,
223 LCD_SPU_DMA_PITCH_UV);
224 }
225
Russell King98fb74f2015-06-15 10:17:57 +0100226 val = (drm_rect_height(&src) & 0xffff0000) | drm_rect_width(&src) >> 16;
Russell King96f60e32012-08-15 13:59:49 +0100227 if (dplane->src_hw != val) {
228 dplane->src_hw = val;
229 armada_reg_queue_set(dplane->vbl.regs, idx, val,
230 LCD_SPU_DMA_HPXL_VLN);
231 }
Russell King98fb74f2015-06-15 10:17:57 +0100232
233 val = drm_rect_height(&dest) << 16 | drm_rect_width(&dest);
Russell King96f60e32012-08-15 13:59:49 +0100234 if (dplane->dst_hw != val) {
235 dplane->dst_hw = val;
236 armada_reg_queue_set(dplane->vbl.regs, idx, val,
237 LCD_SPU_DZM_HPXL_VLN);
238 }
Russell King98fb74f2015-06-15 10:17:57 +0100239
240 val = dest.y1 << 16 | dest.x1;
Russell King96f60e32012-08-15 13:59:49 +0100241 if (dplane->dst_yx != val) {
242 dplane->dst_yx = val;
243 armada_reg_queue_set(dplane->vbl.regs, idx, val,
244 LCD_SPU_DMA_OVSA_HPXL_VLN);
245 }
Russell King98fb74f2015-06-15 10:17:57 +0100246
Russell King96f60e32012-08-15 13:59:49 +0100247 if (dplane->ctrl0 != ctrl0) {
248 dplane->ctrl0 = ctrl0;
249 armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
250 CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
251 CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
252 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
253 CFG_YUV2RGB) | CFG_DMA_ENA,
254 LCD_SPU_DMA_CTRL0);
255 }
256 if (idx) {
257 armada_reg_queue_end(dplane->vbl.regs, idx);
258 armada_drm_vbl_event_add(dcrtc, &dplane->vbl.update);
259 }
260 return 0;
261}
262
Russell King28a2aeb2015-07-15 18:11:23 +0100263static int armada_ovl_plane_disable(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100264{
Russell King28a2aeb2015-07-15 18:11:23 +0100265 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100266 struct drm_framebuffer *fb;
267 struct armada_crtc *dcrtc;
268
269 if (!dplane->base.crtc)
270 return 0;
271
272 dcrtc = drm_to_armada_crtc(dplane->base.crtc);
273 dcrtc->plane = NULL;
274
275 spin_lock_irq(&dcrtc->irq_lock);
276 armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
277 armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
278 dplane->ctrl0 = 0;
279 spin_unlock_irq(&dcrtc->irq_lock);
280
281 /* Power down the Y/U/V FIFOs */
282 armada_updatel(CFG_PDWN16x66 | CFG_PDWN32x66, 0,
283 dcrtc->base + LCD_SPU_SRAM_PARA1);
284
285 if (plane->fb)
286 drm_framebuffer_unreference(plane->fb);
287
Russell King66377ef2015-07-15 18:11:24 +0100288 fb = xchg(&dplane->old_fb, NULL);
Russell King96f60e32012-08-15 13:59:49 +0100289 if (fb)
290 drm_framebuffer_unreference(fb);
291
292 return 0;
293}
294
Russell King28a2aeb2015-07-15 18:11:23 +0100295static void armada_ovl_plane_destroy(struct drm_plane *plane)
Russell King96f60e32012-08-15 13:59:49 +0100296{
Russell King28a2aeb2015-07-15 18:11:23 +0100297 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King41dbb2d2015-06-15 10:13:30 +0100298
299 drm_plane_cleanup(plane);
300
301 kfree(dplane);
Russell King96f60e32012-08-15 13:59:49 +0100302}
303
Russell King28a2aeb2015-07-15 18:11:23 +0100304static int armada_ovl_plane_set_property(struct drm_plane *plane,
Russell King96f60e32012-08-15 13:59:49 +0100305 struct drm_property *property, uint64_t val)
306{
307 struct armada_private *priv = plane->dev->dev_private;
Russell King28a2aeb2015-07-15 18:11:23 +0100308 struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane);
Russell King96f60e32012-08-15 13:59:49 +0100309 bool update_attr = false;
310
311 if (property == priv->colorkey_prop) {
312#define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
313 dplane->prop.colorkey_yr = CCC(K2R(val));
314 dplane->prop.colorkey_ug = CCC(K2G(val));
315 dplane->prop.colorkey_vb = CCC(K2B(val));
316#undef CCC
317 update_attr = true;
318 } else if (property == priv->colorkey_min_prop) {
319 dplane->prop.colorkey_yr &= ~0x00ff0000;
320 dplane->prop.colorkey_yr |= K2R(val) << 16;
321 dplane->prop.colorkey_ug &= ~0x00ff0000;
322 dplane->prop.colorkey_ug |= K2G(val) << 16;
323 dplane->prop.colorkey_vb &= ~0x00ff0000;
324 dplane->prop.colorkey_vb |= K2B(val) << 16;
325 update_attr = true;
326 } else if (property == priv->colorkey_max_prop) {
327 dplane->prop.colorkey_yr &= ~0xff000000;
328 dplane->prop.colorkey_yr |= K2R(val) << 24;
329 dplane->prop.colorkey_ug &= ~0xff000000;
330 dplane->prop.colorkey_ug |= K2G(val) << 24;
331 dplane->prop.colorkey_vb &= ~0xff000000;
332 dplane->prop.colorkey_vb |= K2B(val) << 24;
333 update_attr = true;
334 } else if (property == priv->colorkey_val_prop) {
335 dplane->prop.colorkey_yr &= ~0x0000ff00;
336 dplane->prop.colorkey_yr |= K2R(val) << 8;
337 dplane->prop.colorkey_ug &= ~0x0000ff00;
338 dplane->prop.colorkey_ug |= K2G(val) << 8;
339 dplane->prop.colorkey_vb &= ~0x0000ff00;
340 dplane->prop.colorkey_vb |= K2B(val) << 8;
341 update_attr = true;
342 } else if (property == priv->colorkey_alpha_prop) {
343 dplane->prop.colorkey_yr &= ~0x000000ff;
344 dplane->prop.colorkey_yr |= K2R(val);
345 dplane->prop.colorkey_ug &= ~0x000000ff;
346 dplane->prop.colorkey_ug |= K2G(val);
347 dplane->prop.colorkey_vb &= ~0x000000ff;
348 dplane->prop.colorkey_vb |= K2B(val);
349 update_attr = true;
350 } else if (property == priv->colorkey_mode_prop) {
351 dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
352 dplane->prop.colorkey_mode |= CFG_CKMODE(val);
353 update_attr = true;
354 } else if (property == priv->brightness_prop) {
355 dplane->prop.brightness = val - 256;
356 update_attr = true;
357 } else if (property == priv->contrast_prop) {
358 dplane->prop.contrast = val;
359 update_attr = true;
360 } else if (property == priv->saturation_prop) {
361 dplane->prop.saturation = val;
362 update_attr = true;
363 }
364
365 if (update_attr && dplane->base.crtc)
366 armada_ovl_update_attr(&dplane->prop,
367 drm_to_armada_crtc(dplane->base.crtc));
368
369 return 0;
370}
371
Russell King28a2aeb2015-07-15 18:11:23 +0100372static const struct drm_plane_funcs armada_ovl_plane_funcs = {
373 .update_plane = armada_ovl_plane_update,
374 .disable_plane = armada_ovl_plane_disable,
375 .destroy = armada_ovl_plane_destroy,
376 .set_property = armada_ovl_plane_set_property,
Russell King96f60e32012-08-15 13:59:49 +0100377};
378
Russell King28a2aeb2015-07-15 18:11:23 +0100379static const uint32_t armada_ovl_formats[] = {
Russell King96f60e32012-08-15 13:59:49 +0100380 DRM_FORMAT_UYVY,
381 DRM_FORMAT_YUYV,
382 DRM_FORMAT_YUV420,
383 DRM_FORMAT_YVU420,
384 DRM_FORMAT_YUV422,
385 DRM_FORMAT_YVU422,
386 DRM_FORMAT_VYUY,
387 DRM_FORMAT_YVYU,
388 DRM_FORMAT_ARGB8888,
389 DRM_FORMAT_ABGR8888,
390 DRM_FORMAT_XRGB8888,
391 DRM_FORMAT_XBGR8888,
392 DRM_FORMAT_RGB888,
393 DRM_FORMAT_BGR888,
394 DRM_FORMAT_ARGB1555,
395 DRM_FORMAT_ABGR1555,
396 DRM_FORMAT_RGB565,
397 DRM_FORMAT_BGR565,
398};
399
400static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
401 { CKMODE_DISABLE, "disabled" },
402 { CKMODE_Y, "Y component" },
403 { CKMODE_U, "U component" },
404 { CKMODE_V, "V component" },
405 { CKMODE_RGB, "RGB" },
406 { CKMODE_R, "R component" },
407 { CKMODE_G, "G component" },
408 { CKMODE_B, "B component" },
409};
410
411static int armada_overlay_create_properties(struct drm_device *dev)
412{
413 struct armada_private *priv = dev->dev_private;
414
415 if (priv->colorkey_prop)
416 return 0;
417
418 priv->colorkey_prop = drm_property_create_range(dev, 0,
419 "colorkey", 0, 0xffffff);
420 priv->colorkey_min_prop = drm_property_create_range(dev, 0,
421 "colorkey_min", 0, 0xffffff);
422 priv->colorkey_max_prop = drm_property_create_range(dev, 0,
423 "colorkey_max", 0, 0xffffff);
424 priv->colorkey_val_prop = drm_property_create_range(dev, 0,
425 "colorkey_val", 0, 0xffffff);
426 priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
427 "colorkey_alpha", 0, 0xffffff);
428 priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
429 "colorkey_mode",
430 armada_drm_colorkey_enum_list,
431 ARRAY_SIZE(armada_drm_colorkey_enum_list));
432 priv->brightness_prop = drm_property_create_range(dev, 0,
433 "brightness", 0, 256 + 255);
434 priv->contrast_prop = drm_property_create_range(dev, 0,
435 "contrast", 0, 0x7fff);
436 priv->saturation_prop = drm_property_create_range(dev, 0,
437 "saturation", 0, 0x7fff);
438
439 if (!priv->colorkey_prop)
440 return -ENOMEM;
441
442 return 0;
443}
444
445int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
446{
447 struct armada_private *priv = dev->dev_private;
448 struct drm_mode_object *mobj;
Russell King28a2aeb2015-07-15 18:11:23 +0100449 struct armada_ovl_plane *dplane;
Russell King96f60e32012-08-15 13:59:49 +0100450 int ret;
451
452 ret = armada_overlay_create_properties(dev);
453 if (ret)
454 return ret;
455
456 dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
457 if (!dplane)
458 return -ENOMEM;
459
Russell King96f60e32012-08-15 13:59:49 +0100460 init_waitqueue_head(&dplane->vbl.wait);
Russell King28a2aeb2015-07-15 18:11:23 +0100461 armada_drm_vbl_event_init(&dplane->vbl.update, armada_ovl_plane_vbl,
Russell King96f60e32012-08-15 13:59:49 +0100462 dplane);
463
Russell King28a2aeb2015-07-15 18:11:23 +0100464 drm_plane_init(dev, &dplane->base, crtcs, &armada_ovl_plane_funcs,
465 armada_ovl_formats, ARRAY_SIZE(armada_ovl_formats),
466 false);
467 if (ret) {
468 kfree(dplane);
469 return ret;
470 }
Russell King96f60e32012-08-15 13:59:49 +0100471
472 dplane->prop.colorkey_yr = 0xfefefe00;
473 dplane->prop.colorkey_ug = 0x01010100;
474 dplane->prop.colorkey_vb = 0x01010100;
475 dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
476 dplane->prop.brightness = 0;
477 dplane->prop.contrast = 0x4000;
478 dplane->prop.saturation = 0x4000;
479
480 mobj = &dplane->base.base;
481 drm_object_attach_property(mobj, priv->colorkey_prop,
482 0x0101fe);
483 drm_object_attach_property(mobj, priv->colorkey_min_prop,
484 0x0101fe);
485 drm_object_attach_property(mobj, priv->colorkey_max_prop,
486 0x0101fe);
487 drm_object_attach_property(mobj, priv->colorkey_val_prop,
488 0x0101fe);
489 drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
490 0x000000);
491 drm_object_attach_property(mobj, priv->colorkey_mode_prop,
492 CKMODE_RGB);
493 drm_object_attach_property(mobj, priv->brightness_prop, 256);
494 drm_object_attach_property(mobj, priv->contrast_prop,
495 dplane->prop.contrast);
496 drm_object_attach_property(mobj, priv->saturation_prop,
497 dplane->prop.saturation);
498
499 return 0;
500}