blob: 042a8903bdb1b9985952b36402e106bdef66d09f [file] [log] [blame]
Kumar Galaf335b8a2014-04-03 14:48:22 -05001/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
Srinivas Kandagatla223280b2015-04-10 21:43:30 +01005#include <dt-bindings/reset/qcom,gcc-msm8960.h>
Stephen Boyd3fe5e3c2014-07-16 13:49:43 -07006#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
Kumar Galaf335b8a2014-04-03 14:48:22 -05007#include <dt-bindings/soc/qcom,gsbi.h>
Pramod Gurav8b8936f2014-08-29 20:00:56 +05308#include <dt-bindings/interrupt-controller/arm-gic.h>
Kumar Galaf335b8a2014-04-03 14:48:22 -05009/ {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
13
Bjorn Andersson24a9baf2015-10-22 11:13:48 -070014 reserved-memory {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
21 no-map;
22 };
23 };
24
Kumar Galaf335b8a2014-04-03 14:48:22 -050025 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc0>;
36 qcom,saw = <&saw0>;
Lina Iyer06c49f22015-03-25 14:25:35 -060037 cpu-idle-states = <&CPU_SPC>;
Kumar Galaf335b8a2014-04-03 14:48:22 -050038 };
39
40 cpu@1 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc1>;
47 qcom,saw = <&saw1>;
Lina Iyer06c49f22015-03-25 14:25:35 -060048 cpu-idle-states = <&CPU_SPC>;
Kumar Galaf335b8a2014-04-03 14:48:22 -050049 };
50
51 cpu@2 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc2>;
58 qcom,saw = <&saw2>;
Lina Iyer06c49f22015-03-25 14:25:35 -060059 cpu-idle-states = <&CPU_SPC>;
Kumar Galaf335b8a2014-04-03 14:48:22 -050060 };
61
62 cpu@3 {
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2>;
68 qcom,acc = <&acc3>;
69 qcom,saw = <&saw3>;
Lina Iyer06c49f22015-03-25 14:25:35 -060070 cpu-idle-states = <&CPU_SPC>;
Kumar Galaf335b8a2014-04-03 14:48:22 -050071 };
72
73 L2: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 };
Lina Iyer06c49f22015-03-25 14:25:35 -060077
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
85 };
86 };
Kumar Galaf335b8a2014-04-03 14:48:22 -050087 };
88
89 cpu-pmu {
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
92 };
93
Georgi Djakovaa269122015-12-03 16:02:55 +020094 clocks {
95 cxo_board {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <19200000>;
99 };
100
101 pxo_board {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <27000000>;
105 };
106
107 sleep_clk {
108 compatible = "fixed-clock";
109 #clock-cells = <0>;
110 clock-frequency = <32768>;
111 };
112 };
113
Bjorn Andersson24a9baf2015-10-22 11:13:48 -0700114 sfpb_mutex: hwmutex {
115 compatible = "qcom,sfpb-mutex";
116 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
117 #hwlock-cells = <1>;
118 };
119
120 smem {
121 compatible = "qcom,smem";
122 memory-region = <&smem_region>;
123
124 hwlocks = <&sfpb_mutex 3>;
125 };
126
Bjorn Andersson2afc5282016-03-28 20:37:04 -0700127 smd {
128 compatible = "qcom,smd";
129
130 modem@0 {
131 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
132
133 qcom,ipc = <&l2cc 8 3>;
134 qcom,smd-edge = <0>;
135
136 status = "disabled";
137 };
138
139 q6@1 {
140 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
141
142 qcom,ipc = <&l2cc 8 15>;
143 qcom,smd-edge = <1>;
144
145 status = "disabled";
146 };
147
148 dsps@3 {
149 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
150
151 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
152 qcom,smd-edge = <3>;
153
154 status = "disabled";
155 };
156
157 riva@6 {
158 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
159
160 qcom,ipc = <&l2cc 8 25>;
161 qcom,smd-edge = <6>;
162
163 status = "disabled";
164 };
165 };
166
Bjorn Anderssonb4d45822016-03-28 20:37:03 -0700167 smsm {
168 compatible = "qcom,smsm";
169
170 #address-cells = <1>;
171 #size-cells = <0>;
172
173 qcom,ipc-1 = <&l2cc 8 4>;
174 qcom,ipc-2 = <&l2cc 8 14>;
175 qcom,ipc-3 = <&l2cc 8 23>;
176 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
177
178 apps_smsm: apps@0 {
179 reg = <0>;
180 #qcom,state-cells = <1>;
181 };
182
183 modem_smsm: modem@1 {
184 reg = <1>;
185 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
186
187 interrupt-controller;
188 #interrupt-cells = <2>;
189 };
190
191 q6_smsm: q6@2 {
192 reg = <2>;
193 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
194
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 wcnss_smsm: wcnss@3 {
200 reg = <3>;
201 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
202
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 dsps_smsm: dsps@4 {
208 reg = <4>;
209 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
210
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 };
214 };
215
Kumar Galaf335b8a2014-04-03 14:48:22 -0500216 soc: soc {
217 #address-cells = <1>;
218 #size-cells = <1>;
219 ranges;
220 compatible = "simple-bus";
221
Pramod Gurav8b8936f2014-08-29 20:00:56 +0530222 tlmm_pinmux: pinctrl@800000 {
223 compatible = "qcom,apq8064-pinctrl";
224 reg = <0x800000 0x4000>;
225
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
Pramod Guravcd6dd112014-08-29 20:00:57 +0530231
232 pinctrl-names = "default";
233 pinctrl-0 = <&ps_hold>;
Pramod Gurav8b8936f2014-08-29 20:00:56 +0530234 };
235
Bjorn Andersson24a9baf2015-10-22 11:13:48 -0700236 sfpb_wrapper_mutex: syscon@1200000 {
237 compatible = "syscon";
238 reg = <0x01200000 0x8000>;
239 };
240
Kumar Galaf335b8a2014-04-03 14:48:22 -0500241 intc: interrupt-controller@2000000 {
242 compatible = "qcom,msm-qgic2";
243 interrupt-controller;
244 #interrupt-cells = <3>;
245 reg = <0x02000000 0x1000>,
246 <0x02002000 0x1000>;
247 };
248
249 timer@200a000 {
250 compatible = "qcom,kpss-timer", "qcom,msm-timer";
251 interrupts = <1 1 0x301>,
252 <1 2 0x301>,
253 <1 3 0x301>;
254 reg = <0x0200a000 0x100>;
255 clock-frequency = <27000000>,
256 <32768>;
257 cpu-offset = <0x80000>;
258 };
259
260 acc0: clock-controller@2088000 {
261 compatible = "qcom,kpss-acc-v1";
262 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
263 };
264
265 acc1: clock-controller@2098000 {
266 compatible = "qcom,kpss-acc-v1";
267 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
268 };
269
270 acc2: clock-controller@20a8000 {
271 compatible = "qcom,kpss-acc-v1";
272 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
273 };
274
275 acc3: clock-controller@20b8000 {
276 compatible = "qcom,kpss-acc-v1";
277 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
278 };
279
Lina Iyer9fc23ce2015-03-25 14:25:32 -0600280 saw0: power-controller@2089000 {
281 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
Kumar Galaf335b8a2014-04-03 14:48:22 -0500282 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
283 regulator;
284 };
285
Lina Iyer9fc23ce2015-03-25 14:25:32 -0600286 saw1: power-controller@2099000 {
287 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
Kumar Galaf335b8a2014-04-03 14:48:22 -0500288 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
289 regulator;
290 };
291
Lina Iyer9fc23ce2015-03-25 14:25:32 -0600292 saw2: power-controller@20a9000 {
293 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
Kumar Galaf335b8a2014-04-03 14:48:22 -0500294 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
295 regulator;
296 };
297
Lina Iyer9fc23ce2015-03-25 14:25:32 -0600298 saw3: power-controller@20b9000 {
299 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
Kumar Galaf335b8a2014-04-03 14:48:22 -0500300 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
301 regulator;
302 };
303
Bjorn Anderssonb9e4c5e2016-03-28 20:37:02 -0700304 sps_sic_non_secure: sps-sic-non-secure@12100000 {
305 compatible = "syscon";
306 reg = <0x12100000 0x10000>;
307 };
308
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530309 gsbi1: gsbi@12440000 {
310 status = "disabled";
311 compatible = "qcom,gsbi-v1.0.0";
Andy Gross4105d9d2015-02-09 16:01:08 -0600312 cell-index = <1>;
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530313 reg = <0x12440000 0x100>;
314 clocks = <&gcc GSBI1_H_CLK>;
315 clock-names = "iface";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges;
319
Andy Gross4105d9d2015-02-09 16:01:08 -0600320 syscon-tcsr = <&tcsr>;
321
Srinivas Kandagatlae07214d2016-02-23 14:11:10 +0000322 gsbi1_i2c: i2c@12460000 {
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530323 compatible = "qcom,i2c-qup-v1.1.1";
Srinivas Kandagatla64b22b22016-02-23 14:14:26 +0000324 pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
325 pinctrl-names = "default", "sleep";
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530326 reg = <0x12460000 0x1000>;
327 interrupts = <0 194 IRQ_TYPE_NONE>;
328 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
329 clock-names = "core", "iface";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 };
Srinivas Kandagatlab2dc04c52016-02-23 14:14:33 +0000333
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530334 };
335
336 gsbi2: gsbi@12480000 {
337 status = "disabled";
338 compatible = "qcom,gsbi-v1.0.0";
Andy Gross4105d9d2015-02-09 16:01:08 -0600339 cell-index = <2>;
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530340 reg = <0x12480000 0x100>;
341 clocks = <&gcc GSBI2_H_CLK>;
342 clock-names = "iface";
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346
Andy Gross4105d9d2015-02-09 16:01:08 -0600347 syscon-tcsr = <&tcsr>;
348
Srinivas Kandagatlae07214d2016-02-23 14:11:10 +0000349 gsbi2_i2c: i2c@124a0000 {
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530350 compatible = "qcom,i2c-qup-v1.1.1";
351 reg = <0x124a0000 0x1000>;
Srinivas Kandagatla7788d432016-02-23 14:14:45 +0000352 pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
353 pinctrl-names = "default", "sleep";
kiran.padwal@smartplayin.com8c3166f2014-09-17 16:00:25 +0530354 interrupts = <0 196 IRQ_TYPE_NONE>;
355 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
356 clock-names = "core", "iface";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 };
360 };
361
Srinivas Kandagatla3f62b462015-04-10 21:44:48 +0100362 gsbi3: gsbi@16200000 {
363 status = "disabled";
364 compatible = "qcom,gsbi-v1.0.0";
Srinivas Kandagatla504155c2015-07-27 14:52:19 +0100365 cell-index = <3>;
Srinivas Kandagatla3f62b462015-04-10 21:44:48 +0100366 reg = <0x16200000 0x100>;
367 clocks = <&gcc GSBI3_H_CLK>;
368 clock-names = "iface";
369 #address-cells = <1>;
370 #size-cells = <1>;
371 ranges;
Srinivas Kandagatlae07214d2016-02-23 14:11:10 +0000372 gsbi3_i2c: i2c@16280000 {
Srinivas Kandagatla3f62b462015-04-10 21:44:48 +0100373 compatible = "qcom,i2c-qup-v1.1.1";
Srinivas Kandagatla64b22b22016-02-23 14:14:26 +0000374 pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
375 pinctrl-names = "default", "sleep";
Srinivas Kandagatla3f62b462015-04-10 21:44:48 +0100376 reg = <0x16280000 0x1000>;
377 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
378 clocks = <&gcc GSBI3_QUP_CLK>,
379 <&gcc GSBI3_H_CLK>;
380 clock-names = "core", "iface";
John Stultz5d31f602016-02-05 10:06:17 -0800381 #address-cells = <1>;
382 #size-cells = <0>;
Srinivas Kandagatla3f62b462015-04-10 21:44:48 +0100383 };
384 };
385
Srinivas Kandagatla2a5cbc12016-02-23 14:14:50 +0000386 gsbi4: gsbi@16300000 {
387 status = "disabled";
388 compatible = "qcom,gsbi-v1.0.0";
389 cell-index = <4>;
390 reg = <0x16300000 0x03>;
391 clocks = <&gcc GSBI4_H_CLK>;
392 clock-names = "iface";
393 #address-cells = <1>;
394 #size-cells = <1>;
395 ranges;
396
397 gsbi4_i2c: i2c@16380000 {
398 compatible = "qcom,i2c-qup-v1.1.1";
399 pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;
400 pinctrl-names = "default", "sleep";
401 reg = <0x16380000 0x1000>;
402 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
403 clocks = <&gcc GSBI4_QUP_CLK>,
404 <&gcc GSBI4_H_CLK>;
405 clock-names = "core", "iface";
406 };
407 };
408
Bjorn Andersson1099b262015-10-22 11:13:50 -0700409 gsbi5: gsbi@1a200000 {
410 status = "disabled";
411 compatible = "qcom,gsbi-v1.0.0";
412 cell-index = <5>;
413 reg = <0x1a200000 0x03>;
414 clocks = <&gcc GSBI5_H_CLK>;
415 clock-names = "iface";
416 #address-cells = <1>;
417 #size-cells = <1>;
418 ranges;
419
420 gsbi5_serial: serial@1a240000 {
421 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
422 reg = <0x1a240000 0x100>,
423 <0x1a200000 0x03>;
424 interrupts = <0 154 0x0>;
425 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
426 clock-names = "core", "iface";
427 status = "disabled";
428 };
Srinivas Kandagatlab2dc04c52016-02-23 14:14:33 +0000429
430 gsbi5_spi: spi@1a280000 {
431 compatible = "qcom,spi-qup-v1.1.1";
432 reg = <0x1a280000 0x1000>;
433 interrupts = <0 155 0>;
434 pinctrl-0 = <&spi5_default &spi5_sleep>;
435 pinctrl-names = "default", "sleep";
436 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
437 clock-names = "core", "iface";
438 status = "disabled";
439 #address-cells = <1>;
440 #size-cells = <0>;
441 };
Bjorn Andersson1099b262015-10-22 11:13:50 -0700442 };
443
Pramod Gurav86e252a2015-07-27 14:52:10 +0100444 gsbi6: gsbi@16500000 {
445 status = "disabled";
446 compatible = "qcom,gsbi-v1.0.0";
447 cell-index = <6>;
448 reg = <0x16500000 0x03>;
449 clocks = <&gcc GSBI6_H_CLK>;
450 clock-names = "iface";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 ranges;
454
455 gsbi6_serial: serial@16540000 {
456 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
457 reg = <0x16540000 0x100>,
458 <0x16500000 0x03>;
459 interrupts = <0 156 0x0>;
460 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
461 clock-names = "core", "iface";
462 status = "disabled";
463 };
Srinivas Kandagatla806334e2016-02-23 14:15:03 +0000464
465 gsbi6_i2c: i2c@16580000 {
466 compatible = "qcom,i2c-qup-v1.1.1";
467 pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>;
468 pinctrl-names = "default", "sleep";
469 reg = <0x16580000 0x1000>;
470 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
471 clocks = <&gcc GSBI6_QUP_CLK>,
472 <&gcc GSBI6_H_CLK>;
473 clock-names = "core", "iface";
474 };
Pramod Gurav86e252a2015-07-27 14:52:10 +0100475 };
476
Kumar Galaf335b8a2014-04-03 14:48:22 -0500477 gsbi7: gsbi@16600000 {
478 status = "disabled";
479 compatible = "qcom,gsbi-v1.0.0";
Andy Gross4105d9d2015-02-09 16:01:08 -0600480 cell-index = <7>;
Kumar Galaf335b8a2014-04-03 14:48:22 -0500481 reg = <0x16600000 0x100>;
482 clocks = <&gcc GSBI7_H_CLK>;
483 clock-names = "iface";
484 #address-cells = <1>;
485 #size-cells = <1>;
486 ranges;
Andy Gross4105d9d2015-02-09 16:01:08 -0600487 syscon-tcsr = <&tcsr>;
488
Pramod Guravd5d46542015-04-10 21:44:31 +0100489 gsbi7_serial: serial@16640000 {
Kumar Galaf335b8a2014-04-03 14:48:22 -0500490 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
491 reg = <0x16640000 0x1000>,
492 <0x16600000 0x1000>;
493 interrupts = <0 158 0x0>;
494 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
495 clock-names = "core", "iface";
496 status = "disabled";
497 };
498 };
499
John Stultz6a607e02015-09-18 13:31:12 +0100500 rng@1a500000 {
501 compatible = "qcom,prng";
502 reg = <0x1a500000 0x200>;
503 clocks = <&gcc PRNG_CLK>;
504 clock-names = "core";
505 };
506
Kumar Galaf335b8a2014-04-03 14:48:22 -0500507 qcom,ssbi@500000 {
508 compatible = "qcom,ssbi";
509 reg = <0x00500000 0x1000>;
510 qcom,controller-type = "pmic-arbiter";
Srinivas Kandagatla874443f2015-07-27 14:51:52 +0100511
512 pmicintc: pmic@0 {
513 compatible = "qcom,pm8921";
514 interrupt-parent = <&tlmm_pinmux>;
515 interrupts = <74 8>;
516 #interrupt-cells = <2>;
517 interrupt-controller;
518 #address-cells = <1>;
519 #size-cells = <0>;
520
521 pm8921_gpio: gpio@150 {
522
Stephen Boyd2ca9c2a42015-11-20 17:49:46 -0800523 compatible = "qcom,pm8921-gpio",
524 "qcom,ssbi-gpio";
Srinivas Kandagatla874443f2015-07-27 14:51:52 +0100525 reg = <0x150>;
526 interrupts = <192 1>, <193 1>, <194 1>,
527 <195 1>, <196 1>, <197 1>,
528 <198 1>, <199 1>, <200 1>,
529 <201 1>, <202 1>, <203 1>,
530 <204 1>, <205 1>, <206 1>,
531 <207 1>, <208 1>, <209 1>,
532 <210 1>, <211 1>, <212 1>,
533 <213 1>, <214 1>, <215 1>,
534 <216 1>, <217 1>, <218 1>,
535 <219 1>, <220 1>, <221 1>,
536 <222 1>, <223 1>, <224 1>,
537 <225 1>, <226 1>, <227 1>,
538 <228 1>, <229 1>, <230 1>,
539 <231 1>, <232 1>, <233 1>,
540 <234 1>, <235 1>;
541
542 gpio-controller;
543 #gpio-cells = <2>;
544
545 };
Srinivas Kandagatlabce36042015-07-27 14:52:02 +0100546
547 pm8921_mpps: mpps@50 {
Stephen Boyd2ca9c2a42015-11-20 17:49:46 -0800548 compatible = "qcom,pm8921-mpp",
549 "qcom,ssbi-mpp";
Srinivas Kandagatlabce36042015-07-27 14:52:02 +0100550 reg = <0x50>;
551 gpio-controller;
552 #gpio-cells = <2>;
553 interrupts =
554 <128 1>, <129 1>, <130 1>, <131 1>,
555 <132 1>, <133 1>, <134 1>, <135 1>,
556 <136 1>, <137 1>, <138 1>, <139 1>;
557 };
558
Srinivas Kandagatlabbf89b92015-09-18 13:31:19 +0100559 rtc@11d {
560 compatible = "qcom,pm8921-rtc";
561 interrupt-parent = <&pmicintc>;
562 interrupts = <39 1>;
563 reg = <0x11d>;
564 allow-set-time;
565 };
566
Srinivas Kandagatla3050c5f2015-09-18 13:31:25 +0100567 pwrkey@1c {
568 compatible = "qcom,pm8921-pwrkey";
569 reg = <0x1c>;
570 interrupt-parent = <&pmicintc>;
571 interrupts = <50 1>, <51 1>;
572 debounce = <15625>;
573 pull-up;
574 };
Srinivas Kandagatla874443f2015-07-27 14:51:52 +0100575 };
Kumar Galaf335b8a2014-04-03 14:48:22 -0500576 };
577
578 gcc: clock-controller@900000 {
579 compatible = "qcom,gcc-apq8064";
580 reg = <0x00900000 0x4000>;
581 #clock-cells = <1>;
582 #reset-cells = <1>;
583 };
Stephen Boyd3fe5e3c2014-07-16 13:49:43 -0700584
Kumar Gala1e1177b2015-01-28 13:36:12 -0800585 lcc: clock-controller@28000000 {
586 compatible = "qcom,lcc-apq8064";
587 reg = <0x28000000 0x1000>;
588 #clock-cells = <1>;
589 #reset-cells = <1>;
590 };
591
Stephen Boyd3fe5e3c2014-07-16 13:49:43 -0700592 mmcc: clock-controller@4000000 {
593 compatible = "qcom,mmcc-apq8064";
594 reg = <0x4000000 0x1000>;
595 #clock-cells = <1>;
596 #reset-cells = <1>;
597 };
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100598
Srinivas Kandagatladc2f8152015-04-10 21:42:44 +0100599 l2cc: clock-controller@2011000 {
600 compatible = "syscon";
601 reg = <0x2011000 0x1000>;
602 };
603
604 rpm@108000 {
605 compatible = "qcom,rpm-apq8064";
606 reg = <0x108000 0x1000>;
607 qcom,ipc = <&l2cc 0x8 2>;
608
609 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
610 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
611 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
612 interrupt-names = "ack", "err", "wakeup";
613
Georgi Djakovaac1b292015-12-03 16:02:56 +0200614 rpmcc: clock-controller {
615 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
616 #clock-cells = <1>;
617 };
618
Srinivas Kandagatladc2f8152015-04-10 21:42:44 +0100619 regulators {
620 compatible = "qcom,rpm-pm8921-regulators";
621
Bjorn Andersson2bce6e22015-10-22 11:13:49 -0700622 pm8921_s1: s1 {};
623 pm8921_s2: s2 {};
624 pm8921_s3: s3 {};
625 pm8921_s4: s4 {};
626 pm8921_s7: s7 {};
627 pm8921_s8: s8 {};
628
629 pm8921_l1: l1 {};
630 pm8921_l2: l2 {};
631 pm8921_l3: l3 {};
632 pm8921_l4: l4 {};
633 pm8921_l5: l5 {};
634 pm8921_l6: l6 {};
635 pm8921_l7: l7 {};
636 pm8921_l8: l8 {};
637 pm8921_l9: l9 {};
638 pm8921_l10: l10 {};
639 pm8921_l11: l11 {};
640 pm8921_l12: l12 {};
641 pm8921_l14: l14 {};
642 pm8921_l15: l15 {};
643 pm8921_l16: l16 {};
644 pm8921_l17: l17 {};
645 pm8921_l18: l18 {};
646 pm8921_l21: l21 {};
647 pm8921_l22: l22 {};
648 pm8921_l23: l23 {};
649 pm8921_l24: l24 {};
650 pm8921_l25: l25 {};
651 pm8921_l26: l26 {};
652 pm8921_l27: l27 {};
653 pm8921_l28: l28 {};
654 pm8921_l29: l29 {};
655
656 pm8921_lvs1: lvs1 {};
657 pm8921_lvs2: lvs2 {};
658 pm8921_lvs3: lvs3 {};
659 pm8921_lvs4: lvs4 {};
660 pm8921_lvs5: lvs5 {};
661 pm8921_lvs6: lvs6 {};
662 pm8921_lvs7: lvs7 {};
663
664 pm8921_usb_switch: usb-switch {};
665
Srinivas Kandagatladc2f8152015-04-10 21:42:44 +0100666 pm8921_hdmi_switch: hdmi-switch {
667 bias-pull-down;
668 };
Bjorn Andersson2bce6e22015-10-22 11:13:49 -0700669
670 pm8921_ncp: ncp {};
Srinivas Kandagatladc2f8152015-04-10 21:42:44 +0100671 };
672 };
673
Srinivas Kandagatlaea986612015-04-10 21:43:42 +0100674 usb1_phy: phy@12500000 {
675 compatible = "qcom,usb-otg-ci";
676 reg = <0x12500000 0x400>;
677 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
678 status = "disabled";
679 dr_mode = "host";
680
681 clocks = <&gcc USB_HS1_XCVR_CLK>,
682 <&gcc USB_HS1_H_CLK>;
683 clock-names = "core", "iface";
684
685 resets = <&gcc USB_HS1_RESET>;
686 reset-names = "link";
687 };
688
Srinivas Kandagatla223280b2015-04-10 21:43:30 +0100689 usb3_phy: phy@12520000 {
690 compatible = "qcom,usb-otg-ci";
691 reg = <0x12520000 0x400>;
692 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
693 status = "disabled";
694 dr_mode = "host";
695
696 clocks = <&gcc USB_HS3_XCVR_CLK>,
697 <&gcc USB_HS3_H_CLK>;
698 clock-names = "core", "iface";
699
700 resets = <&gcc USB_HS3_RESET>;
701 reset-names = "link";
702 };
703
704 usb4_phy: phy@12530000 {
705 compatible = "qcom,usb-otg-ci";
706 reg = <0x12530000 0x400>;
707 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
708 status = "disabled";
709 dr_mode = "host";
710
711 clocks = <&gcc USB_HS4_XCVR_CLK>,
712 <&gcc USB_HS4_H_CLK>;
713 clock-names = "core", "iface";
714
715 resets = <&gcc USB_HS4_RESET>;
716 reset-names = "link";
717 };
718
Srinivas Kandagatlaea986612015-04-10 21:43:42 +0100719 gadget1: gadget@12500000 {
720 compatible = "qcom,ci-hdrc";
721 reg = <0x12500000 0x400>;
722 status = "disabled";
723 dr_mode = "peripheral";
724 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
725 usb-phy = <&usb1_phy>;
726 };
727
728 usb1: usb@12500000 {
729 compatible = "qcom,ehci-host";
730 reg = <0x12500000 0x400>;
731 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
732 status = "disabled";
733 usb-phy = <&usb1_phy>;
734 };
735
Srinivas Kandagatla223280b2015-04-10 21:43:30 +0100736 usb3: usb@12520000 {
737 compatible = "qcom,ehci-host";
738 reg = <0x12520000 0x400>;
739 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
740 status = "disabled";
741 usb-phy = <&usb3_phy>;
742 };
743
744 usb4: usb@12530000 {
745 compatible = "qcom,ehci-host";
746 reg = <0x12530000 0x400>;
747 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
748 status = "disabled";
749 usb-phy = <&usb4_phy>;
750 };
751
Srinivas Kandagatlae6293352015-04-10 21:43:56 +0100752 sata_phy0: phy@1b400000 {
753 compatible = "qcom,apq8064-sata-phy";
754 status = "disabled";
755 reg = <0x1b400000 0x200>;
756 reg-names = "phy_mem";
757 clocks = <&gcc SATA_PHY_CFG_CLK>;
758 clock-names = "cfg";
759 #phy-cells = <0>;
760 };
761
762 sata0: sata@29000000 {
763 compatible = "generic-ahci";
764 status = "disabled";
765 reg = <0x29000000 0x180>;
766 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
767
768 clocks = <&gcc SFAB_SATA_S_H_CLK>,
769 <&gcc SATA_H_CLK>,
770 <&gcc SATA_A_CLK>,
771 <&gcc SATA_RXOOB_CLK>,
772 <&gcc SATA_PMALIVE_CLK>;
773 clock-names = "slave_iface",
774 "iface",
775 "bus",
776 "rxoob",
777 "core_pmalive";
778
779 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
780 <&gcc SATA_PMALIVE_CLK>;
781 assigned-clock-rates = <100000000>, <100000000>;
782
783 phys = <&sata_phy0>;
784 phy-names = "sata-phy";
785 };
786
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100787 /* Temporary fixed regulator */
Srinivas Kandagatlaedb81ca2014-05-16 20:18:53 +0100788 sdcc1bam:dma@12402000{
789 compatible = "qcom,bam-v1.3.0";
790 reg = <0x12402000 0x8000>;
791 interrupts = <0 98 0>;
792 clocks = <&gcc SDC1_H_CLK>;
793 clock-names = "bam_clk";
794 #dma-cells = <1>;
795 qcom,ee = <0>;
796 };
797
798 sdcc3bam:dma@12182000{
799 compatible = "qcom,bam-v1.3.0";
800 reg = <0x12182000 0x8000>;
801 interrupts = <0 96 0>;
802 clocks = <&gcc SDC3_H_CLK>;
803 clock-names = "bam_clk";
804 #dma-cells = <1>;
805 qcom,ee = <0>;
806 };
807
Srinivas Kandagatla0be5fef2014-09-17 06:39:35 +0100808 sdcc4bam:dma@121c2000{
809 compatible = "qcom,bam-v1.3.0";
810 reg = <0x121c2000 0x8000>;
811 interrupts = <0 95 0>;
812 clocks = <&gcc SDC4_H_CLK>;
813 clock-names = "bam_clk";
814 #dma-cells = <1>;
815 qcom,ee = <0>;
816 };
817
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100818 amba {
Masahiro Yamada2ef7d5f2016-03-09 13:26:45 +0900819 compatible = "simple-bus";
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100820 #address-cells = <1>;
821 #size-cells = <1>;
822 ranges;
823 sdcc1: sdcc@12400000 {
824 status = "disabled";
825 compatible = "arm,pl18x", "arm,primecell";
826 arm,primecell-periphid = <0x00051180>;
827 reg = <0x12400000 0x2000>;
828 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
829 interrupt-names = "cmd_irq";
830 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
831 clock-names = "mclk", "apb_pclk";
832 bus-width = <8>;
833 max-frequency = <96000000>;
834 non-removable;
835 cap-sd-highspeed;
836 cap-mmc-highspeed;
Srinivas Kandagatlaedb81ca2014-05-16 20:18:53 +0100837 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
838 dma-names = "tx", "rx";
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100839 };
840
841 sdcc3: sdcc@12180000 {
842 compatible = "arm,pl18x", "arm,primecell";
843 arm,primecell-periphid = <0x00051180>;
844 status = "disabled";
845 reg = <0x12180000 0x2000>;
846 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
847 interrupt-names = "cmd_irq";
848 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
849 clock-names = "mclk", "apb_pclk";
850 bus-width = <4>;
851 cap-sd-highspeed;
852 cap-mmc-highspeed;
853 max-frequency = <192000000>;
854 no-1-8-v;
Srinivas Kandagatlaedb81ca2014-05-16 20:18:53 +0100855 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
856 dma-names = "tx", "rx";
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100857 };
Srinivas Kandagatla0be5fef2014-09-17 06:39:35 +0100858
859 sdcc4: sdcc@121c0000 {
860 compatible = "arm,pl18x", "arm,primecell";
861 arm,primecell-periphid = <0x00051180>;
862 status = "disabled";
863 reg = <0x121c0000 0x2000>;
864 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
865 interrupt-names = "cmd_irq";
866 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
867 clock-names = "mclk", "apb_pclk";
868 bus-width = <4>;
869 cap-sd-highspeed;
870 cap-mmc-highspeed;
871 max-frequency = <48000000>;
Srinivas Kandagatla0be5fef2014-09-17 06:39:35 +0100872 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
873 dma-names = "tx", "rx";
874 pinctrl-names = "default";
875 pinctrl-0 = <&sdc4_gpios>;
876 };
Srinivas Kandagatla045644f2014-04-29 08:33:52 +0100877 };
Andy Gross4105d9d2015-02-09 16:01:08 -0600878
879 tcsr: syscon@1a400000 {
880 compatible = "qcom,tcsr-apq8064", "syscon";
881 reg = <0x1a400000 0x100>;
882 };
Stanimir Varbanovbcc74b02015-12-18 14:38:58 +0200883
884 pcie: pci@1b500000 {
885 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
886 reg = <0x1b500000 0x1000
887 0x1b502000 0x80
888 0x1b600000 0x100
889 0x0ff00000 0x100000>;
890 reg-names = "dbi", "elbi", "parf", "config";
891 device_type = "pci";
892 linux,pci-domain = <0>;
893 bus-range = <0x00 0xff>;
894 num-lanes = <1>;
895 #address-cells = <3>;
896 #size-cells = <2>;
897 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
898 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
899 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
900 interrupt-names = "msi";
901 #interrupt-cells = <1>;
902 interrupt-map-mask = <0 0 0 0x7>;
903 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
904 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
905 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
906 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
907 clocks = <&gcc PCIE_A_CLK>,
908 <&gcc PCIE_H_CLK>,
909 <&gcc PCIE_PHY_REF_CLK>;
910 clock-names = "core", "iface", "phy";
911 resets = <&gcc PCIE_ACLK_RESET>,
912 <&gcc PCIE_HCLK_RESET>,
913 <&gcc PCIE_POR_RESET>,
914 <&gcc PCIE_PCI_RESET>,
915 <&gcc PCIE_PHY_RESET>;
916 reset-names = "axi", "ahb", "por", "pci", "phy";
917 status = "disabled";
918 };
Kumar Galaf335b8a2014-04-03 14:48:22 -0500919 };
920};
Srinivas Kandagatlaa30e78b2016-02-23 14:14:07 +0000921#include "qcom-apq8064-pins.dtsi"