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Johannes Berge9676692012-04-10 14:10:28 -07001/******************************************************************************
2 *
3 * Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27/*
28 * DVM device-specific data & functions
29 */
30#include "iwl-core.h"
31#include "iwl-agn.h"
32#include "iwl-dev.h"
33#include "iwl-commands.h"
34#include "iwl-io.h"
35#include "iwl-prph.h"
36
37/*
38 * 1000 series
39 * ===========
40 */
41
42/*
43 * For 1000, use advance thermal throttling critical temperature threshold,
44 * but legacy thermal management implementation for now.
45 * This is for the reason of 1000 uCode using advance thermal throttling API
46 * but not implement ct_kill_exit based on ct_kill exit temperature
47 * so the thermal throttling will still based on legacy thermal throttling
48 * management.
49 * The code here need to be modified once 1000 uCode has the advanced thermal
50 * throttling algorithm in place
51 */
52static void iwl1000_set_ct_threshold(struct iwl_priv *priv)
53{
54 /* want Celsius */
55 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
56 priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
57}
58
59/* NIC configuration for 1000 series */
60static void iwl1000_nic_config(struct iwl_priv *priv)
61{
62 /* set CSR_HW_CONFIG_REG for uCode use */
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -070063 iwl_set_bit(priv->trans, CSR_HW_IF_CONFIG_REG,
Johannes Berge9676692012-04-10 14:10:28 -070064 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
65 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
66
67 /* Setting digital SVR for 1000 card to 1.32V */
68 /* locking is acquired in iwl_set_bits_mask_prph() function */
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -070069 iwl_set_bits_mask_prph(priv->trans, APMG_DIGITAL_SVR_REG,
Johannes Berge9676692012-04-10 14:10:28 -070070 APMG_SVR_DIGITAL_VOLTAGE_1_32,
71 ~APMG_SVR_VOLTAGE_CONFIG_BIT_MSK);
72}
73
Meenakshi Venkataramane381b212012-03-13 15:18:07 -070074/**
75 * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time
76 * @priv -- pointer to iwl_priv data structure
77 * @tsf_bits -- number of bits need to shift for masking)
78 */
79static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv,
80 u16 tsf_bits)
81{
82 return (1 << tsf_bits) - 1;
83}
84
85/**
86 * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time
87 * @priv -- pointer to iwl_priv data structure
88 * @tsf_bits -- number of bits need to shift for masking)
89 */
90static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv,
91 u16 tsf_bits)
92{
93 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
94}
95
96/*
97 * extended beacon time format
98 * time in usec will be changed into a 32-bit value in extended:internal format
99 * the extended part is the beacon counts
100 * the internal part is the time in usec within one beacon interval
101 */
102static u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec,
103 u32 beacon_interval)
104{
105 u32 quot;
106 u32 rem;
107 u32 interval = beacon_interval * TIME_UNIT;
108
109 if (!interval || !usec)
110 return 0;
111
112 quot = (usec / interval) &
113 (iwl_beacon_time_mask_high(priv, IWLAGN_EXT_BEACON_TIME_POS) >>
114 IWLAGN_EXT_BEACON_TIME_POS);
115 rem = (usec % interval) & iwl_beacon_time_mask_low(priv,
116 IWLAGN_EXT_BEACON_TIME_POS);
117
118 return (quot << IWLAGN_EXT_BEACON_TIME_POS) + rem;
119}
120
121/* base is usually what we get from ucode with each received frame,
122 * the same as HW timer counter counting down
123 */
124static __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
125 u32 addon, u32 beacon_interval)
126{
127 u32 base_low = base & iwl_beacon_time_mask_low(priv,
128 IWLAGN_EXT_BEACON_TIME_POS);
129 u32 addon_low = addon & iwl_beacon_time_mask_low(priv,
130 IWLAGN_EXT_BEACON_TIME_POS);
131 u32 interval = beacon_interval * TIME_UNIT;
132 u32 res = (base & iwl_beacon_time_mask_high(priv,
133 IWLAGN_EXT_BEACON_TIME_POS)) +
134 (addon & iwl_beacon_time_mask_high(priv,
135 IWLAGN_EXT_BEACON_TIME_POS));
136
137 if (base_low > addon_low)
138 res += base_low - addon_low;
139 else if (base_low < addon_low) {
140 res += interval + base_low - addon_low;
141 res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
142 } else
143 res += (1 << IWLAGN_EXT_BEACON_TIME_POS);
144
145 return cpu_to_le32(res);
146}
147
Johannes Berge9676692012-04-10 14:10:28 -0700148static const struct iwl_sensitivity_ranges iwl1000_sensitivity = {
149 .min_nrg_cck = 95,
150 .auto_corr_min_ofdm = 90,
151 .auto_corr_min_ofdm_mrc = 170,
152 .auto_corr_min_ofdm_x1 = 120,
153 .auto_corr_min_ofdm_mrc_x1 = 240,
154
155 .auto_corr_max_ofdm = 120,
156 .auto_corr_max_ofdm_mrc = 210,
157 .auto_corr_max_ofdm_x1 = 155,
158 .auto_corr_max_ofdm_mrc_x1 = 290,
159
160 .auto_corr_min_cck = 125,
161 .auto_corr_max_cck = 200,
162 .auto_corr_min_cck_mrc = 170,
163 .auto_corr_max_cck_mrc = 400,
164 .nrg_th_cck = 95,
165 .nrg_th_ofdm = 95,
166
167 .barker_corr_th_min = 190,
168 .barker_corr_th_min_mrc = 390,
169 .nrg_th_cca = 62,
170};
171
172static void iwl1000_hw_set_hw_params(struct iwl_priv *priv)
173{
174 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ);
175
176 priv->hw_params.tx_chains_num =
177 num_of_ant(priv->hw_params.valid_tx_ant);
178 if (cfg(priv)->rx_with_siso_diversity)
179 priv->hw_params.rx_chains_num = 1;
180 else
181 priv->hw_params.rx_chains_num =
182 num_of_ant(priv->hw_params.valid_rx_ant);
183
184 iwl1000_set_ct_threshold(priv);
185
186 /* Set initial sensitivity parameters */
187 priv->hw_params.sens = &iwl1000_sensitivity;
188}
189
190struct iwl_lib_ops iwl1000_lib = {
191 .set_hw_params = iwl1000_hw_set_hw_params,
192 .nic_config = iwl1000_nic_config,
193 .eeprom_ops = {
194 .regulatory_bands = {
195 EEPROM_REG_BAND_1_CHANNELS,
196 EEPROM_REG_BAND_2_CHANNELS,
197 EEPROM_REG_BAND_3_CHANNELS,
198 EEPROM_REG_BAND_4_CHANNELS,
199 EEPROM_REG_BAND_5_CHANNELS,
200 EEPROM_REG_BAND_24_HT40_CHANNELS,
201 EEPROM_REGULATORY_BAND_NO_HT40,
202 },
203 },
204 .temperature = iwlagn_temperature,
205};
206
207
208/*
209 * 2000 series
210 * ===========
211 */
212
213static void iwl2000_set_ct_threshold(struct iwl_priv *priv)
214{
215 /* want Celsius */
216 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
217 priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
218}
219
220/* NIC configuration for 2000 series */
221static void iwl2000_nic_config(struct iwl_priv *priv)
222{
223 iwl_rf_config(priv);
224
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700225 iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700226 CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER);
227}
228
229static const struct iwl_sensitivity_ranges iwl2000_sensitivity = {
230 .min_nrg_cck = 97,
231 .auto_corr_min_ofdm = 80,
232 .auto_corr_min_ofdm_mrc = 128,
233 .auto_corr_min_ofdm_x1 = 105,
234 .auto_corr_min_ofdm_mrc_x1 = 192,
235
236 .auto_corr_max_ofdm = 145,
237 .auto_corr_max_ofdm_mrc = 232,
238 .auto_corr_max_ofdm_x1 = 110,
239 .auto_corr_max_ofdm_mrc_x1 = 232,
240
241 .auto_corr_min_cck = 125,
242 .auto_corr_max_cck = 175,
243 .auto_corr_min_cck_mrc = 160,
244 .auto_corr_max_cck_mrc = 310,
245 .nrg_th_cck = 97,
246 .nrg_th_ofdm = 100,
247
248 .barker_corr_th_min = 190,
249 .barker_corr_th_min_mrc = 390,
250 .nrg_th_cca = 62,
251};
252
253static void iwl2000_hw_set_hw_params(struct iwl_priv *priv)
254{
255 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ);
256
257 priv->hw_params.tx_chains_num =
258 num_of_ant(priv->hw_params.valid_tx_ant);
259 if (cfg(priv)->rx_with_siso_diversity)
260 priv->hw_params.rx_chains_num = 1;
261 else
262 priv->hw_params.rx_chains_num =
263 num_of_ant(priv->hw_params.valid_rx_ant);
264
265 iwl2000_set_ct_threshold(priv);
266
267 /* Set initial sensitivity parameters */
268 priv->hw_params.sens = &iwl2000_sensitivity;
269}
270
271struct iwl_lib_ops iwl2000_lib = {
272 .set_hw_params = iwl2000_hw_set_hw_params,
273 .nic_config = iwl2000_nic_config,
274 .eeprom_ops = {
275 .regulatory_bands = {
276 EEPROM_REG_BAND_1_CHANNELS,
277 EEPROM_REG_BAND_2_CHANNELS,
278 EEPROM_REG_BAND_3_CHANNELS,
279 EEPROM_REG_BAND_4_CHANNELS,
280 EEPROM_REG_BAND_5_CHANNELS,
281 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
282 EEPROM_REGULATORY_BAND_NO_HT40,
283 },
284 .enhanced_txpower = true,
285 },
286 .temperature = iwlagn_temperature,
287};
288
289struct iwl_lib_ops iwl2030_lib = {
290 .set_hw_params = iwl2000_hw_set_hw_params,
291 .nic_config = iwl2000_nic_config,
292 .eeprom_ops = {
293 .regulatory_bands = {
294 EEPROM_REG_BAND_1_CHANNELS,
295 EEPROM_REG_BAND_2_CHANNELS,
296 EEPROM_REG_BAND_3_CHANNELS,
297 EEPROM_REG_BAND_4_CHANNELS,
298 EEPROM_REG_BAND_5_CHANNELS,
299 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
300 EEPROM_REGULATORY_BAND_NO_HT40,
301 },
302 .enhanced_txpower = true,
303 },
304 .temperature = iwlagn_temperature,
305};
306
307/*
308 * 5000 series
309 * ===========
310 */
311
312/* NIC configuration for 5000 series */
313static void iwl5000_nic_config(struct iwl_priv *priv)
314{
315 iwl_rf_config(priv);
316
317 /* W/A : NIC is stuck in a reset state after Early PCIe power off
318 * (PCIe power is lost before PERST# is asserted),
319 * causing ME FW to lose ownership and not being able to obtain it back.
320 */
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700321 iwl_set_bits_mask_prph(priv->trans, APMG_PS_CTRL_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700322 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
323 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
324}
325
326static const struct iwl_sensitivity_ranges iwl5000_sensitivity = {
327 .min_nrg_cck = 100,
328 .auto_corr_min_ofdm = 90,
329 .auto_corr_min_ofdm_mrc = 170,
330 .auto_corr_min_ofdm_x1 = 105,
331 .auto_corr_min_ofdm_mrc_x1 = 220,
332
333 .auto_corr_max_ofdm = 120,
334 .auto_corr_max_ofdm_mrc = 210,
335 .auto_corr_max_ofdm_x1 = 120,
336 .auto_corr_max_ofdm_mrc_x1 = 240,
337
338 .auto_corr_min_cck = 125,
339 .auto_corr_max_cck = 200,
340 .auto_corr_min_cck_mrc = 200,
341 .auto_corr_max_cck_mrc = 400,
342 .nrg_th_cck = 100,
343 .nrg_th_ofdm = 100,
344
345 .barker_corr_th_min = 190,
346 .barker_corr_th_min_mrc = 390,
347 .nrg_th_cca = 62,
348};
349
350static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
351 .min_nrg_cck = 95,
352 .auto_corr_min_ofdm = 90,
353 .auto_corr_min_ofdm_mrc = 170,
354 .auto_corr_min_ofdm_x1 = 105,
355 .auto_corr_min_ofdm_mrc_x1 = 220,
356
357 .auto_corr_max_ofdm = 120,
358 .auto_corr_max_ofdm_mrc = 210,
359 /* max = min for performance bug in 5150 DSP */
360 .auto_corr_max_ofdm_x1 = 105,
361 .auto_corr_max_ofdm_mrc_x1 = 220,
362
363 .auto_corr_min_cck = 125,
364 .auto_corr_max_cck = 200,
365 .auto_corr_min_cck_mrc = 170,
366 .auto_corr_max_cck_mrc = 400,
367 .nrg_th_cck = 95,
368 .nrg_th_ofdm = 95,
369
370 .barker_corr_th_min = 190,
371 .barker_corr_th_min_mrc = 390,
372 .nrg_th_cca = 62,
373};
374
375#define IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF (-5)
376
377static s32 iwl_temp_calib_to_offset(struct iwl_priv *priv)
378{
379 u16 temperature, voltage;
380 __le16 *temp_calib = (__le16 *)iwl_eeprom_query_addr(priv,
381 EEPROM_KELVIN_TEMPERATURE);
382
383 temperature = le16_to_cpu(temp_calib[0]);
384 voltage = le16_to_cpu(temp_calib[1]);
385
386 /* offset = temp - volt / coeff */
387 return (s32)(temperature -
388 voltage / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF);
389}
390
391static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
392{
393 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
394 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
395 iwl_temp_calib_to_offset(priv);
396
397 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
398}
399
400static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
401{
402 /* want Celsius */
403 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
404}
405
406static void iwl5000_hw_set_hw_params(struct iwl_priv *priv)
407{
408 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
409 BIT(IEEE80211_BAND_5GHZ);
410
411 priv->hw_params.tx_chains_num =
412 num_of_ant(priv->hw_params.valid_tx_ant);
413 priv->hw_params.rx_chains_num =
414 num_of_ant(priv->hw_params.valid_rx_ant);
415
416 iwl5000_set_ct_threshold(priv);
417
418 /* Set initial sensitivity parameters */
419 priv->hw_params.sens = &iwl5000_sensitivity;
420}
421
422static void iwl5150_hw_set_hw_params(struct iwl_priv *priv)
423{
424 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
425 BIT(IEEE80211_BAND_5GHZ);
426
427 priv->hw_params.tx_chains_num =
428 num_of_ant(priv->hw_params.valid_tx_ant);
429 priv->hw_params.rx_chains_num =
430 num_of_ant(priv->hw_params.valid_rx_ant);
431
432 iwl5150_set_ct_threshold(priv);
433
434 /* Set initial sensitivity parameters */
435 priv->hw_params.sens = &iwl5150_sensitivity;
436}
437
438static void iwl5150_temperature(struct iwl_priv *priv)
439{
440 u32 vt = 0;
441 s32 offset = iwl_temp_calib_to_offset(priv);
442
443 vt = le32_to_cpu(priv->statistics.common.temperature);
444 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
445 /* now vt hold the temperature in Kelvin */
446 priv->temperature = KELVIN_TO_CELSIUS(vt);
447 iwl_tt_handler(priv);
448}
449
450static int iwl5000_hw_channel_switch(struct iwl_priv *priv,
451 struct ieee80211_channel_switch *ch_switch)
452{
453 /*
454 * MULTI-FIXME
455 * See iwlagn_mac_channel_switch.
456 */
457 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
458 struct iwl5000_channel_switch_cmd cmd;
459 const struct iwl_channel_info *ch_info;
460 u32 switch_time_in_usec, ucode_switch_time;
461 u16 ch;
462 u32 tsf_low;
463 u8 switch_count;
464 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
465 struct ieee80211_vif *vif = ctx->vif;
466 struct iwl_host_cmd hcmd = {
467 .id = REPLY_CHANNEL_SWITCH,
468 .len = { sizeof(cmd), },
469 .flags = CMD_SYNC,
470 .data = { &cmd, },
471 };
472
473 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
474 ch = ch_switch->channel->hw_value;
475 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
476 ctx->active.channel, ch);
477 cmd.channel = cpu_to_le16(ch);
478 cmd.rxon_flags = ctx->staging.flags;
479 cmd.rxon_filter_flags = ctx->staging.filter_flags;
480 switch_count = ch_switch->count;
481 tsf_low = ch_switch->timestamp & 0x0ffffffff;
482 /*
483 * calculate the ucode channel switch time
484 * adding TSF as one of the factor for when to switch
485 */
486 if ((priv->ucode_beacon_time > tsf_low) && beacon_interval) {
487 if (switch_count > ((priv->ucode_beacon_time - tsf_low) /
488 beacon_interval)) {
489 switch_count -= (priv->ucode_beacon_time -
490 tsf_low) / beacon_interval;
491 } else
492 switch_count = 0;
493 }
494 if (switch_count <= 1)
495 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
496 else {
497 switch_time_in_usec =
498 vif->bss_conf.beacon_int * switch_count * TIME_UNIT;
499 ucode_switch_time = iwl_usecs_to_beacons(priv,
500 switch_time_in_usec,
501 beacon_interval);
502 cmd.switch_time = iwl_add_beacon_time(priv,
503 priv->ucode_beacon_time,
504 ucode_switch_time,
505 beacon_interval);
506 }
507 IWL_DEBUG_11H(priv, "uCode time for the switch is 0x%x\n",
508 cmd.switch_time);
509 ch_info = iwl_get_channel_info(priv, priv->band, ch);
510 if (ch_info)
511 cmd.expect_beacon = is_channel_radar(ch_info);
512 else {
513 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
514 ctx->active.channel, ch);
515 return -EFAULT;
516 }
517
518 return iwl_dvm_send_cmd(priv, &hcmd);
519}
520
521struct iwl_lib_ops iwl5000_lib = {
522 .set_hw_params = iwl5000_hw_set_hw_params,
523 .set_channel_switch = iwl5000_hw_channel_switch,
524 .nic_config = iwl5000_nic_config,
525 .eeprom_ops = {
526 .regulatory_bands = {
527 EEPROM_REG_BAND_1_CHANNELS,
528 EEPROM_REG_BAND_2_CHANNELS,
529 EEPROM_REG_BAND_3_CHANNELS,
530 EEPROM_REG_BAND_4_CHANNELS,
531 EEPROM_REG_BAND_5_CHANNELS,
532 EEPROM_REG_BAND_24_HT40_CHANNELS,
533 EEPROM_REG_BAND_52_HT40_CHANNELS
534 },
535 },
536 .temperature = iwlagn_temperature,
537};
538
539struct iwl_lib_ops iwl5150_lib = {
540 .set_hw_params = iwl5150_hw_set_hw_params,
541 .set_channel_switch = iwl5000_hw_channel_switch,
542 .nic_config = iwl5000_nic_config,
543 .eeprom_ops = {
544 .regulatory_bands = {
545 EEPROM_REG_BAND_1_CHANNELS,
546 EEPROM_REG_BAND_2_CHANNELS,
547 EEPROM_REG_BAND_3_CHANNELS,
548 EEPROM_REG_BAND_4_CHANNELS,
549 EEPROM_REG_BAND_5_CHANNELS,
550 EEPROM_REG_BAND_24_HT40_CHANNELS,
551 EEPROM_REG_BAND_52_HT40_CHANNELS
552 },
553 },
554 .temperature = iwl5150_temperature,
555};
556
557
558
559/*
560 * 6000 series
561 * ===========
562 */
563
564static void iwl6000_set_ct_threshold(struct iwl_priv *priv)
565{
566 /* want Celsius */
567 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
568 priv->hw_params.ct_kill_exit_threshold = CT_KILL_EXIT_THRESHOLD;
569}
570
571/* NIC configuration for 6000 series */
572static void iwl6000_nic_config(struct iwl_priv *priv)
573{
574 iwl_rf_config(priv);
575
576 switch (cfg(priv)->device_family) {
577 case IWL_DEVICE_FAMILY_6005:
578 case IWL_DEVICE_FAMILY_6030:
579 case IWL_DEVICE_FAMILY_6000:
580 break;
581 case IWL_DEVICE_FAMILY_6000i:
582 /* 2x2 IPA phy type */
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700583 iwl_write32(priv->trans, CSR_GP_DRIVER_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700584 CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA);
585 break;
586 case IWL_DEVICE_FAMILY_6050:
587 /* Indicate calibration version to uCode. */
588 if (iwl_eeprom_calib_version(priv) >= 6)
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700589 iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700590 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
591 break;
592 case IWL_DEVICE_FAMILY_6150:
593 /* Indicate calibration version to uCode. */
594 if (iwl_eeprom_calib_version(priv) >= 6)
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700595 iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700596 CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6);
Emmanuel Grumbach68e8dfd2012-04-18 07:28:17 -0700597 iwl_set_bit(priv->trans, CSR_GP_DRIVER_REG,
Johannes Berge9676692012-04-10 14:10:28 -0700598 CSR_GP_DRIVER_REG_BIT_6050_1x2);
599 break;
600 default:
601 WARN_ON(1);
602 }
603}
604
605static const struct iwl_sensitivity_ranges iwl6000_sensitivity = {
606 .min_nrg_cck = 110,
607 .auto_corr_min_ofdm = 80,
608 .auto_corr_min_ofdm_mrc = 128,
609 .auto_corr_min_ofdm_x1 = 105,
610 .auto_corr_min_ofdm_mrc_x1 = 192,
611
612 .auto_corr_max_ofdm = 145,
613 .auto_corr_max_ofdm_mrc = 232,
614 .auto_corr_max_ofdm_x1 = 110,
615 .auto_corr_max_ofdm_mrc_x1 = 232,
616
617 .auto_corr_min_cck = 125,
618 .auto_corr_max_cck = 175,
619 .auto_corr_min_cck_mrc = 160,
620 .auto_corr_max_cck_mrc = 310,
621 .nrg_th_cck = 110,
622 .nrg_th_ofdm = 110,
623
624 .barker_corr_th_min = 190,
625 .barker_corr_th_min_mrc = 336,
626 .nrg_th_cca = 62,
627};
628
629static void iwl6000_hw_set_hw_params(struct iwl_priv *priv)
630{
631 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
632 BIT(IEEE80211_BAND_5GHZ);
633
634 priv->hw_params.tx_chains_num =
635 num_of_ant(priv->hw_params.valid_tx_ant);
636 if (cfg(priv)->rx_with_siso_diversity)
637 priv->hw_params.rx_chains_num = 1;
638 else
639 priv->hw_params.rx_chains_num =
640 num_of_ant(priv->hw_params.valid_rx_ant);
641
642 iwl6000_set_ct_threshold(priv);
643
644 /* Set initial sensitivity parameters */
645 priv->hw_params.sens = &iwl6000_sensitivity;
646
647}
648
649static int iwl6000_hw_channel_switch(struct iwl_priv *priv,
650 struct ieee80211_channel_switch *ch_switch)
651{
652 /*
653 * MULTI-FIXME
654 * See iwlagn_mac_channel_switch.
655 */
656 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
657 struct iwl6000_channel_switch_cmd cmd;
658 const struct iwl_channel_info *ch_info;
659 u32 switch_time_in_usec, ucode_switch_time;
660 u16 ch;
661 u32 tsf_low;
662 u8 switch_count;
663 u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval);
664 struct ieee80211_vif *vif = ctx->vif;
665 struct iwl_host_cmd hcmd = {
666 .id = REPLY_CHANNEL_SWITCH,
667 .len = { sizeof(cmd), },
668 .flags = CMD_SYNC,
669 .data = { &cmd, },
670 };
671
672 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
673 ch = ch_switch->channel->hw_value;
674 IWL_DEBUG_11H(priv, "channel switch from %u to %u\n",
675 ctx->active.channel, ch);
676 cmd.channel = cpu_to_le16(ch);
677 cmd.rxon_flags = ctx->staging.flags;
678 cmd.rxon_filter_flags = ctx->staging.filter_flags;
679 switch_count = ch_switch->count;
680 tsf_low = ch_switch->timestamp & 0x0ffffffff;
681 /*
682 * calculate the ucode channel switch time
683 * adding TSF as one of the factor for when to switch
684 */
685 if ((priv->ucode_beacon_time > tsf_low) && beacon_interval) {
686 if (switch_count > ((priv->ucode_beacon_time - tsf_low) /
687 beacon_interval)) {
688 switch_count -= (priv->ucode_beacon_time -
689 tsf_low) / beacon_interval;
690 } else
691 switch_count = 0;
692 }
693 if (switch_count <= 1)
694 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
695 else {
696 switch_time_in_usec =
697 vif->bss_conf.beacon_int * switch_count * TIME_UNIT;
698 ucode_switch_time = iwl_usecs_to_beacons(priv,
699 switch_time_in_usec,
700 beacon_interval);
701 cmd.switch_time = iwl_add_beacon_time(priv,
702 priv->ucode_beacon_time,
703 ucode_switch_time,
704 beacon_interval);
705 }
706 IWL_DEBUG_11H(priv, "uCode time for the switch is 0x%x\n",
707 cmd.switch_time);
708 ch_info = iwl_get_channel_info(priv, priv->band, ch);
709 if (ch_info)
710 cmd.expect_beacon = is_channel_radar(ch_info);
711 else {
712 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
713 ctx->active.channel, ch);
714 return -EFAULT;
715 }
716
717 return iwl_dvm_send_cmd(priv, &hcmd);
718}
719
720struct iwl_lib_ops iwl6000_lib = {
721 .set_hw_params = iwl6000_hw_set_hw_params,
722 .set_channel_switch = iwl6000_hw_channel_switch,
723 .nic_config = iwl6000_nic_config,
724 .eeprom_ops = {
725 .regulatory_bands = {
726 EEPROM_REG_BAND_1_CHANNELS,
727 EEPROM_REG_BAND_2_CHANNELS,
728 EEPROM_REG_BAND_3_CHANNELS,
729 EEPROM_REG_BAND_4_CHANNELS,
730 EEPROM_REG_BAND_5_CHANNELS,
731 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
732 EEPROM_REG_BAND_52_HT40_CHANNELS
733 },
734 .enhanced_txpower = true,
735 },
736 .temperature = iwlagn_temperature,
737};
738
739struct iwl_lib_ops iwl6030_lib = {
740 .set_hw_params = iwl6000_hw_set_hw_params,
741 .set_channel_switch = iwl6000_hw_channel_switch,
742 .nic_config = iwl6000_nic_config,
743 .eeprom_ops = {
744 .regulatory_bands = {
745 EEPROM_REG_BAND_1_CHANNELS,
746 EEPROM_REG_BAND_2_CHANNELS,
747 EEPROM_REG_BAND_3_CHANNELS,
748 EEPROM_REG_BAND_4_CHANNELS,
749 EEPROM_REG_BAND_5_CHANNELS,
750 EEPROM_6000_REG_BAND_24_HT40_CHANNELS,
751 EEPROM_REG_BAND_52_HT40_CHANNELS
752 },
753 .enhanced_txpower = true,
754 },
755 .temperature = iwlagn_temperature,
756};