Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | /include/ "skeleton.dtsi" |
| 13 | |
| 14 | / { |
| 15 | interrupt-parent = <&icoll>; |
| 16 | |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 17 | aliases { |
| 18 | gpio0 = &gpio0; |
| 19 | gpio1 = &gpio1; |
| 20 | gpio2 = &gpio2; |
| 21 | gpio3 = &gpio3; |
| 22 | gpio4 = &gpio4; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 23 | saif0 = &saif0; |
| 24 | saif1 = &saif1; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 25 | serial0 = &auart0; |
| 26 | serial1 = &auart1; |
| 27 | serial2 = &auart2; |
| 28 | serial3 = &auart3; |
| 29 | serial4 = &auart4; |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 30 | }; |
| 31 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 32 | cpus { |
| 33 | cpu@0 { |
| 34 | compatible = "arm,arm926ejs"; |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | apb@80000000 { |
| 39 | compatible = "simple-bus"; |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <1>; |
| 42 | reg = <0x80000000 0x80000>; |
| 43 | ranges; |
| 44 | |
| 45 | apbh@80000000 { |
| 46 | compatible = "simple-bus"; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <1>; |
| 49 | reg = <0x80000000 0x3c900>; |
| 50 | ranges; |
| 51 | |
| 52 | icoll: interrupt-controller@80000000 { |
| 53 | compatible = "fsl,imx28-icoll", "fsl,mxs-icoll"; |
| 54 | interrupt-controller; |
| 55 | #interrupt-cells = <1>; |
| 56 | reg = <0x80000000 0x2000>; |
| 57 | }; |
| 58 | |
| 59 | hsadc@80002000 { |
| 60 | reg = <0x80002000 2000>; |
| 61 | interrupts = <13 87>; |
| 62 | status = "disabled"; |
| 63 | }; |
| 64 | |
| 65 | dma-apbh@80004000 { |
Dong Aisheng | 84f3570 | 2012-05-04 20:12:19 +0800 | [diff] [blame] | 66 | compatible = "fsl,imx28-dma-apbh"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 67 | reg = <0x80004000 2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | perfmon@80006000 { |
| 71 | reg = <0x80006000 800>; |
| 72 | interrupts = <27>; |
| 73 | status = "disabled"; |
| 74 | }; |
| 75 | |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 76 | gpmi-nand@8000c000 { |
| 77 | compatible = "fsl,imx28-gpmi-nand"; |
| 78 | #address-cells = <1>; |
| 79 | #size-cells = <1>; |
| 80 | reg = <0x8000c000 2000>, <0x8000a000 2000>; |
| 81 | reg-names = "gpmi-nand", "bch"; |
| 82 | interrupts = <88>, <41>; |
| 83 | interrupt-names = "gpmi-dma", "bch"; |
| 84 | fsl,gpmi-dma-channel = <4>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 85 | status = "disabled"; |
| 86 | }; |
| 87 | |
| 88 | ssp0: ssp@80010000 { |
| 89 | reg = <0x80010000 2000>; |
| 90 | interrupts = <96 82>; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 91 | fsl,ssp-dma-channel = <0>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 92 | status = "disabled"; |
| 93 | }; |
| 94 | |
| 95 | ssp1: ssp@80012000 { |
| 96 | reg = <0x80012000 2000>; |
| 97 | interrupts = <97 83>; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 98 | fsl,ssp-dma-channel = <1>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 99 | status = "disabled"; |
| 100 | }; |
| 101 | |
| 102 | ssp2: ssp@80014000 { |
| 103 | reg = <0x80014000 2000>; |
| 104 | interrupts = <98 84>; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 105 | fsl,ssp-dma-channel = <2>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 106 | status = "disabled"; |
| 107 | }; |
| 108 | |
| 109 | ssp3: ssp@80016000 { |
| 110 | reg = <0x80016000 2000>; |
| 111 | interrupts = <99 85>; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 112 | fsl,ssp-dma-channel = <3>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 113 | status = "disabled"; |
| 114 | }; |
| 115 | |
| 116 | pinctrl@80018000 { |
| 117 | #address-cells = <1>; |
| 118 | #size-cells = <0>; |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 119 | compatible = "fsl,imx28-pinctrl", "simple-bus"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 120 | reg = <0x80018000 2000>; |
| 121 | |
Shawn Guo | ce4c6f9 | 2012-05-04 14:32:35 +0800 | [diff] [blame] | 122 | gpio0: gpio@0 { |
| 123 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 124 | interrupts = <127>; |
| 125 | gpio-controller; |
| 126 | #gpio-cells = <2>; |
| 127 | interrupt-controller; |
| 128 | #interrupt-cells = <2>; |
| 129 | }; |
| 130 | |
| 131 | gpio1: gpio@1 { |
| 132 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 133 | interrupts = <126>; |
| 134 | gpio-controller; |
| 135 | #gpio-cells = <2>; |
| 136 | interrupt-controller; |
| 137 | #interrupt-cells = <2>; |
| 138 | }; |
| 139 | |
| 140 | gpio2: gpio@2 { |
| 141 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 142 | interrupts = <125>; |
| 143 | gpio-controller; |
| 144 | #gpio-cells = <2>; |
| 145 | interrupt-controller; |
| 146 | #interrupt-cells = <2>; |
| 147 | }; |
| 148 | |
| 149 | gpio3: gpio@3 { |
| 150 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 151 | interrupts = <124>; |
| 152 | gpio-controller; |
| 153 | #gpio-cells = <2>; |
| 154 | interrupt-controller; |
| 155 | #interrupt-cells = <2>; |
| 156 | }; |
| 157 | |
| 158 | gpio4: gpio@4 { |
| 159 | compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; |
| 160 | interrupts = <123>; |
| 161 | gpio-controller; |
| 162 | #gpio-cells = <2>; |
| 163 | interrupt-controller; |
| 164 | #interrupt-cells = <2>; |
| 165 | }; |
| 166 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 167 | duart_pins_a: duart@0 { |
| 168 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 169 | fsl,pinmux-ids = < |
| 170 | 0x3102 /* MX28_PAD_PWM0__DUART_RX */ |
| 171 | 0x3112 /* MX28_PAD_PWM1__DUART_TX */ |
| 172 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 173 | fsl,drive-strength = <0>; |
| 174 | fsl,voltage = <1>; |
| 175 | fsl,pull-up = <0>; |
| 176 | }; |
| 177 | |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 178 | duart_pins_b: duart@1 { |
| 179 | reg = <1>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 180 | fsl,pinmux-ids = < |
| 181 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ |
| 182 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ |
| 183 | >; |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 184 | fsl,drive-strength = <0>; |
| 185 | fsl,voltage = <1>; |
| 186 | fsl,pull-up = <0>; |
| 187 | }; |
| 188 | |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 189 | gpmi_pins_a: gpmi-nand@0 { |
| 190 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 191 | fsl,pinmux-ids = < |
| 192 | 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ |
| 193 | 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ |
| 194 | 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ |
| 195 | 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ |
| 196 | 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ |
| 197 | 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ |
| 198 | 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ |
| 199 | 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ |
| 200 | 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ |
| 201 | 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ |
| 202 | 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ |
| 203 | 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ |
| 204 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ |
| 205 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ |
| 206 | 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ |
| 207 | 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ |
| 208 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ |
| 209 | >; |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 210 | fsl,drive-strength = <0>; |
| 211 | fsl,voltage = <1>; |
| 212 | fsl,pull-up = <0>; |
| 213 | }; |
| 214 | |
| 215 | gpmi_status_cfg: gpmi-status-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 216 | fsl,pinmux-ids = < |
| 217 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ |
| 218 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ |
| 219 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ |
| 220 | >; |
Huang Shijie | 7a8e514 | 2012-05-25 17:25:35 +0800 | [diff] [blame] | 221 | fsl,drive-strength = <2>; |
| 222 | }; |
| 223 | |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 224 | auart0_pins_a: auart0@0 { |
| 225 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 226 | fsl,pinmux-ids = < |
| 227 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ |
| 228 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ |
| 229 | 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ |
| 230 | 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ |
| 231 | >; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 232 | fsl,drive-strength = <0>; |
| 233 | fsl,voltage = <1>; |
| 234 | fsl,pull-up = <0>; |
| 235 | }; |
| 236 | |
| 237 | auart3_pins_a: auart3@0 { |
| 238 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 239 | fsl,pinmux-ids = < |
| 240 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ |
| 241 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ |
| 242 | 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ |
| 243 | 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ |
| 244 | >; |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 245 | fsl,drive-strength = <0>; |
| 246 | fsl,voltage = <1>; |
| 247 | fsl,pull-up = <0>; |
| 248 | }; |
| 249 | |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 250 | mac0_pins_a: mac0@0 { |
| 251 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 252 | fsl,pinmux-ids = < |
| 253 | 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ |
| 254 | 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ |
| 255 | 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ |
| 256 | 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ |
| 257 | 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ |
| 258 | 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ |
| 259 | 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ |
| 260 | 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ |
| 261 | 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ |
| 262 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 263 | fsl,drive-strength = <1>; |
| 264 | fsl,voltage = <1>; |
| 265 | fsl,pull-up = <1>; |
| 266 | }; |
| 267 | |
| 268 | mac1_pins_a: mac1@0 { |
| 269 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 270 | fsl,pinmux-ids = < |
| 271 | 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ |
| 272 | 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ |
| 273 | 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ |
| 274 | 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ |
| 275 | 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ |
| 276 | 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ |
| 277 | >; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 278 | fsl,drive-strength = <1>; |
| 279 | fsl,voltage = <1>; |
| 280 | fsl,pull-up = <1>; |
| 281 | }; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 282 | |
| 283 | mmc0_8bit_pins_a: mmc0-8bit@0 { |
| 284 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 285 | fsl,pinmux-ids = < |
| 286 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ |
| 287 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ |
| 288 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ |
| 289 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ |
| 290 | 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ |
| 291 | 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ |
| 292 | 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ |
| 293 | 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ |
| 294 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ |
| 295 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 296 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 297 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 298 | fsl,drive-strength = <1>; |
| 299 | fsl,voltage = <1>; |
| 300 | fsl,pull-up = <1>; |
| 301 | }; |
| 302 | |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 303 | mmc0_4bit_pins_a: mmc0-4bit@0 { |
| 304 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 305 | fsl,pinmux-ids = < |
| 306 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ |
| 307 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ |
| 308 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ |
| 309 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ |
| 310 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ |
| 311 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 312 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 313 | >; |
Maxime Ripard | 8385e7c | 2012-06-27 10:18:11 +0200 | [diff] [blame] | 314 | fsl,drive-strength = <1>; |
| 315 | fsl,voltage = <1>; |
| 316 | fsl,pull-up = <1>; |
| 317 | }; |
| 318 | |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 319 | mmc0_cd_cfg: mmc0-cd-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 320 | fsl,pinmux-ids = < |
| 321 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ |
| 322 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 323 | fsl,pull-up = <0>; |
| 324 | }; |
| 325 | |
| 326 | mmc0_sck_cfg: mmc0-sck-cfg { |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 327 | fsl,pinmux-ids = < |
| 328 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ |
| 329 | >; |
Shawn Guo | 35d2304 | 2012-05-06 16:33:34 +0800 | [diff] [blame] | 330 | fsl,drive-strength = <2>; |
| 331 | fsl,pull-up = <0>; |
| 332 | }; |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 333 | |
| 334 | i2c0_pins_a: i2c0@0 { |
| 335 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 336 | fsl,pinmux-ids = < |
| 337 | 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ |
| 338 | 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ |
| 339 | >; |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 340 | fsl,drive-strength = <1>; |
| 341 | fsl,voltage = <1>; |
| 342 | fsl,pull-up = <1>; |
| 343 | }; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 344 | |
| 345 | saif0_pins_a: saif0@0 { |
| 346 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 347 | fsl,pinmux-ids = < |
| 348 | 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ |
| 349 | 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ |
| 350 | 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ |
| 351 | 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ |
| 352 | >; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 353 | fsl,drive-strength = <2>; |
| 354 | fsl,voltage = <1>; |
| 355 | fsl,pull-up = <1>; |
| 356 | }; |
| 357 | |
| 358 | saif1_pins_a: saif1@0 { |
| 359 | reg = <0>; |
Shawn Guo | f14da76 | 2012-06-28 11:44:57 +0800 | [diff] [blame] | 360 | fsl,pinmux-ids = < |
| 361 | 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ |
| 362 | >; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 363 | fsl,drive-strength = <2>; |
| 364 | fsl,voltage = <1>; |
| 365 | fsl,pull-up = <1>; |
| 366 | }; |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 367 | |
| 368 | pwm2_pins_a: pwm2@0 { |
| 369 | reg = <0>; |
| 370 | fsl,pinmux-ids = < |
| 371 | 0x3120 /* MX28_PAD_PWM2__PWM_2 */ |
| 372 | >; |
| 373 | fsl,drive-strength = <0>; |
| 374 | fsl,voltage = <1>; |
| 375 | fsl,pull-up = <0>; |
| 376 | }; |
Shawn Guo | a915ee42 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 377 | |
| 378 | lcdif_24bit_pins_a: lcdif-24bit@0 { |
| 379 | reg = <0>; |
| 380 | fsl,pinmux-ids = < |
| 381 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ |
| 382 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ |
| 383 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ |
| 384 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ |
| 385 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ |
| 386 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ |
| 387 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ |
| 388 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ |
| 389 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ |
| 390 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ |
| 391 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ |
| 392 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ |
| 393 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ |
| 394 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ |
| 395 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ |
| 396 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ |
| 397 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ |
| 398 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ |
| 399 | 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ |
| 400 | 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ |
| 401 | 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ |
| 402 | 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ |
| 403 | 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ |
| 404 | 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ |
| 405 | 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ |
| 406 | 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ |
| 407 | 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ |
| 408 | 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ |
| 409 | >; |
| 410 | fsl,drive-strength = <0>; |
| 411 | fsl,voltage = <1>; |
| 412 | fsl,pull-up = <0>; |
| 413 | }; |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame^] | 414 | |
| 415 | can0_pins_a: can0@0 { |
| 416 | reg = <0>; |
| 417 | fsl,pinmux-ids = < |
| 418 | 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ |
| 419 | 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ |
| 420 | >; |
| 421 | fsl,drive-strength = <0>; |
| 422 | fsl,voltage = <1>; |
| 423 | fsl,pull-up = <0>; |
| 424 | }; |
| 425 | |
| 426 | can1_pins_a: can1@0 { |
| 427 | reg = <0>; |
| 428 | fsl,pinmux-ids = < |
| 429 | 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ |
| 430 | 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ |
| 431 | >; |
| 432 | fsl,drive-strength = <0>; |
| 433 | fsl,voltage = <1>; |
| 434 | fsl,pull-up = <0>; |
| 435 | }; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 436 | }; |
| 437 | |
| 438 | digctl@8001c000 { |
| 439 | reg = <0x8001c000 2000>; |
| 440 | interrupts = <89>; |
| 441 | status = "disabled"; |
| 442 | }; |
| 443 | |
| 444 | etm@80022000 { |
| 445 | reg = <0x80022000 2000>; |
| 446 | status = "disabled"; |
| 447 | }; |
| 448 | |
| 449 | dma-apbx@80024000 { |
Dong Aisheng | 84f3570 | 2012-05-04 20:12:19 +0800 | [diff] [blame] | 450 | compatible = "fsl,imx28-dma-apbx"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 451 | reg = <0x80024000 2000>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 452 | }; |
| 453 | |
| 454 | dcp@80028000 { |
| 455 | reg = <0x80028000 2000>; |
| 456 | interrupts = <52 53 54>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
| 460 | pxp@8002a000 { |
| 461 | reg = <0x8002a000 2000>; |
| 462 | interrupts = <39>; |
| 463 | status = "disabled"; |
| 464 | }; |
| 465 | |
| 466 | ocotp@8002c000 { |
| 467 | reg = <0x8002c000 2000>; |
| 468 | status = "disabled"; |
| 469 | }; |
| 470 | |
| 471 | axi-ahb@8002e000 { |
| 472 | reg = <0x8002e000 2000>; |
| 473 | status = "disabled"; |
| 474 | }; |
| 475 | |
| 476 | lcdif@80030000 { |
Shawn Guo | a915ee42 | 2012-06-28 11:45:07 +0800 | [diff] [blame] | 477 | compatible = "fsl,imx28-lcdif"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 478 | reg = <0x80030000 2000>; |
| 479 | interrupts = <38 86>; |
| 480 | status = "disabled"; |
| 481 | }; |
| 482 | |
| 483 | can0: can@80032000 { |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame^] | 484 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 485 | reg = <0x80032000 2000>; |
| 486 | interrupts = <8>; |
| 487 | status = "disabled"; |
| 488 | }; |
| 489 | |
| 490 | can1: can@80034000 { |
Shawn Guo | 6ca44ac | 2012-06-28 11:45:03 +0800 | [diff] [blame^] | 491 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 492 | reg = <0x80034000 2000>; |
| 493 | interrupts = <9>; |
| 494 | status = "disabled"; |
| 495 | }; |
| 496 | |
| 497 | simdbg@8003c000 { |
| 498 | reg = <0x8003c000 200>; |
| 499 | status = "disabled"; |
| 500 | }; |
| 501 | |
| 502 | simgpmisel@8003c200 { |
| 503 | reg = <0x8003c200 100>; |
| 504 | status = "disabled"; |
| 505 | }; |
| 506 | |
| 507 | simsspsel@8003c300 { |
| 508 | reg = <0x8003c300 100>; |
| 509 | status = "disabled"; |
| 510 | }; |
| 511 | |
| 512 | simmemsel@8003c400 { |
| 513 | reg = <0x8003c400 100>; |
| 514 | status = "disabled"; |
| 515 | }; |
| 516 | |
| 517 | gpiomon@8003c500 { |
| 518 | reg = <0x8003c500 100>; |
| 519 | status = "disabled"; |
| 520 | }; |
| 521 | |
| 522 | simenet@8003c700 { |
| 523 | reg = <0x8003c700 100>; |
| 524 | status = "disabled"; |
| 525 | }; |
| 526 | |
| 527 | armjtag@8003c800 { |
| 528 | reg = <0x8003c800 100>; |
| 529 | status = "disabled"; |
| 530 | }; |
| 531 | }; |
| 532 | |
| 533 | apbx@80040000 { |
| 534 | compatible = "simple-bus"; |
| 535 | #address-cells = <1>; |
| 536 | #size-cells = <1>; |
| 537 | reg = <0x80040000 0x40000>; |
| 538 | ranges; |
| 539 | |
| 540 | clkctl@80040000 { |
| 541 | reg = <0x80040000 2000>; |
| 542 | status = "disabled"; |
| 543 | }; |
| 544 | |
| 545 | saif0: saif@80042000 { |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 546 | compatible = "fsl,imx28-saif"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 547 | reg = <0x80042000 2000>; |
| 548 | interrupts = <59 80>; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 549 | fsl,saif-dma-channel = <4>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 550 | status = "disabled"; |
| 551 | }; |
| 552 | |
| 553 | power@80044000 { |
| 554 | reg = <0x80044000 2000>; |
| 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | saif1: saif@80046000 { |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 559 | compatible = "fsl,imx28-saif"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 560 | reg = <0x80046000 2000>; |
| 561 | interrupts = <58 81>; |
Shawn Guo | 530f1d4 | 2012-05-10 15:03:16 +0800 | [diff] [blame] | 562 | fsl,saif-dma-channel = <5>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | lradc@80050000 { |
| 567 | reg = <0x80050000 2000>; |
| 568 | status = "disabled"; |
| 569 | }; |
| 570 | |
| 571 | spdif@80054000 { |
| 572 | reg = <0x80054000 2000>; |
| 573 | interrupts = <45 66>; |
| 574 | status = "disabled"; |
| 575 | }; |
| 576 | |
| 577 | rtc@80056000 { |
Shawn Guo | f98c990 | 2012-06-28 11:45:05 +0800 | [diff] [blame] | 578 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 579 | reg = <0x80056000 2000>; |
Shawn Guo | f98c990 | 2012-06-28 11:45:05 +0800 | [diff] [blame] | 580 | interrupts = <29>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 581 | }; |
| 582 | |
| 583 | i2c0: i2c@80058000 { |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 584 | #address-cells = <1>; |
| 585 | #size-cells = <0>; |
| 586 | compatible = "fsl,imx28-i2c"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 587 | reg = <0x80058000 2000>; |
| 588 | interrupts = <111 68>; |
| 589 | status = "disabled"; |
| 590 | }; |
| 591 | |
| 592 | i2c1: i2c@8005a000 { |
Shawn Guo | 2a96e39 | 2012-05-10 15:02:10 +0800 | [diff] [blame] | 593 | #address-cells = <1>; |
| 594 | #size-cells = <0>; |
| 595 | compatible = "fsl,imx28-i2c"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 596 | reg = <0x8005a000 2000>; |
| 597 | interrupts = <110 69>; |
| 598 | status = "disabled"; |
| 599 | }; |
| 600 | |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 601 | pwm: pwm@80064000 { |
| 602 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 603 | reg = <0x80064000 2000>; |
Shawn Guo | 52f7176 | 2012-06-28 11:45:06 +0800 | [diff] [blame] | 604 | #pwm-cells = <2>; |
| 605 | fsl,pwm-number = <8>; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 606 | status = "disabled"; |
| 607 | }; |
| 608 | |
| 609 | timrot@80068000 { |
| 610 | reg = <0x80068000 2000>; |
| 611 | status = "disabled"; |
| 612 | }; |
| 613 | |
| 614 | auart0: serial@8006a000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 615 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 616 | reg = <0x8006a000 0x2000>; |
| 617 | interrupts = <112 70 71>; |
| 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
| 621 | auart1: serial@8006c000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 622 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 623 | reg = <0x8006c000 0x2000>; |
| 624 | interrupts = <113 72 73>; |
| 625 | status = "disabled"; |
| 626 | }; |
| 627 | |
| 628 | auart2: serial@8006e000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 629 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 630 | reg = <0x8006e000 0x2000>; |
| 631 | interrupts = <114 74 75>; |
| 632 | status = "disabled"; |
| 633 | }; |
| 634 | |
| 635 | auart3: serial@80070000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 636 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 637 | reg = <0x80070000 0x2000>; |
| 638 | interrupts = <115 76 77>; |
| 639 | status = "disabled"; |
| 640 | }; |
| 641 | |
| 642 | auart4: serial@80072000 { |
Fabio Estevam | 80d969e | 2012-06-15 12:35:56 -0300 | [diff] [blame] | 643 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; |
Dong Aisheng | bc3a59c | 2012-03-31 21:26:57 +0800 | [diff] [blame] | 644 | reg = <0x80072000 0x2000>; |
| 645 | interrupts = <116 78 79>; |
| 646 | status = "disabled"; |
| 647 | }; |
| 648 | |
| 649 | duart: serial@80074000 { |
| 650 | compatible = "arm,pl011", "arm,primecell"; |
| 651 | reg = <0x80074000 0x1000>; |
| 652 | interrupts = <47>; |
| 653 | status = "disabled"; |
| 654 | }; |
| 655 | |
| 656 | usbphy0: usbphy@8007c000 { |
| 657 | reg = <0x8007c000 0x2000>; |
| 658 | status = "disabled"; |
| 659 | }; |
| 660 | |
| 661 | usbphy1: usbphy@8007e000 { |
| 662 | reg = <0x8007e000 0x2000>; |
| 663 | status = "disabled"; |
| 664 | }; |
| 665 | }; |
| 666 | }; |
| 667 | |
| 668 | ahb@80080000 { |
| 669 | compatible = "simple-bus"; |
| 670 | #address-cells = <1>; |
| 671 | #size-cells = <1>; |
| 672 | reg = <0x80080000 0x80000>; |
| 673 | ranges; |
| 674 | |
| 675 | usbctrl0: usbctrl@80080000 { |
| 676 | reg = <0x80080000 0x10000>; |
| 677 | status = "disabled"; |
| 678 | }; |
| 679 | |
| 680 | usbctrl1: usbctrl@80090000 { |
| 681 | reg = <0x80090000 0x10000>; |
| 682 | status = "disabled"; |
| 683 | }; |
| 684 | |
| 685 | dflpt@800c0000 { |
| 686 | reg = <0x800c0000 0x10000>; |
| 687 | status = "disabled"; |
| 688 | }; |
| 689 | |
| 690 | mac0: ethernet@800f0000 { |
| 691 | compatible = "fsl,imx28-fec"; |
| 692 | reg = <0x800f0000 0x4000>; |
| 693 | interrupts = <101>; |
| 694 | status = "disabled"; |
| 695 | }; |
| 696 | |
| 697 | mac1: ethernet@800f4000 { |
| 698 | compatible = "fsl,imx28-fec"; |
| 699 | reg = <0x800f4000 0x4000>; |
| 700 | interrupts = <102>; |
| 701 | status = "disabled"; |
| 702 | }; |
| 703 | |
| 704 | switch@800f8000 { |
| 705 | reg = <0x800f8000 0x8000>; |
| 706 | status = "disabled"; |
| 707 | }; |
| 708 | |
| 709 | }; |
| 710 | }; |