| Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Alex Deucher |
| 23 | */ |
| 24 | #ifndef CIK_H |
| 25 | #define CIK_H |
| 26 | |
| 27 | #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 |
| 28 | |
| 29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 |
| 30 | |
| 31 | #define DMIF_ADDR_CALC 0xC00 |
| 32 | |
| Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame^] | 33 | #define SRBM_STATUS2 0xE4C |
| 34 | #define SRBM_STATUS 0xE50 |
| 35 | |
| Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 36 | #define MC_SHARED_CHMAP 0x2004 |
| 37 | #define NOOFCHAN_SHIFT 12 |
| 38 | #define NOOFCHAN_MASK 0x0000f000 |
| 39 | #define MC_SHARED_CHREMAP 0x2008 |
| 40 | |
| 41 | #define MC_ARB_RAMCFG 0x2760 |
| 42 | #define NOOFBANK_SHIFT 0 |
| 43 | #define NOOFBANK_MASK 0x00000003 |
| 44 | #define NOOFRANK_SHIFT 2 |
| 45 | #define NOOFRANK_MASK 0x00000004 |
| 46 | #define NOOFROWS_SHIFT 3 |
| 47 | #define NOOFROWS_MASK 0x00000038 |
| 48 | #define NOOFCOLS_SHIFT 6 |
| 49 | #define NOOFCOLS_MASK 0x000000C0 |
| 50 | #define CHANSIZE_SHIFT 8 |
| 51 | #define CHANSIZE_MASK 0x00000100 |
| 52 | #define NOOFGROUPS_SHIFT 12 |
| 53 | #define NOOFGROUPS_MASK 0x00001000 |
| 54 | |
| 55 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 56 | #define HDP_NONSURFACE_BASE 0x2C04 |
| 57 | #define HDP_NONSURFACE_INFO 0x2C08 |
| 58 | #define HDP_NONSURFACE_SIZE 0x2C0C |
| 59 | |
| 60 | #define HDP_ADDR_CONFIG 0x2F48 |
| 61 | #define HDP_MISC_CNTL 0x2F4C |
| 62 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
| 63 | |
| 64 | #define BIF_FB_EN 0x5490 |
| 65 | #define FB_READ_EN (1 << 0) |
| 66 | #define FB_WRITE_EN (1 << 1) |
| 67 | |
| 68 | #define GRBM_CNTL 0x8000 |
| 69 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 70 | |
| Alex Deucher | 6f2043c | 2013-04-09 12:43:41 -0400 | [diff] [blame^] | 71 | #define GRBM_STATUS2 0x8008 |
| 72 | #define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F |
| 73 | #define ME0PIPE1_CF_RQ_PENDING (1 << 4) |
| 74 | #define ME0PIPE1_PF_RQ_PENDING (1 << 5) |
| 75 | #define ME1PIPE0_RQ_PENDING (1 << 6) |
| 76 | #define ME1PIPE1_RQ_PENDING (1 << 7) |
| 77 | #define ME1PIPE2_RQ_PENDING (1 << 8) |
| 78 | #define ME1PIPE3_RQ_PENDING (1 << 9) |
| 79 | #define ME2PIPE0_RQ_PENDING (1 << 10) |
| 80 | #define ME2PIPE1_RQ_PENDING (1 << 11) |
| 81 | #define ME2PIPE2_RQ_PENDING (1 << 12) |
| 82 | #define ME2PIPE3_RQ_PENDING (1 << 13) |
| 83 | #define RLC_RQ_PENDING (1 << 14) |
| 84 | #define RLC_BUSY (1 << 24) |
| 85 | #define TC_BUSY (1 << 25) |
| 86 | #define CPF_BUSY (1 << 28) |
| 87 | #define CPC_BUSY (1 << 29) |
| 88 | #define CPG_BUSY (1 << 30) |
| 89 | |
| 90 | #define GRBM_STATUS 0x8010 |
| 91 | #define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F |
| 92 | #define SRBM_RQ_PENDING (1 << 5) |
| 93 | #define ME0PIPE0_CF_RQ_PENDING (1 << 7) |
| 94 | #define ME0PIPE0_PF_RQ_PENDING (1 << 8) |
| 95 | #define GDS_DMA_RQ_PENDING (1 << 9) |
| 96 | #define DB_CLEAN (1 << 12) |
| 97 | #define CB_CLEAN (1 << 13) |
| 98 | #define TA_BUSY (1 << 14) |
| 99 | #define GDS_BUSY (1 << 15) |
| 100 | #define WD_BUSY_NO_DMA (1 << 16) |
| 101 | #define VGT_BUSY (1 << 17) |
| 102 | #define IA_BUSY_NO_DMA (1 << 18) |
| 103 | #define IA_BUSY (1 << 19) |
| 104 | #define SX_BUSY (1 << 20) |
| 105 | #define WD_BUSY (1 << 21) |
| 106 | #define SPI_BUSY (1 << 22) |
| 107 | #define BCI_BUSY (1 << 23) |
| 108 | #define SC_BUSY (1 << 24) |
| 109 | #define PA_BUSY (1 << 25) |
| 110 | #define DB_BUSY (1 << 26) |
| 111 | #define CP_COHERENCY_BUSY (1 << 28) |
| 112 | #define CP_BUSY (1 << 29) |
| 113 | #define CB_BUSY (1 << 30) |
| 114 | #define GUI_ACTIVE (1 << 31) |
| 115 | #define GRBM_STATUS_SE0 0x8014 |
| 116 | #define GRBM_STATUS_SE1 0x8018 |
| 117 | #define GRBM_STATUS_SE2 0x8038 |
| 118 | #define GRBM_STATUS_SE3 0x803C |
| 119 | #define SE_DB_CLEAN (1 << 1) |
| 120 | #define SE_CB_CLEAN (1 << 2) |
| 121 | #define SE_BCI_BUSY (1 << 22) |
| 122 | #define SE_VGT_BUSY (1 << 23) |
| 123 | #define SE_PA_BUSY (1 << 24) |
| 124 | #define SE_TA_BUSY (1 << 25) |
| 125 | #define SE_SX_BUSY (1 << 26) |
| 126 | #define SE_SPI_BUSY (1 << 27) |
| 127 | #define SE_SC_BUSY (1 << 29) |
| 128 | #define SE_DB_BUSY (1 << 30) |
| 129 | #define SE_CB_BUSY (1 << 31) |
| 130 | |
| 131 | #define GRBM_SOFT_RESET 0x8020 |
| 132 | #define SOFT_RESET_CP (1 << 0) /* All CP blocks */ |
| 133 | #define SOFT_RESET_RLC (1 << 2) /* RLC */ |
| 134 | #define SOFT_RESET_GFX (1 << 16) /* GFX */ |
| 135 | #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */ |
| 136 | #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */ |
| 137 | #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */ |
| 138 | |
| 139 | #define CP_MEC_CNTL 0x8234 |
| 140 | #define MEC_ME2_HALT (1 << 28) |
| 141 | #define MEC_ME1_HALT (1 << 30) |
| 142 | |
| 143 | #define CP_ME_CNTL 0x86D8 |
| 144 | #define CP_CE_HALT (1 << 24) |
| 145 | #define CP_PFP_HALT (1 << 26) |
| 146 | #define CP_ME_HALT (1 << 28) |
| 147 | |
| Alex Deucher | 8cc1a53 | 2013-04-09 12:41:24 -0400 | [diff] [blame] | 148 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 149 | #define MEQ1_START(x) ((x) << 0) |
| 150 | #define MEQ2_START(x) ((x) << 8) |
| 151 | |
| 152 | #define VGT_VTX_VECT_EJECT_REG 0x88B0 |
| 153 | |
| 154 | #define VGT_CACHE_INVALIDATION 0x88C4 |
| 155 | #define CACHE_INVALIDATION(x) ((x) << 0) |
| 156 | #define VC_ONLY 0 |
| 157 | #define TC_ONLY 1 |
| 158 | #define VC_AND_TC 2 |
| 159 | #define AUTO_INVLD_EN(x) ((x) << 6) |
| 160 | #define NO_AUTO 0 |
| 161 | #define ES_AUTO 1 |
| 162 | #define GS_AUTO 2 |
| 163 | #define ES_AND_GS_AUTO 3 |
| 164 | |
| 165 | #define VGT_GS_VERTEX_REUSE 0x88D4 |
| 166 | |
| 167 | #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc |
| 168 | #define INACTIVE_CUS_MASK 0xFFFF0000 |
| 169 | #define INACTIVE_CUS_SHIFT 16 |
| 170 | #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 |
| 171 | |
| 172 | #define PA_CL_ENHANCE 0x8A14 |
| 173 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
| 174 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
| 175 | |
| 176 | #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 |
| 177 | #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) |
| 178 | #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) |
| 179 | |
| 180 | #define PA_SC_FIFO_SIZE 0x8BCC |
| 181 | #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) |
| 182 | #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) |
| 183 | #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) |
| 184 | #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) |
| 185 | |
| 186 | #define PA_SC_ENHANCE 0x8BF0 |
| 187 | #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0) |
| 188 | #define DISABLE_PA_SC_GUIDANCE (1 << 13) |
| 189 | |
| 190 | #define SQ_CONFIG 0x8C00 |
| 191 | |
| 192 | #define SX_DEBUG_1 0x9060 |
| 193 | |
| 194 | #define SPI_CONFIG_CNTL 0x9100 |
| 195 | |
| 196 | #define SPI_CONFIG_CNTL_1 0x913C |
| 197 | #define VTX_DONE_DELAY(x) ((x) << 0) |
| 198 | #define INTERP_ONE_PRIM_PER_ROW (1 << 4) |
| 199 | |
| 200 | #define TA_CNTL_AUX 0x9508 |
| 201 | |
| 202 | #define DB_DEBUG 0x9830 |
| 203 | #define DB_DEBUG2 0x9834 |
| 204 | #define DB_DEBUG3 0x9838 |
| 205 | |
| 206 | #define CC_RB_BACKEND_DISABLE 0x98F4 |
| 207 | #define BACKEND_DISABLE(x) ((x) << 16) |
| 208 | #define GB_ADDR_CONFIG 0x98F8 |
| 209 | #define NUM_PIPES(x) ((x) << 0) |
| 210 | #define NUM_PIPES_MASK 0x00000007 |
| 211 | #define NUM_PIPES_SHIFT 0 |
| 212 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
| 213 | #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 |
| 214 | #define PIPE_INTERLEAVE_SIZE_SHIFT 4 |
| 215 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |
| 216 | #define NUM_SHADER_ENGINES_MASK 0x00003000 |
| 217 | #define NUM_SHADER_ENGINES_SHIFT 12 |
| 218 | #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) |
| 219 | #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 |
| 220 | #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 |
| 221 | #define ROW_SIZE(x) ((x) << 28) |
| 222 | #define ROW_SIZE_MASK 0x30000000 |
| 223 | #define ROW_SIZE_SHIFT 28 |
| 224 | |
| 225 | #define GB_TILE_MODE0 0x9910 |
| 226 | # define ARRAY_MODE(x) ((x) << 2) |
| 227 | # define ARRAY_LINEAR_GENERAL 0 |
| 228 | # define ARRAY_LINEAR_ALIGNED 1 |
| 229 | # define ARRAY_1D_TILED_THIN1 2 |
| 230 | # define ARRAY_2D_TILED_THIN1 4 |
| 231 | # define ARRAY_PRT_TILED_THIN1 5 |
| 232 | # define ARRAY_PRT_2D_TILED_THIN1 6 |
| 233 | # define PIPE_CONFIG(x) ((x) << 6) |
| 234 | # define ADDR_SURF_P2 0 |
| 235 | # define ADDR_SURF_P4_8x16 4 |
| 236 | # define ADDR_SURF_P4_16x16 5 |
| 237 | # define ADDR_SURF_P4_16x32 6 |
| 238 | # define ADDR_SURF_P4_32x32 7 |
| 239 | # define ADDR_SURF_P8_16x16_8x16 8 |
| 240 | # define ADDR_SURF_P8_16x32_8x16 9 |
| 241 | # define ADDR_SURF_P8_32x32_8x16 10 |
| 242 | # define ADDR_SURF_P8_16x32_16x16 11 |
| 243 | # define ADDR_SURF_P8_32x32_16x16 12 |
| 244 | # define ADDR_SURF_P8_32x32_16x32 13 |
| 245 | # define ADDR_SURF_P8_32x64_32x32 14 |
| 246 | # define TILE_SPLIT(x) ((x) << 11) |
| 247 | # define ADDR_SURF_TILE_SPLIT_64B 0 |
| 248 | # define ADDR_SURF_TILE_SPLIT_128B 1 |
| 249 | # define ADDR_SURF_TILE_SPLIT_256B 2 |
| 250 | # define ADDR_SURF_TILE_SPLIT_512B 3 |
| 251 | # define ADDR_SURF_TILE_SPLIT_1KB 4 |
| 252 | # define ADDR_SURF_TILE_SPLIT_2KB 5 |
| 253 | # define ADDR_SURF_TILE_SPLIT_4KB 6 |
| 254 | # define MICRO_TILE_MODE_NEW(x) ((x) << 22) |
| 255 | # define ADDR_SURF_DISPLAY_MICRO_TILING 0 |
| 256 | # define ADDR_SURF_THIN_MICRO_TILING 1 |
| 257 | # define ADDR_SURF_DEPTH_MICRO_TILING 2 |
| 258 | # define ADDR_SURF_ROTATED_MICRO_TILING 3 |
| 259 | # define SAMPLE_SPLIT(x) ((x) << 25) |
| 260 | # define ADDR_SURF_SAMPLE_SPLIT_1 0 |
| 261 | # define ADDR_SURF_SAMPLE_SPLIT_2 1 |
| 262 | # define ADDR_SURF_SAMPLE_SPLIT_4 2 |
| 263 | # define ADDR_SURF_SAMPLE_SPLIT_8 3 |
| 264 | |
| 265 | #define GB_MACROTILE_MODE0 0x9990 |
| 266 | # define BANK_WIDTH(x) ((x) << 0) |
| 267 | # define ADDR_SURF_BANK_WIDTH_1 0 |
| 268 | # define ADDR_SURF_BANK_WIDTH_2 1 |
| 269 | # define ADDR_SURF_BANK_WIDTH_4 2 |
| 270 | # define ADDR_SURF_BANK_WIDTH_8 3 |
| 271 | # define BANK_HEIGHT(x) ((x) << 2) |
| 272 | # define ADDR_SURF_BANK_HEIGHT_1 0 |
| 273 | # define ADDR_SURF_BANK_HEIGHT_2 1 |
| 274 | # define ADDR_SURF_BANK_HEIGHT_4 2 |
| 275 | # define ADDR_SURF_BANK_HEIGHT_8 3 |
| 276 | # define MACRO_TILE_ASPECT(x) ((x) << 4) |
| 277 | # define ADDR_SURF_MACRO_ASPECT_1 0 |
| 278 | # define ADDR_SURF_MACRO_ASPECT_2 1 |
| 279 | # define ADDR_SURF_MACRO_ASPECT_4 2 |
| 280 | # define ADDR_SURF_MACRO_ASPECT_8 3 |
| 281 | # define NUM_BANKS(x) ((x) << 6) |
| 282 | # define ADDR_SURF_2_BANK 0 |
| 283 | # define ADDR_SURF_4_BANK 1 |
| 284 | # define ADDR_SURF_8_BANK 2 |
| 285 | # define ADDR_SURF_16_BANK 3 |
| 286 | |
| 287 | #define CB_HW_CONTROL 0x9A10 |
| 288 | |
| 289 | #define GC_USER_RB_BACKEND_DISABLE 0x9B7C |
| 290 | #define BACKEND_DISABLE_MASK 0x00FF0000 |
| 291 | #define BACKEND_DISABLE_SHIFT 16 |
| 292 | |
| 293 | #define TCP_CHAN_STEER_LO 0xac0c |
| 294 | #define TCP_CHAN_STEER_HI 0xac10 |
| 295 | |
| 296 | #define PA_SC_RASTER_CONFIG 0x28350 |
| 297 | # define RASTER_CONFIG_RB_MAP_0 0 |
| 298 | # define RASTER_CONFIG_RB_MAP_1 1 |
| 299 | # define RASTER_CONFIG_RB_MAP_2 2 |
| 300 | # define RASTER_CONFIG_RB_MAP_3 3 |
| 301 | |
| 302 | #define GRBM_GFX_INDEX 0x30800 |
| 303 | #define INSTANCE_INDEX(x) ((x) << 0) |
| 304 | #define SH_INDEX(x) ((x) << 8) |
| 305 | #define SE_INDEX(x) ((x) << 16) |
| 306 | #define SH_BROADCAST_WRITES (1 << 29) |
| 307 | #define INSTANCE_BROADCAST_WRITES (1 << 30) |
| 308 | #define SE_BROADCAST_WRITES (1 << 31) |
| 309 | |
| 310 | #define VGT_ESGS_RING_SIZE 0x30900 |
| 311 | #define VGT_GSVS_RING_SIZE 0x30904 |
| 312 | #define VGT_PRIMITIVE_TYPE 0x30908 |
| 313 | #define VGT_INDEX_TYPE 0x3090C |
| 314 | |
| 315 | #define VGT_NUM_INDICES 0x30930 |
| 316 | #define VGT_NUM_INSTANCES 0x30934 |
| 317 | #define VGT_TF_RING_SIZE 0x30938 |
| 318 | #define VGT_HS_OFFCHIP_PARAM 0x3093C |
| 319 | #define VGT_TF_MEMORY_BASE 0x30940 |
| 320 | |
| 321 | #define PA_SU_LINE_STIPPLE_VALUE 0x30a00 |
| 322 | #define PA_SC_LINE_STIPPLE_STATE 0x30a04 |
| 323 | |
| 324 | #define SQC_CACHES 0x30d20 |
| 325 | |
| 326 | #define CP_PERFMON_CNTL 0x36020 |
| 327 | |
| 328 | #define CGTS_TCC_DISABLE 0x3c00c |
| 329 | #define CGTS_USER_TCC_DISABLE 0x3c010 |
| 330 | #define TCC_DISABLE_MASK 0xFFFF0000 |
| 331 | #define TCC_DISABLE_SHIFT 16 |
| 332 | |
| 333 | #endif |