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gerrit-public.fairphone.software / kernel / msm-5.4 / 1b14f3a57b0a1a9e0ca7091ca9f8c14fe23dfd70 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 767803e1fd55f2d6e75053527e47a26d536e4f77 [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]7 aliases {
8 serial0 = &uarta;
9 serial1 = &uartb;
10 serial2 = &uartc;
11 serial3 = &uartd;
12 serial4 = &uarte;
13 };
14
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]15 host1x {
16 compatible = "nvidia,tegra30-host1x", "simple-bus";
17 reg = <0x50000000 0x00024000>;
18 interrupts = <0 65 0x04 /* mpcore syncpt */
19 0 67 0x04>; /* mpcore general */
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]20 clocks = <&tegra_car 28>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x04000000>;
26
27 mpe {
28 compatible = "nvidia,tegra30-mpe";
29 reg = <0x54040000 0x00040000>;
30 interrupts = <0 68 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]31 clocks = <&tegra_car 60>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]32 };
33
34 vi {
35 compatible = "nvidia,tegra30-vi";
36 reg = <0x54080000 0x00040000>;
37 interrupts = <0 69 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]38 clocks = <&tegra_car 164>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]39 };
40
41 epp {
42 compatible = "nvidia,tegra30-epp";
43 reg = <0x540c0000 0x00040000>;
44 interrupts = <0 70 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]45 clocks = <&tegra_car 19>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]46 };
47
48 isp {
49 compatible = "nvidia,tegra30-isp";
50 reg = <0x54100000 0x00040000>;
51 interrupts = <0 71 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]52 clocks = <&tegra_car 23>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]53 };
54
55 gr2d {
56 compatible = "nvidia,tegra30-gr2d";
57 reg = <0x54140000 0x00040000>;
58 interrupts = <0 72 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]59 clocks = <&tegra_car 21>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]60 };
61
62 gr3d {
63 compatible = "nvidia,tegra30-gr3d";
64 reg = <0x54180000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]65 clocks = <&tegra_car 24 &tegra_car 98>;
66 clock-names = "3d", "3d2";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]67 };
68
69 dc@54200000 {
70 compatible = "nvidia,tegra30-dc";
71 reg = <0x54200000 0x00040000>;
72 interrupts = <0 73 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]73 clocks = <&tegra_car 27>, <&tegra_car 179>;
74 clock-names = "disp1", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]75
76 rgb {
77 status = "disabled";
78 };
79 };
80
81 dc@54240000 {
82 compatible = "nvidia,tegra30-dc";
83 reg = <0x54240000 0x00040000>;
84 interrupts = <0 74 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]85 clocks = <&tegra_car 26>, <&tegra_car 179>;
86 clock-names = "disp2", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]87
88 rgb {
89 status = "disabled";
90 };
91 };
92
93 hdmi {
94 compatible = "nvidia,tegra30-hdmi";
95 reg = <0x54280000 0x00040000>;
96 interrupts = <0 75 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]97 clocks = <&tegra_car 51>, <&tegra_car 189>;
98 clock-names = "hdmi", "parent";
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]99 status = "disabled";
100 };
101
102 tvo {
103 compatible = "nvidia,tegra30-tvo";
104 reg = <0x542c0000 0x00040000>;
105 interrupts = <0 76 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]106 clocks = <&tegra_car 169>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]107 status = "disabled";
108 };
109
110 dsi {
111 compatible = "nvidia,tegra30-dsi";
112 reg = <0x54300000 0x00040000>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]113 clocks = <&tegra_car 48>;
Thierry Redinged390972012-11-15 22:07:57 +0100[diff] [blame]114 status = "disabled";
115 };
116 };
117
Stephen Warren73368ba2012-09-19 14:17:24 -0600[diff] [blame]118 timer@50004600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x50040600 0x20>;
121 interrupts = <1 13 0xf04>;
122 };
123
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]124 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]125 compatible = "arm,cortex-a9-gic";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]126 reg = <0x50041000 0x1000
127 0x50040100 0x0100>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]128 interrupt-controller;
129 #interrupt-cells = <3>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]130 };
131
Stephen Warrenbb2c1de2013-01-14 10:09:16 -0700[diff] [blame]132 cache-controller {
133 compatible = "arm,pl310-cache";
134 reg = <0x50043000 0x1000>;
135 arm,data-latency = <6 6 2>;
136 arm,tag-latency = <5 5 2>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
Stephen Warren2f2b7fb2012-09-19 12:02:31 -0600[diff] [blame]141 timer@60005000 {
142 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
143 reg = <0x60005000 0x400>;
144 interrupts = <0 0 0x04
145 0 1 0x04
146 0 41 0x04
147 0 42 0x04
148 0 121 0x04
149 0 122 0x04>;
150 };
151
Prashant Gaikwad95985662013-01-11 13:16:23 +0530[diff] [blame]152 tegra_car: clock {
153 compatible = "nvidia,tegra30-car";
154 reg = <0x60006000 0x1000>;
155 #clock-cells = <1>;
156 };
157
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]158 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]159 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
160 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]161 interrupts = <0 104 0x04
162 0 105 0x04
163 0 106 0x04
164 0 107 0x04
165 0 108 0x04
166 0 109 0x04
167 0 110 0x04
168 0 111 0x04
169 0 112 0x04
170 0 113 0x04
171 0 114 0x04
172 0 115 0x04
173 0 116 0x04
174 0 117 0x04
175 0 118 0x04
176 0 119 0x04
177 0 128 0x04
178 0 129 0x04
179 0 130 0x04
180 0 131 0x04
181 0 132 0x04
182 0 133 0x04
183 0 134 0x04
184 0 135 0x04
185 0 136 0x04
186 0 137 0x04
187 0 138 0x04
188 0 139 0x04
189 0 140 0x04
190 0 141 0x04
191 0 142 0x04
192 0 143 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]193 clocks = <&tegra_car 34>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]194 };
195
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]196 ahb: ahb {
197 compatible = "nvidia,tegra30-ahb";
198 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
199 };
200
201 gpio: gpio {
Laxman Dewangan35f210e2012-12-19 20:27:12 +0530[diff] [blame]202 compatible = "nvidia,tegra30-gpio";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]203 reg = <0x6000d000 0x1000>;
204 interrupts = <0 32 0x04
205 0 33 0x04
206 0 34 0x04
207 0 35 0x04
208 0 55 0x04
209 0 87 0x04
210 0 89 0x04
211 0 125 0x04>;
212 #gpio-cells = <2>;
213 gpio-controller;
214 #interrupt-cells = <2>;
215 interrupt-controller;
216 };
217
218 pinmux: pinmux {
219 compatible = "nvidia,tegra30-pinmux";
Pritesh Raithatha322337b2012-10-30 15:37:09 +0530[diff] [blame]220 reg = <0x70000868 0xd4 /* Pad control registers */
221 0x70003000 0x3e4>; /* Mux registers */
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]222 };
223
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]224 /*
225 * There are two serial driver i.e. 8250 based simple serial
226 * driver and APB DMA based serial driver for higher baudrate
227 * and performace. To enable the 8250 based driver, the compatible
228 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
229 * the APB DMA based serial driver, the comptible is
230 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
231 */
232 uarta: serial@70006000 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]233 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
234 reg = <0x70006000 0x40>;
235 reg-shift = <2>;
236 interrupts = <0 36 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]237 nvidia,dma-request-selector = <&apbdma 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]238 clocks = <&tegra_car 6>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]239 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]240 };
241
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]242 uartb: serial@70006040 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]243 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
244 reg = <0x70006040 0x40>;
245 reg-shift = <2>;
246 interrupts = <0 37 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]247 nvidia,dma-request-selector = <&apbdma 9>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]248 clocks = <&tegra_car 160>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]249 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]250 };
251
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]252 uartc: serial@70006200 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]253 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
254 reg = <0x70006200 0x100>;
255 reg-shift = <2>;
256 interrupts = <0 46 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]257 nvidia,dma-request-selector = <&apbdma 10>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]258 clocks = <&tegra_car 55>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]259 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]260 };
261
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]262 uartd: serial@70006300 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]263 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
264 reg = <0x70006300 0x100>;
265 reg-shift = <2>;
266 interrupts = <0 90 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]267 nvidia,dma-request-selector = <&apbdma 19>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]268 clocks = <&tegra_car 65>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]269 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]270 };
271
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]272 uarte: serial@70006400 {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]273 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
274 reg = <0x70006400 0x100>;
275 reg-shift = <2>;
276 interrupts = <0 91 0x04>;
Laxman Dewanganb6551bb2012-12-19 12:01:11 +0530[diff] [blame]277 nvidia,dma-request-selector = <&apbdma 20>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]278 clocks = <&tegra_car 66>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]279 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]280 };
281
Thierry Reding2b8b15d2012-09-20 17:06:05 +0200[diff] [blame]282 pwm: pwm {
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]283 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
284 reg = <0x7000a000 0x100>;
285 #pwm-cells = <2>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]286 clocks = <&tegra_car 17>;
Thierry Reding140fd972011-12-21 08:04:13 +0100[diff] [blame]287 };
288
Stephen Warren380e04a2012-09-19 12:13:16 -0600[diff] [blame]289 rtc {
290 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
291 reg = <0x7000e000 0x100>;
292 interrupts = <0 2 0x04>;
293 };
294
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]295 i2c@7000c000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]296 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]297 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]298 interrupts = <0 38 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]299 #address-cells = <1>;
300 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]301 clocks = <&tegra_car 12>, <&tegra_car 182>;
302 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]303 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]304 };
305
306 i2c@7000c400 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]307 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]308 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]309 interrupts = <0 84 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]310 #address-cells = <1>;
311 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]312 clocks = <&tegra_car 54>, <&tegra_car 182>;
313 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]314 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]315 };
316
317 i2c@7000c500 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]318 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]319 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]320 interrupts = <0 92 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]321 #address-cells = <1>;
322 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]323 clocks = <&tegra_car 67>, <&tegra_car 182>;
324 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]325 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]326 };
327
328 i2c@7000c700 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]329 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
330 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]331 interrupts = <0 120 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]332 #address-cells = <1>;
333 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]334 clocks = <&tegra_car 103>, <&tegra_car 182>;
335 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]336 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]337 };
338
339 i2c@7000d000 {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]340 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]341 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]342 interrupts = <0 53 0x04>;
Stephen Warren2eaab062012-05-11 17:12:52 -0600[diff] [blame]343 #address-cells = <1>;
344 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]345 clocks = <&tegra_car 47>, <&tegra_car 182>;
346 clock-names = "div-clk", "fast-clk";
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]347 status = "disabled";
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]348 };
349
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]350 spi@7000d400 {
351 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
352 reg = <0x7000d400 0x200>;
353 interrupts = <0 59 0x04>;
354 nvidia,dma-request-selector = <&apbdma 15>;
355 #address-cells = <1>;
356 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]357 clocks = <&tegra_car 41>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]358 status = "disabled";
359 };
360
361 spi@7000d600 {
362 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
363 reg = <0x7000d600 0x200>;
364 interrupts = <0 82 0x04>;
365 nvidia,dma-request-selector = <&apbdma 16>;
366 #address-cells = <1>;
367 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]368 clocks = <&tegra_car 44>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]369 status = "disabled";
370 };
371
372 spi@7000d800 {
373 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
374 reg = <0x7000d480 0x200>;
375 interrupts = <0 83 0x04>;
376 nvidia,dma-request-selector = <&apbdma 17>;
377 #address-cells = <1>;
378 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]379 clocks = <&tegra_car 46>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]380 status = "disabled";
381 };
382
383 spi@7000da00 {
384 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
385 reg = <0x7000da00 0x200>;
386 interrupts = <0 93 0x04>;
387 nvidia,dma-request-selector = <&apbdma 18>;
388 #address-cells = <1>;
389 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]390 clocks = <&tegra_car 68>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]391 status = "disabled";
392 };
393
394 spi@7000dc00 {
395 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
396 reg = <0x7000dc00 0x200>;
397 interrupts = <0 94 0x04>;
398 nvidia,dma-request-selector = <&apbdma 27>;
399 #address-cells = <1>;
400 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]401 clocks = <&tegra_car 104>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]402 status = "disabled";
403 };
404
405 spi@7000de00 {
406 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
407 reg = <0x7000de00 0x200>;
408 interrupts = <0 79 0x04>;
409 nvidia,dma-request-selector = <&apbdma 28>;
410 #address-cells = <1>;
411 #size-cells = <0>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]412 clocks = <&tegra_car 105>;
Laxman Dewangana86b0db2012-10-30 12:35:23 +0530[diff] [blame]413 status = "disabled";
414 };
415
Laxman Dewangan699ed4b2013-01-11 19:03:03 +0530[diff] [blame]416 kbc {
417 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
418 reg = <0x7000e200 0x100>;
419 interrupts = <0 85 0x04>;
420 clocks = <&tegra_car 36>;
421 status = "disabled";
422 };
423
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]424 pmc {
425 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
426 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]427 };
428
hdoyu@nvidia.coma9140aa2012-05-16 19:47:44 +0000[diff] [blame]429 memory-controller {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]430 compatible = "nvidia,tegra30-mc";
431 reg = <0x7000f000 0x010
432 0x7000f03c 0x1b4
433 0x7000f200 0x028
434 0x7000f284 0x17c>;
435 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]436 };
437
Hiroshi Doyu3fbf07d2013-01-29 10:30:29 +0200[diff] [blame]438 iommu {
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]439 compatible = "nvidia,tegra30-smmu";
440 reg = <0x7000f010 0x02c
441 0x7000f1f0 0x010
442 0x7000f228 0x05c>;
443 nvidia,#asids = <4>; /* # of ASIDs */
444 dma-window = <0 0x40000000>; /* IOVA start & length */
445 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]446 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]447
448 ahub {
449 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]450 reg = <0x70080000 0x200
451 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]452 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]453 nvidia,dma-request-selector = <&apbdma 1>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]454 clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
455 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
456 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
457 <&tegra_car 110>, <&tegra_car 162>;
458 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
459 "i2s3", "i2s4", "dam0", "dam1", "dam2",
460 "spdif_in";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]461 ranges;
462 #address-cells = <1>;
463 #size-cells = <1>;
464
465 tegra_i2s0: i2s@70080300 {
466 compatible = "nvidia,tegra30-i2s";
467 reg = <0x70080300 0x100>;
468 nvidia,ahub-cif-ids = <4 4>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]469 clocks = <&tegra_car 30>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]470 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]471 };
472
473 tegra_i2s1: i2s@70080400 {
474 compatible = "nvidia,tegra30-i2s";
475 reg = <0x70080400 0x100>;
476 nvidia,ahub-cif-ids = <5 5>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]477 clocks = <&tegra_car 11>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]478 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]479 };
480
481 tegra_i2s2: i2s@70080500 {
482 compatible = "nvidia,tegra30-i2s";
483 reg = <0x70080500 0x100>;
484 nvidia,ahub-cif-ids = <6 6>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]485 clocks = <&tegra_car 18>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]486 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]487 };
488
489 tegra_i2s3: i2s@70080600 {
490 compatible = "nvidia,tegra30-i2s";
491 reg = <0x70080600 0x100>;
492 nvidia,ahub-cif-ids = <7 7>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]493 clocks = <&tegra_car 101>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]494 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]495 };
496
497 tegra_i2s4: i2s@70080700 {
498 compatible = "nvidia,tegra30-i2s";
499 reg = <0x70080700 0x100>;
500 nvidia,ahub-cif-ids = <8 8>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]501 clocks = <&tegra_car 102>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]502 status = "disabled";
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]503 };
504 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]505
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]506 sdhci@78000000 {
507 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
508 reg = <0x78000000 0x200>;
509 interrupts = <0 14 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]510 clocks = <&tegra_car 14>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]511 status = "disabled";
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]512 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]513
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]514 sdhci@78000200 {
515 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
516 reg = <0x78000200 0x200>;
517 interrupts = <0 15 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]518 clocks = <&tegra_car 9>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]519 status = "disabled";
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]520 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]521
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]522 sdhci@78000400 {
523 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
524 reg = <0x78000400 0x200>;
525 interrupts = <0 19 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]526 clocks = <&tegra_car 69>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]527 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]528 };
529
530 sdhci@78000600 {
531 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
532 reg = <0x78000600 0x200>;
533 interrupts = <0 31 0x04>;
Prashant Gaikwad1cbc7332013-01-11 13:31:22 +0530[diff] [blame]534 clocks = <&tegra_car 15>;
Roland Stigge223ef782012-06-11 21:09:45 +0200[diff] [blame]535 status = "disabled";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]536 };
537
Hiroshi Doyu7d19a342013-01-11 15:11:54 +0200[diff] [blame]538 cpus {
539 #address-cells = <1>;
540 #size-cells = <0>;
541
542 cpu@0 {
543 device_type = "cpu";
544 compatible = "arm,cortex-a9";
545 reg = <0>;
546 };
547
548 cpu@1 {
549 device_type = "cpu";
550 compatible = "arm,cortex-a9";
551 reg = <1>;
552 };
553
554 cpu@2 {
555 device_type = "cpu";
556 compatible = "arm,cortex-a9";
557 reg = <2>;
558 };
559
560 cpu@3 {
561 device_type = "cpu";
562 compatible = "arm,cortex-a9";
563 reg = <3>;
564 };
565 };
566
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]567 pmu {
568 compatible = "arm,cortex-a9-pmu";
569 interrupts = <0 144 0x04
570 0 145 0x04
571 0 146 0x04
572 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]573 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]574};