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gerrit-public.fairphone.software / kernel / msm-5.4 / c04abb3a07b56db4756b6f970609e65a8624b0a3 / . / arch / arm / boot / dts / tegra30.dtsi
blob: 9fb47adc935d748c1c7cb5398675f22ae0d89fca [file] [log] [blame]
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
6
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]7 intc: interrupt-controller {
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]8 compatible = "arm,cortex-a9-gic";
9 interrupt-controller;
10 #interrupt-cells = <3>;
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]11 reg = <0x50041000 0x1000
12 0x50040100 0x0100>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]16 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1400>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]18 interrupts = <0 104 0x04
19 0 105 0x04
20 0 106 0x04
21 0 107 0x04
22 0 108 0x04
23 0 109 0x04
24 0 110 0x04
25 0 111 0x04
26 0 112 0x04
27 0 113 0x04
28 0 114 0x04
29 0 115 0x04
30 0 116 0x04
31 0 117 0x04
32 0 118 0x04
33 0 119 0x04
34 0 128 0x04
35 0 129 0x04
36 0 130 0x04
37 0 131 0x04
38 0 132 0x04
39 0 133 0x04
40 0 134 0x04
41 0 135 0x04
42 0 136 0x04
43 0 137 0x04
44 0 138 0x04
45 0 139 0x04
46 0 140 0x04
47 0 141 0x04
48 0 142 0x04
49 0 143 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]50 };
51
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]52 ahb: ahb {
53 compatible = "nvidia,tegra30-ahb";
54 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
55 };
56
57 gpio: gpio {
58 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
59 reg = <0x6000d000 0x1000>;
60 interrupts = <0 32 0x04
61 0 33 0x04
62 0 34 0x04
63 0 35 0x04
64 0 55 0x04
65 0 87 0x04
66 0 89 0x04
67 0 125 0x04>;
68 #gpio-cells = <2>;
69 gpio-controller;
70 #interrupt-cells = <2>;
71 interrupt-controller;
72 };
73
74 pinmux: pinmux {
75 compatible = "nvidia,tegra30-pinmux";
76 reg = <0x70000868 0xd0 /* Pad control registers */
77 0x70003000 0x3e0>; /* Mux registers */
78 };
79
80 serial@70006000 {
81 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
82 reg = <0x70006000 0x40>;
83 reg-shift = <2>;
84 interrupts = <0 36 0x04>;
85 };
86
87 serial@70006040 {
88 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
89 reg = <0x70006040 0x40>;
90 reg-shift = <2>;
91 interrupts = <0 37 0x04>;
92 };
93
94 serial@70006200 {
95 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
96 reg = <0x70006200 0x100>;
97 reg-shift = <2>;
98 interrupts = <0 46 0x04>;
99 };
100
101 serial@70006300 {
102 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
103 reg = <0x70006300 0x100>;
104 reg-shift = <2>;
105 interrupts = <0 90 0x04>;
106 };
107
108 serial@70006400 {
109 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
110 reg = <0x70006400 0x100>;
111 reg-shift = <2>;
112 interrupts = <0 91 0x04>;
113 };
114
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]115 i2c@7000c000 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]119 reg = <0x7000c000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]120 interrupts = <0 38 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]121 };
122
123 i2c@7000c400 {
124 #address-cells = <1>;
125 #size-cells = <0>;
126 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]127 reg = <0x7000c400 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]128 interrupts = <0 84 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]129 };
130
131 i2c@7000c500 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]135 reg = <0x7000c500 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]136 interrupts = <0 92 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]137 };
138
139 i2c@7000c700 {
140 #address-cells = <1>;
141 #size-cells = <0>;
142 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
143 reg = <0x7000c700 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]144 interrupts = <0 120 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]145 };
146
147 i2c@7000d000 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
Stephen Warrenba04c282012-05-11 16:28:59 -0600[diff] [blame]151 reg = <0x7000d000 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]152 interrupts = <0 53 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]153 };
154
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]155 pmc {
156 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
157 reg = <0x7000e400 0x400>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]158 };
159
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]160 mc {
161 compatible = "nvidia,tegra30-mc";
162 reg = <0x7000f000 0x010
163 0x7000f03c 0x1b4
164 0x7000f200 0x028
165 0x7000f284 0x17c>;
166 interrupts = <0 77 0x04>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]167 };
168
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]169 smmu {
170 compatible = "nvidia,tegra30-smmu";
171 reg = <0x7000f010 0x02c
172 0x7000f1f0 0x010
173 0x7000f228 0x05c>;
174 nvidia,#asids = <4>; /* # of ASIDs */
175 dma-window = <0 0x40000000>; /* IOVA start & length */
176 nvidia,ahb = <&ahb>;
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]177 };
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]178
179 ahub {
180 compatible = "nvidia,tegra30-ahub";
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]181 reg = <0x70080000 0x200
182 0x70080200 0x100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]183 interrupts = <0 103 0x04>;
Stephen Warren9ee6a5c2012-03-27 12:40:53 -0600[diff] [blame]184 nvidia,dma-request-selector = <&apbdma 1>;
185
186 ranges;
187 #address-cells = <1>;
188 #size-cells = <1>;
189
190 tegra_i2s0: i2s@70080300 {
191 compatible = "nvidia,tegra30-i2s";
192 reg = <0x70080300 0x100>;
193 nvidia,ahub-cif-ids = <4 4>;
194 };
195
196 tegra_i2s1: i2s@70080400 {
197 compatible = "nvidia,tegra30-i2s";
198 reg = <0x70080400 0x100>;
199 nvidia,ahub-cif-ids = <5 5>;
200 };
201
202 tegra_i2s2: i2s@70080500 {
203 compatible = "nvidia,tegra30-i2s";
204 reg = <0x70080500 0x100>;
205 nvidia,ahub-cif-ids = <6 6>;
206 };
207
208 tegra_i2s3: i2s@70080600 {
209 compatible = "nvidia,tegra30-i2s";
210 reg = <0x70080600 0x100>;
211 nvidia,ahub-cif-ids = <7 7>;
212 };
213
214 tegra_i2s4: i2s@70080700 {
215 compatible = "nvidia,tegra30-i2s";
216 reg = <0x70080700 0x100>;
217 nvidia,ahub-cif-ids = <8 8>;
218 };
219 };
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]220
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]221 sdhci@78000000 {
222 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
223 reg = <0x78000000 0x200>;
224 interrupts = <0 14 0x04>;
Hiroshi DOYU7868a9b2012-05-07 09:43:47 +0300[diff] [blame]225 };
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]226
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]227 sdhci@78000200 {
228 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
229 reg = <0x78000200 0x200>;
230 interrupts = <0 15 0x04>;
hdoyu@nvidia.comecf43742012-05-09 21:42:33 +0000[diff] [blame]231 };
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]232
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]233 sdhci@78000400 {
234 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
235 reg = <0x78000400 0x200>;
236 interrupts = <0 19 0x04>;
237 };
238
239 sdhci@78000600 {
240 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
241 reg = <0x78000600 0x200>;
242 interrupts = <0 31 0x04>;
243 };
244
245 pmu {
246 compatible = "arm,cortex-a9-pmu";
247 interrupts = <0 144 0x04
248 0 145 0x04
249 0 146 0x04
250 0 147 0x04>;
hdoyu@nvidia.com54174a32012-05-09 21:50:21 +0000[diff] [blame]251 };
Peter De Schrijverc3e00a02011-12-14 17:03:13 +0200[diff] [blame]252};