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Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -03001#define EM_GPIO_0 (1 << 0)
2#define EM_GPIO_1 (1 << 1)
3#define EM_GPIO_2 (1 << 2)
4#define EM_GPIO_3 (1 << 3)
5#define EM_GPIO_4 (1 << 4)
6#define EM_GPIO_5 (1 << 5)
7#define EM_GPIO_6 (1 << 6)
8#define EM_GPIO_7 (1 << 7)
9
10#define EM_GPO_0 (1 << 0)
11#define EM_GPO_1 (1 << 1)
12#define EM_GPO_2 (1 << 2)
13#define EM_GPO_3 (1 << 3)
14
15/* em2800 registers */
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030016#define EM2800_R08_AUDIOSRC 0x08
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030017
18/* em28xx registers */
19
20 /* GPIO/GPO registers */
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030021#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
22#define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030023
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030024#define EM28XX_R06_I2C_CLK 0x06
25#define EM28XX_R0A_CHIPID 0x0a
26#define EM28XX_R0C_USBSUSP 0x0c /* */
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030027
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030028#define EM28XX_R0E_AUDIOSRC 0x0e
29#define EM28XX_R0F_XCLK 0x0f
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030030
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030031#define EM28XX_R10_VINMODE 0x10
32#define EM28XX_R11_VINCTRL 0x11
33#define EM28XX_R12_VINENABLE 0x12 /* */
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030034
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030035#define EM28XX_R14_GAMMA 0x14
36#define EM28XX_R15_RGAIN 0x15
37#define EM28XX_R16_GGAIN 0x16
38#define EM28XX_R17_BGAIN 0x17
39#define EM28XX_R18_ROFFSET 0x18
40#define EM28XX_R19_GOFFSET 0x19
41#define EM28XX_R1A_BOFFSET 0x1a
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030042
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030043#define EM28XX_R1B_OFLOW 0x1b
44#define EM28XX_R1C_HSTART 0x1c
45#define EM28XX_R1D_VSTART 0x1d
46#define EM28XX_R1E_CWIDTH 0x1e
47#define EM28XX_R1F_CHEIGHT 0x1f
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030048
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030049#define EM28XX_R20_YGAIN 0x20
50#define EM28XX_R21_YOFFSET 0x21
51#define EM28XX_R22_UVGAIN 0x22
52#define EM28XX_R23_UOFFSET 0x23
53#define EM28XX_R24_VOFFSET 0x24
54#define EM28XX_R25_SHARPNESS 0x25
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030055
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030056#define EM28XX_R26_COMPR 0x26
57#define EM28XX_R27_OUTFMT 0x27
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030058
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030059#define EM28XX_R28_XMIN 0x28
60#define EM28XX_R29_XMAX 0x29
61#define EM28XX_R2A_YMIN 0x2a
62#define EM28XX_R2B_YMAX 0x2b
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030063
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030064#define EM28XX_R30_HSCALELOW 0x30
65#define EM28XX_R31_HSCALEHIGH 0x31
66#define EM28XX_R32_VSCALELOW 0x32
67#define EM28XX_R33_VSCALEHIGH 0x33
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030068
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030069#define EM28XX_R40_AC97LSB 0x40
70#define EM28XX_R41_AC97MSB 0x41
71#define EM28XX_R42_AC97ADDR 0x42
72#define EM28XX_R43_AC97BUSY 0x43
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030073
Mauro Carvalho Chehaba924a492008-11-12 08:41:29 -030074#define EM28XX_R45_IR 0x45
75 /* 0x45 bit 7 - parity bit
76 bits 6-0 - count
77 0x46 IR brand
78 0x47 IR data
79 */
80
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030081/* em202 registers */
Mauro Carvalho Chehab41facaa2008-04-17 21:44:58 -030082#define EM28XX_R02_MASTER_AC97 0x02
83#define EM28XX_R10_LINE_IN_AC97 0x10
84#define EM28XX_R14_VIDEO_AC97 0x14
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -030085
Devin Heitmueller6a1acc32008-11-12 02:05:06 -030086/* em2874 registers */
Devin Heitmueller4b922532008-11-13 03:15:55 -030087#define EM2874_R50_IR_CONFIG 0x50
88#define EM2874_R51_IR 0x51
Devin Heitmuellerebef13d2008-11-12 02:05:24 -030089#define EM2874_R5F_TS_ENABLE 0x5f
Devin Heitmueller6a1acc32008-11-12 02:05:06 -030090#define EM2874_R80_GPIO 0x80
91
Devin Heitmueller4b922532008-11-13 03:15:55 -030092/* em2874 IR config register (0x50) */
93#define EM2874_IR_NEC 0x00
94#define EM2874_IR_RC5 0x04
95#define EM2874_IR_RC5_MODE_0 0x08
96#define EM2874_IR_RC5_MODE_6A 0x0b
97
Devin Heitmuellerebef13d2008-11-12 02:05:24 -030098/* em2874 Transport Stream Enable Register (0x5f) */
99#define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
100#define EM2874_TS1_FILTER_ENABLE (1 << 1)
101#define EM2874_TS1_NULL_DISCARD (1 << 2)
102#define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
103#define EM2874_TS2_FILTER_ENABLE (1 << 5)
104#define EM2874_TS2_NULL_DISCARD (1 << 6)
105
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -0300106/* register settings */
107#define EM2800_AUDIO_SRC_TUNER 0x0d
108#define EM2800_AUDIO_SRC_LINE 0x0c
109#define EM28XX_AUDIO_SRC_TUNER 0xc0
110#define EM28XX_AUDIO_SRC_LINE 0x80
111
112/* FIXME: Need to be populated with the other chip ID's */
113enum em28xx_chip_id {
Mauro Carvalho Chehabf09fb532008-11-16 10:40:21 -0300114 CHIP_ID_EM2820 = 18,
115 CHIP_ID_EM2840 = 20,
Devin Heitmuellera8a1f8c2008-06-10 12:35:42 -0300116 CHIP_ID_EM2860 = 34,
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -0300117 CHIP_ID_EM2883 = 36,
Devin Heitmueller5caeba02008-11-12 02:04:48 -0300118 CHIP_ID_EM2874 = 65,
Mauro Carvalho Chehab2ba890e2008-04-17 21:42:58 -0300119};
Mauro Carvalho Chehab6fbcebf2008-11-17 22:30:09 -0300120
121/*
122 * Registers used by em202 and other AC97 chips
123 */
124
125/* Standard AC97 registers */
126#define AC97_RESET 0x00
127#define AC97_MASTER_VOL 0x02
128#define AC97_LINE_LEVEL_VOL 0x04
129#define AC97_MASTER_MONO_VOL 0x06
130
131#define AC97_PC_BEEP_VOL 0x0a
132#define AC97_PHONE_VOL 0x0c
133#define AC97_MIC_VOL 0x0e
134#define AC97_LINEIN_VOL 0x10
135#define AC97_CD_VOL 0x12
136#define AC97_VIDEO_VOL 0x14
137#define AC97_AUX_VOL 0x16
138#define AC97_PCM_OUT_VOL 0x18
139#define AC97_RECORD_SELECT 0x1a
140#define AC97_RECORD_GAIN 0x1c
141#define AC97_GENERAL_PURPOSE 0x20
142#define AC97_3D_CTRL 0x22
143#define AC97_AUD_INT_AND_PAG 0x24
144#define AC97_POWER_DOWN_CTRL 0x26
145#define AC97_EXT_AUD_ID 0x28
146#define AC97_EXT_AUD_CTRL 0x2a
147
148/* Supported rate varies for each AC97 device
149 if write an unsupported value, it will return the closest one
150 */
151#define AC97_PCM_OUT_FRONT_SRATE 0x2c
152#define AC97_PCM_OUT_SURR_SRATE 0x2e
153#define AC97_PCM_OUT_LFE_SRATE 0x30
154#define AC97_PCM_IN_SRATE 0x32
155#define AC97_LFE_MASTER_VOL 0x36
156#define AC97_SURR_MASTER_VOL 0x38
157#define AC97_SPDIF_OUT_CTRL 0x3a
158
159#define AC97_VENDOR_ID1 0x7c
160#define AC97_VENDOR_ID2 0x7e
161
162/* EMP202 vendor registers */
163#define EM202_EXT_MODEM_CTRL 0x3e
164#define EM202_GPIO_CONF 0x4c
165#define EM202_GPIO_POLARITY 0x4e
166#define EM202_GPIO_STICKY 0x50
167#define EM202_GPIO_MASK 0x52
168#define EM202_GPIO_STATUS 0x54
169#define EM202_SPDIF_OUT_SEL 0x6a
170#define EM202_ANTIPOP 0x72
171#define EM202_EAPD_GPIO_ACCESS 0x74