| Tom St Denis | 5e2e211 | 2016-11-07 14:06:01 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2016 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #ifndef SI_ENUMS_H |
| 24 | #define SI_ENUMS_H |
| 25 | |
| Tom St Denis | 7251826 | 2016-11-08 11:55:42 -0500 | [diff] [blame^] | 26 | #define AMDGPU_NUM_OF_VMIDS 8 |
| 27 | #define SI_CRTC0_REGISTER_OFFSET 0 |
| 28 | #define SI_CRTC1_REGISTER_OFFSET 0x300 |
| 29 | #define SI_CRTC2_REGISTER_OFFSET 0x2600 |
| 30 | #define SI_CRTC3_REGISTER_OFFSET 0x2900 |
| 31 | #define SI_CRTC4_REGISTER_OFFSET 0x2c00 |
| 32 | #define SI_CRTC5_REGISTER_OFFSET 0x2f00 |
| 33 | |
| Tom St Denis | 5e2e211 | 2016-11-07 14:06:01 -0500 | [diff] [blame] | 34 | #define DMA0_REGISTER_OFFSET 0x000 |
| 35 | #define DMA1_REGISTER_OFFSET 0x200 |
| 36 | #define ES_AND_GS_AUTO 3 |
| 37 | #define RADEON_PACKET_TYPE3 3 |
| 38 | #define CE_PARTITION_BASE 3 |
| 39 | #define BUF_SWAP_32BIT (2 << 16) |
| 40 | |
| 41 | #define GFX_POWER_STATUS (1 << 1) |
| 42 | #define GFX_CLOCK_STATUS (1 << 2) |
| 43 | #define GFX_LS_STATUS (1 << 3) |
| 44 | #define RLC_BUSY_STATUS (1 << 0) |
| 45 | |
| 46 | #define RLC_PUD(x) ((x) << 0) |
| 47 | #define RLC_PUD_MASK (0xff << 0) |
| 48 | #define RLC_PDD(x) ((x) << 8) |
| 49 | #define RLC_PDD_MASK (0xff << 8) |
| 50 | #define RLC_TTPD(x) ((x) << 16) |
| 51 | #define RLC_TTPD_MASK (0xff << 16) |
| 52 | #define RLC_MSD(x) ((x) << 24) |
| 53 | #define RLC_MSD_MASK (0xff << 24) |
| 54 | #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) |
| 55 | #define WRITE_DATA_DST_SEL(x) ((x) << 8) |
| 56 | #define EVENT_TYPE(x) ((x) << 0) |
| 57 | #define EVENT_INDEX(x) ((x) << 8) |
| 58 | #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) |
| 59 | #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) |
| 60 | #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) |
| 61 | |
| 62 | #define GFX6_NUM_GFX_RINGS 1 |
| 63 | #define GFX6_NUM_COMPUTE_RINGS 2 |
| 64 | #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90 |
| 65 | #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D |
| 66 | |
| 67 | #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 |
| 68 | #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 |
| 69 | #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 |
| 70 | |
| 71 | #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ |
| 72 | (((op) & 0xFF) << 8) | \ |
| 73 | ((n) & 0x3FFF) << 16) |
| 74 | #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) |
| 75 | #define PACKET3_NOP 0x10 |
| 76 | #define PACKET3_SET_BASE 0x11 |
| 77 | #define PACKET3_BASE_INDEX(x) ((x) << 0) |
| 78 | #define PACKET3_CLEAR_STATE 0x12 |
| 79 | #define PACKET3_INDEX_BUFFER_SIZE 0x13 |
| 80 | #define PACKET3_DISPATCH_DIRECT 0x15 |
| 81 | #define PACKET3_DISPATCH_INDIRECT 0x16 |
| 82 | #define PACKET3_ALLOC_GDS 0x1B |
| 83 | #define PACKET3_WRITE_GDS_RAM 0x1C |
| 84 | #define PACKET3_ATOMIC_GDS 0x1D |
| 85 | #define PACKET3_ATOMIC 0x1E |
| 86 | #define PACKET3_OCCLUSION_QUERY 0x1F |
| 87 | #define PACKET3_SET_PREDICATION 0x20 |
| 88 | #define PACKET3_REG_RMW 0x21 |
| 89 | #define PACKET3_COND_EXEC 0x22 |
| 90 | #define PACKET3_PRED_EXEC 0x23 |
| 91 | #define PACKET3_DRAW_INDIRECT 0x24 |
| 92 | #define PACKET3_DRAW_INDEX_INDIRECT 0x25 |
| 93 | #define PACKET3_INDEX_BASE 0x26 |
| 94 | #define PACKET3_DRAW_INDEX_2 0x27 |
| 95 | #define PACKET3_CONTEXT_CONTROL 0x28 |
| 96 | #define PACKET3_INDEX_TYPE 0x2A |
| 97 | #define PACKET3_DRAW_INDIRECT_MULTI 0x2C |
| 98 | #define PACKET3_DRAW_INDEX_AUTO 0x2D |
| 99 | #define PACKET3_DRAW_INDEX_IMMD 0x2E |
| 100 | #define PACKET3_NUM_INSTANCES 0x2F |
| 101 | #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 |
| 102 | #define PACKET3_INDIRECT_BUFFER_CONST 0x31 |
| 103 | #define PACKET3_INDIRECT_BUFFER 0x3F |
| 104 | #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 |
| 105 | #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 |
| 106 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
| 107 | #define PACKET3_WRITE_DATA 0x37 |
| 108 | #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 |
| 109 | #define PACKET3_MEM_SEMAPHORE 0x39 |
| 110 | #define PACKET3_MPEG_INDEX 0x3A |
| 111 | #define PACKET3_COPY_DW 0x3B |
| 112 | #define PACKET3_WAIT_REG_MEM 0x3C |
| 113 | #define PACKET3_MEM_WRITE 0x3D |
| 114 | #define PACKET3_COPY_DATA 0x40 |
| 115 | #define PACKET3_CP_DMA 0x41 |
| 116 | # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) |
| 117 | # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) |
| 118 | # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) |
| 119 | # define PACKET3_CP_DMA_CP_SYNC (1 << 31) |
| 120 | # define PACKET3_CP_DMA_DIS_WC (1 << 21) |
| 121 | # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) |
| 122 | # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) |
| 123 | # define PACKET3_CP_DMA_CMD_SAS (1 << 26) |
| 124 | # define PACKET3_CP_DMA_CMD_DAS (1 << 27) |
| 125 | # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) |
| 126 | # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) |
| 127 | # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) |
| 128 | #define PACKET3_PFP_SYNC_ME 0x42 |
| 129 | #define PACKET3_SURFACE_SYNC 0x43 |
| 130 | # define PACKET3_DEST_BASE_0_ENA (1 << 0) |
| 131 | # define PACKET3_DEST_BASE_1_ENA (1 << 1) |
| 132 | # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) |
| 133 | # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) |
| 134 | # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) |
| 135 | # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) |
| 136 | # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) |
| 137 | # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) |
| 138 | # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) |
| 139 | # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) |
| 140 | # define PACKET3_DB_DEST_BASE_ENA (1 << 14) |
| 141 | # define PACKET3_DEST_BASE_2_ENA (1 << 19) |
| 142 | # define PACKET3_DEST_BASE_3_ENA (1 << 21) |
| 143 | # define PACKET3_TCL1_ACTION_ENA (1 << 22) |
| 144 | # define PACKET3_TC_ACTION_ENA (1 << 23) |
| 145 | # define PACKET3_CB_ACTION_ENA (1 << 25) |
| 146 | # define PACKET3_DB_ACTION_ENA (1 << 26) |
| 147 | # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) |
| 148 | # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) |
| 149 | #define PACKET3_ME_INITIALIZE 0x44 |
| 150 | #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) |
| 151 | #define PACKET3_COND_WRITE 0x45 |
| 152 | #define PACKET3_EVENT_WRITE 0x46 |
| 153 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
| 154 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
| 155 | #define PACKET3_PREAMBLE_CNTL 0x4A |
| 156 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) |
| 157 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) |
| 158 | #define PACKET3_ONE_REG_WRITE 0x57 |
| 159 | #define PACKET3_LOAD_CONFIG_REG 0x5F |
| 160 | #define PACKET3_LOAD_CONTEXT_REG 0x60 |
| 161 | #define PACKET3_LOAD_SH_REG 0x61 |
| 162 | #define PACKET3_SET_CONFIG_REG 0x68 |
| 163 | #define PACKET3_SET_CONFIG_REG_START 0x00002000 |
| 164 | #define PACKET3_SET_CONFIG_REG_END 0x00002c00 |
| 165 | #define PACKET3_SET_CONTEXT_REG 0x69 |
| 166 | #define PACKET3_SET_CONTEXT_REG_START 0x000a000 |
| 167 | #define PACKET3_SET_CONTEXT_REG_END 0x000a400 |
| 168 | #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 |
| 169 | #define PACKET3_SET_RESOURCE_INDIRECT 0x74 |
| 170 | #define PACKET3_SET_SH_REG 0x76 |
| 171 | #define PACKET3_SET_SH_REG_START 0x00002c00 |
| 172 | #define PACKET3_SET_SH_REG_END 0x00003000 |
| 173 | #define PACKET3_SET_SH_REG_OFFSET 0x77 |
| 174 | #define PACKET3_ME_WRITE 0x7A |
| 175 | #define PACKET3_SCRATCH_RAM_WRITE 0x7D |
| 176 | #define PACKET3_SCRATCH_RAM_READ 0x7E |
| 177 | #define PACKET3_CE_WRITE 0x7F |
| 178 | #define PACKET3_LOAD_CONST_RAM 0x80 |
| 179 | #define PACKET3_WRITE_CONST_RAM 0x81 |
| 180 | #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 |
| 181 | #define PACKET3_DUMP_CONST_RAM 0x83 |
| 182 | #define PACKET3_INCREMENT_CE_COUNTER 0x84 |
| 183 | #define PACKET3_INCREMENT_DE_COUNTER 0x85 |
| 184 | #define PACKET3_WAIT_ON_CE_COUNTER 0x86 |
| 185 | #define PACKET3_WAIT_ON_DE_COUNTER 0x87 |
| 186 | #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 |
| 187 | #define PACKET3_SET_CE_DE_COUNTERS 0x89 |
| 188 | #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A |
| 189 | #define PACKET3_SWITCH_BUFFER 0x8B |
| 190 | #define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) |
| 191 | #define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) |
| 192 | #define PACKET3_SEM_SEL_WAIT (0x7 << 29) |
| 193 | |
| 194 | #endif |