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H. Peter Anvin1965aae2008-10-22 22:26:29 -07001#ifndef _ASM_X86_TLBFLUSH_H
2#define _ASM_X86_TLBFLUSH_H
Thomas Gleixnerd291cf82008-01-30 13:30:35 +01003
4#include <linux/mm.h>
5#include <linux/sched.h>
6
7#include <asm/processor.h>
Borislav Petkovcd4d09e2016-01-26 22:12:04 +01008#include <asm/cpufeature.h>
David Howellsf05e7982012-03-28 18:11:12 +01009#include <asm/special_insns.h>
Andy Lutomirskice4a4e562017-05-28 10:00:14 -070010#include <asm/smp.h>
Thomas Gleixnerd291cf82008-01-30 13:30:35 +010011
Andy Lutomirski060a4022016-01-29 11:42:57 -080012static inline void __invpcid(unsigned long pcid, unsigned long addr,
13 unsigned long type)
14{
Borislav Petkove2c7698c2016-02-10 15:51:16 +010015 struct { u64 d[2]; } desc = { { pcid, addr } };
Andy Lutomirski060a4022016-01-29 11:42:57 -080016
17 /*
18 * The memory clobber is because the whole point is to invalidate
19 * stale TLB entries and, especially if we're flushing global
20 * mappings, we don't want the compiler to reorder any subsequent
21 * memory accesses before the TLB flush.
22 *
23 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
24 * invpcid (%rcx), %rax in long mode.
25 */
26 asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
Borislav Petkove2c7698c2016-02-10 15:51:16 +010027 : : "m" (desc), "a" (type), "c" (&desc) : "memory");
Andy Lutomirski060a4022016-01-29 11:42:57 -080028}
29
30#define INVPCID_TYPE_INDIV_ADDR 0
31#define INVPCID_TYPE_SINGLE_CTXT 1
32#define INVPCID_TYPE_ALL_INCL_GLOBAL 2
33#define INVPCID_TYPE_ALL_NON_GLOBAL 3
34
35/* Flush all mappings for a given pcid and addr, not including globals. */
36static inline void invpcid_flush_one(unsigned long pcid,
37 unsigned long addr)
38{
39 __invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);
40}
41
42/* Flush all mappings for a given PCID, not including globals. */
43static inline void invpcid_flush_single_context(unsigned long pcid)
44{
45 __invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);
46}
47
48/* Flush all mappings, including globals, for all PCIDs. */
49static inline void invpcid_flush_all(void)
50{
51 __invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);
52}
53
54/* Flush all mappings for all PCIDs except globals. */
55static inline void invpcid_flush_all_nonglobals(void)
56{
57 __invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);
58}
59
Andy Lutomirskif39681e2017-06-29 08:53:15 -070060static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
61{
62 u64 new_tlb_gen;
63
64 /*
65 * Bump the generation count. This also serves as a full barrier
66 * that synchronizes with switch_mm(): callers are required to order
67 * their read of mm_cpumask after their writes to the paging
68 * structures.
69 */
70 smp_mb__before_atomic();
71 new_tlb_gen = atomic64_inc_return(&mm->context.tlb_gen);
72 smp_mb__after_atomic();
73
74 return new_tlb_gen;
75}
76
Thomas Gleixnerd291cf82008-01-30 13:30:35 +010077#ifdef CONFIG_PARAVIRT
78#include <asm/paravirt.h>
Thomas Gleixner96a388d2007-10-11 11:20:03 +020079#else
Thomas Gleixnerd291cf82008-01-30 13:30:35 +010080#define __flush_tlb() __native_flush_tlb()
81#define __flush_tlb_global() __native_flush_tlb_global()
82#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
Thomas Gleixner96a388d2007-10-11 11:20:03 +020083#endif
Thomas Gleixnerd291cf82008-01-30 13:30:35 +010084
Andy Lutomirski10af6232017-07-24 21:41:38 -070085/*
86 * 6 because 6 should be plenty and struct tlb_state will fit in
87 * two cache lines.
88 */
89#define TLB_NR_DYN_ASIDS 6
90
Andy Lutomirskib0579ad2017-06-29 08:53:16 -070091struct tlb_context {
92 u64 ctx_id;
93 u64 tlb_gen;
94};
95
Andy Lutomirski1e02ce42014-10-24 15:58:08 -070096struct tlb_state {
Andy Lutomirski3d28ebc2017-05-28 10:00:15 -070097 /*
98 * cpu_tlbstate.loaded_mm should match CR3 whenever interrupts
99 * are on. This means that it may not match current->active_mm,
100 * which will contain the previous user mm when we're in lazy TLB
101 * mode even if we've already switched back to swapper_pg_dir.
102 */
103 struct mm_struct *loaded_mm;
Andy Lutomirski10af6232017-07-24 21:41:38 -0700104 u16 loaded_mm_asid;
105 u16 next_asid;
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700106
107 /*
108 * Access to this CR4 shadow and to H/W CR4 is protected by
109 * disabling interrupts when modifying either one.
110 */
111 unsigned long cr4;
Andy Lutomirskib0579ad2017-06-29 08:53:16 -0700112
113 /*
114 * This is a list of all contexts that might exist in the TLB.
Andy Lutomirski10af6232017-07-24 21:41:38 -0700115 * There is one per ASID that we use, and the ASID (what the
116 * CPU calls PCID) is the index into ctxts.
Andy Lutomirskib0579ad2017-06-29 08:53:16 -0700117 *
118 * For each context, ctx_id indicates which mm the TLB's user
119 * entries came from. As an invariant, the TLB will never
120 * contain entries that are out-of-date as when that mm reached
121 * the tlb_gen in the list.
122 *
123 * To be clear, this means that it's legal for the TLB code to
124 * flush the TLB without updating tlb_gen. This can happen
125 * (for now, at least) due to paravirt remote flushes.
Andy Lutomirski10af6232017-07-24 21:41:38 -0700126 *
127 * NB: context 0 is a bit special, since it's also used by
128 * various bits of init code. This is fine -- code that
129 * isn't aware of PCID will end up harmlessly flushing
130 * context 0.
Andy Lutomirskib0579ad2017-06-29 08:53:16 -0700131 */
Andy Lutomirski10af6232017-07-24 21:41:38 -0700132 struct tlb_context ctxs[TLB_NR_DYN_ASIDS];
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700133};
134DECLARE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate);
135
136/* Initialize cr4 shadow for this CPU. */
137static inline void cr4_init_shadow(void)
138{
Andy Lutomirski1ef55be12016-09-29 12:48:12 -0700139 this_cpu_write(cpu_tlbstate.cr4, __read_cr4());
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700140}
141
Andy Lutomirski375074c2014-10-24 15:58:07 -0700142/* Set in this cpu's CR4. */
143static inline void cr4_set_bits(unsigned long mask)
144{
145 unsigned long cr4;
146
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700147 cr4 = this_cpu_read(cpu_tlbstate.cr4);
148 if ((cr4 | mask) != cr4) {
149 cr4 |= mask;
150 this_cpu_write(cpu_tlbstate.cr4, cr4);
151 __write_cr4(cr4);
152 }
Andy Lutomirski375074c2014-10-24 15:58:07 -0700153}
154
155/* Clear in this cpu's CR4. */
156static inline void cr4_clear_bits(unsigned long mask)
157{
158 unsigned long cr4;
159
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700160 cr4 = this_cpu_read(cpu_tlbstate.cr4);
161 if ((cr4 & ~mask) != cr4) {
162 cr4 &= ~mask;
163 this_cpu_write(cpu_tlbstate.cr4, cr4);
164 __write_cr4(cr4);
165 }
166}
167
Thomas Gleixner5a920152017-02-14 00:11:04 -0800168static inline void cr4_toggle_bits(unsigned long mask)
169{
170 unsigned long cr4;
171
172 cr4 = this_cpu_read(cpu_tlbstate.cr4);
173 cr4 ^= mask;
174 this_cpu_write(cpu_tlbstate.cr4, cr4);
175 __write_cr4(cr4);
176}
177
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700178/* Read the CR4 shadow. */
179static inline unsigned long cr4_read_shadow(void)
180{
181 return this_cpu_read(cpu_tlbstate.cr4);
Andy Lutomirski375074c2014-10-24 15:58:07 -0700182}
183
184/*
185 * Save some of cr4 feature set we're using (e.g. Pentium 4MB
186 * enable and PPro Global page enable), so that any CPU's that boot
187 * up after us can get the correct flags. This should only be used
188 * during boot on the boot cpu.
189 */
190extern unsigned long mmu_cr4_features;
191extern u32 *trampoline_cr4_features;
192
193static inline void cr4_set_bits_and_update_boot(unsigned long mask)
194{
195 mmu_cr4_features |= mask;
196 if (trampoline_cr4_features)
197 *trampoline_cr4_features = mmu_cr4_features;
198 cr4_set_bits(mask);
199}
200
Andy Lutomirski72c00982017-09-06 19:54:53 -0700201extern void initialize_tlbstate_and_flush(void);
202
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100203static inline void __native_flush_tlb(void)
204{
Sebastian Andrzej Siewior5cf07912016-08-05 15:37:39 +0200205 /*
206 * If current->mm == NULL then we borrow a mm which may change during a
207 * task switch and therefore we must not be preempted while we write CR3
208 * back:
209 */
210 preempt_disable();
Andy Lutomirski6c690ee2017-06-12 10:26:14 -0700211 native_write_cr3(__native_read_cr3());
Sebastian Andrzej Siewior5cf07912016-08-05 15:37:39 +0200212 preempt_enable();
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100213}
214
Fenghua Yu086fc8f2012-12-20 23:44:27 -0800215static inline void __native_flush_tlb_global_irq_disabled(void)
216{
217 unsigned long cr4;
218
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700219 cr4 = this_cpu_read(cpu_tlbstate.cr4);
Fenghua Yu086fc8f2012-12-20 23:44:27 -0800220 /* clear PGE */
221 native_write_cr4(cr4 & ~X86_CR4_PGE);
222 /* write old PGE again and flush TLBs */
223 native_write_cr4(cr4);
224}
225
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100226static inline void __native_flush_tlb_global(void)
227{
Ingo Molnarb1979a52008-05-12 21:21:15 +0200228 unsigned long flags;
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100229
Andy Lutomirskid8bced72016-01-29 11:42:59 -0800230 if (static_cpu_has(X86_FEATURE_INVPCID)) {
231 /*
232 * Using INVPCID is considerably faster than a pair of writes
233 * to CR4 sandwiched inside an IRQ flag save/restore.
234 */
235 invpcid_flush_all();
236 return;
237 }
238
Ingo Molnarb1979a52008-05-12 21:21:15 +0200239 /*
240 * Read-modify-write to CR4 - protect it from preemption and
241 * from interrupts. (Use the raw variant because this code can
242 * be called from deep inside debugging code.)
243 */
244 raw_local_irq_save(flags);
245
Fenghua Yu086fc8f2012-12-20 23:44:27 -0800246 __native_flush_tlb_global_irq_disabled();
Ingo Molnarb1979a52008-05-12 21:21:15 +0200247
248 raw_local_irq_restore(flags);
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100249}
250
251static inline void __native_flush_tlb_single(unsigned long addr)
252{
Joe Perches94cf8de2008-03-23 01:03:45 -0700253 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100254}
255
256static inline void __flush_tlb_all(void)
257{
Daniel Borkmann2c4ea6e2017-03-11 01:31:19 +0100258 if (boot_cpu_has(X86_FEATURE_PGE))
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100259 __flush_tlb_global();
260 else
261 __flush_tlb();
Andy Lutomirski660da7c2017-06-29 08:53:21 -0700262
263 /*
264 * Note: if we somehow had PCID but not PGE, then this wouldn't work --
265 * we'd end up flushing kernel translations for the current ASID but
266 * we might fail to flush kernel translations for other cached ASIDs.
267 *
268 * To avoid this issue, we force PCID off if PGE is off.
269 */
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100270}
271
272static inline void __flush_tlb_one(unsigned long addr)
273{
Mel Gormanec659932014-01-21 14:33:16 -0800274 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
Michael Wange8747f12013-06-04 14:28:18 +0800275 __flush_tlb_single(addr);
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100276}
277
Alex Shi3e7f3db2012-05-10 18:01:59 +0800278#define TLB_FLUSH_ALL -1UL
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100279
280/*
281 * TLB flushing:
282 *
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100283 * - flush_tlb_all() flushes all processes TLBs
284 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
285 * - flush_tlb_page(vma, vmaddr) flushes one page
286 * - flush_tlb_range(vma, start, end) flushes a range of pages
287 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
Andy Lutomirskia2055ab2017-05-28 10:00:10 -0700288 * - flush_tlb_others(cpumask, info) flushes TLBs on other cpus
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100289 *
290 * ..but the i386 has somewhat limited tlb flushing capabilities,
291 * and page-granular flushes are available only on i486 and up.
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100292 */
Andy Lutomirskia2055ab2017-05-28 10:00:10 -0700293struct flush_tlb_info {
Andy Lutomirskib0579ad2017-06-29 08:53:16 -0700294 /*
295 * We support several kinds of flushes.
296 *
297 * - Fully flush a single mm. .mm will be set, .end will be
298 * TLB_FLUSH_ALL, and .new_tlb_gen will be the tlb_gen to
299 * which the IPI sender is trying to catch us up.
300 *
301 * - Partially flush a single mm. .mm will be set, .start and
302 * .end will indicate the range, and .new_tlb_gen will be set
303 * such that the changes between generation .new_tlb_gen-1 and
304 * .new_tlb_gen are entirely contained in the indicated range.
305 *
306 * - Fully flush all mms whose tlb_gens have been updated. .mm
307 * will be NULL, .end will be TLB_FLUSH_ALL, and .new_tlb_gen
308 * will be zero.
309 */
310 struct mm_struct *mm;
311 unsigned long start;
312 unsigned long end;
313 u64 new_tlb_gen;
Andy Lutomirskia2055ab2017-05-28 10:00:10 -0700314};
315
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100316#define local_flush_tlb() __flush_tlb()
317
Alex Shi611ae8e2012-06-28 09:02:22 +0800318#define flush_tlb_mm(mm) flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
319
320#define flush_tlb_range(vma, start, end) \
321 flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
322
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100323extern void flush_tlb_all(void);
Alex Shi611ae8e2012-06-28 09:02:22 +0800324extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
325 unsigned long end, unsigned long vmflag);
Alex Shieffee4b2012-06-28 09:02:24 +0800326extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100327
Andy Lutomirskica6c99c02017-05-22 15:30:01 -0700328static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
329{
330 flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, VM_NONE);
331}
332
Rusty Russell4595f962009-01-10 21:58:09 -0800333void native_flush_tlb_others(const struct cpumask *cpumask,
Andy Lutomirskia2055ab2017-05-28 10:00:10 -0700334 const struct flush_tlb_info *info);
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100335
Andy Lutomirskie73ad5f2017-05-22 15:30:03 -0700336static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
337 struct mm_struct *mm)
338{
Andy Lutomirskif39681e2017-06-29 08:53:15 -0700339 inc_mm_tlb_gen(mm);
Andy Lutomirskie73ad5f2017-05-22 15:30:03 -0700340 cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
341}
342
343extern void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch);
344
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100345#ifndef CONFIG_PARAVIRT
Andy Lutomirskia2055ab2017-05-28 10:00:10 -0700346#define flush_tlb_others(mask, info) \
347 native_flush_tlb_others(mask, info)
Thomas Gleixnerd291cf82008-01-30 13:30:35 +0100348#endif
349
H. Peter Anvin1965aae2008-10-22 22:26:29 -0700350#endif /* _ASM_X86_TLBFLUSH_H */