blob: cdc6e67607056f06e5730cac05f46a19a4516ae1 [file] [log] [blame]
Eric Anholtd5b1a782015-11-30 12:13:37 -08001/*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
Eric Anholt72f793f2017-02-27 12:11:41 -080024/**
25 * DOC: Interrupt management for the V3D engine
Eric Anholtd5b1a782015-11-30 12:13:37 -080026 *
27 * We have an interrupt status register (V3D_INTCTL) which reports
28 * interrupts, and where writing 1 bits clears those interrupts.
29 * There are also a pair of interrupt registers
30 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
31 * disables that specific interrupt, and 0s written are ignored
32 * (reading either one returns the set of enabled interrupts).
33 *
Varad Gautamca26d282016-02-17 19:08:21 +053034 * When we take a binning flush done interrupt, we need to submit the
35 * next frame for binning and move the finished frame to the render
36 * thread.
37 *
Eric Anholtd5b1a782015-11-30 12:13:37 -080038 * When we take a render frame interrupt, we need to wake the
39 * processes waiting for some frame to be done, and get the next frame
40 * submitted ASAP (so the hardware doesn't sit idle when there's work
41 * to do).
42 *
43 * When we take the binner out of memory interrupt, we need to
44 * allocate some new memory and pass it to the binner so that the
45 * current job can make progress.
46 */
47
48#include "vc4_drv.h"
49#include "vc4_regs.h"
50
51#define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
Varad Gautamca26d282016-02-17 19:08:21 +053052 V3D_INT_FLDONE | \
Eric Anholtd5b1a782015-11-30 12:13:37 -080053 V3D_INT_FRDONE)
54
55DECLARE_WAIT_QUEUE_HEAD(render_wait);
56
57static void
58vc4_overflow_mem_work(struct work_struct *work)
59{
60 struct vc4_dev *vc4 =
61 container_of(work, struct vc4_dev, overflow_mem_work);
62 struct drm_device *dev = vc4->dev;
63 struct vc4_bo *bo;
64
65 bo = vc4_bo_create(dev, 256 * 1024, true);
Eric Anholt2c68f1f2016-01-25 14:13:12 -080066 if (IS_ERR(bo)) {
Eric Anholtd5b1a782015-11-30 12:13:37 -080067 DRM_ERROR("Couldn't allocate binner overflow mem\n");
68 return;
69 }
70
71 /* If there's a job executing currently, then our previous
72 * overflow allocation is getting used in that job and we need
73 * to queue it to be released when the job is done. But if no
74 * job is executing at all, then we can free the old overflow
75 * object direcctly.
76 *
77 * No lock necessary for this pointer since we're the only
78 * ones that update the pointer, and our workqueue won't
79 * reenter.
80 */
81 if (vc4->overflow_mem) {
82 struct vc4_exec_info *current_exec;
83 unsigned long irqflags;
84
85 spin_lock_irqsave(&vc4->job_lock, irqflags);
Varad Gautamca26d282016-02-17 19:08:21 +053086 current_exec = vc4_first_bin_job(vc4);
Eric Anholt9326e6f2016-07-26 13:47:14 -070087 if (!current_exec)
88 current_exec = vc4_last_render_job(vc4);
Eric Anholtd5b1a782015-11-30 12:13:37 -080089 if (current_exec) {
Eric Anholt9326e6f2016-07-26 13:47:14 -070090 vc4->overflow_mem->seqno = current_exec->seqno;
Eric Anholtd5b1a782015-11-30 12:13:37 -080091 list_add_tail(&vc4->overflow_mem->unref_head,
92 &current_exec->unref_list);
93 vc4->overflow_mem = NULL;
94 }
95 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
96 }
97
98 if (vc4->overflow_mem)
99 drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
100 vc4->overflow_mem = bo;
101
102 V3D_WRITE(V3D_BPOA, bo->base.paddr);
103 V3D_WRITE(V3D_BPOS, bo->base.base.size);
104 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
105 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
106}
107
108static void
Varad Gautamca26d282016-02-17 19:08:21 +0530109vc4_irq_finish_bin_job(struct drm_device *dev)
Eric Anholtd5b1a782015-11-30 12:13:37 -0800110{
111 struct vc4_dev *vc4 = to_vc4_dev(dev);
Varad Gautamca26d282016-02-17 19:08:21 +0530112 struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
113
114 if (!exec)
115 return;
116
117 vc4_move_job_to_render(dev, exec);
118 vc4_submit_next_bin_job(dev);
119}
120
121static void
122vc4_cancel_bin_job(struct drm_device *dev)
123{
124 struct vc4_dev *vc4 = to_vc4_dev(dev);
125 struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
126
127 if (!exec)
128 return;
129
130 list_move_tail(&exec->head, &vc4->bin_job_list);
131 vc4_submit_next_bin_job(dev);
132}
133
134static void
135vc4_irq_finish_render_job(struct drm_device *dev)
136{
137 struct vc4_dev *vc4 = to_vc4_dev(dev);
138 struct vc4_exec_info *exec = vc4_first_render_job(vc4);
Eric Anholtd5b1a782015-11-30 12:13:37 -0800139
140 if (!exec)
141 return;
142
143 vc4->finished_seqno++;
144 list_move_tail(&exec->head, &vc4->job_done_list);
Varad Gautamca26d282016-02-17 19:08:21 +0530145 vc4_submit_next_render_job(dev);
Eric Anholtd5b1a782015-11-30 12:13:37 -0800146
147 wake_up_all(&vc4->job_wait_queue);
148 schedule_work(&vc4->job_done_work);
149}
150
151irqreturn_t
152vc4_irq(int irq, void *arg)
153{
154 struct drm_device *dev = arg;
155 struct vc4_dev *vc4 = to_vc4_dev(dev);
156 uint32_t intctl;
157 irqreturn_t status = IRQ_NONE;
158
159 barrier();
160 intctl = V3D_READ(V3D_INTCTL);
161
Varad Gautamca26d282016-02-17 19:08:21 +0530162 /* Acknowledge the interrupts we're handling here. The binner
163 * last flush / render frame done interrupt will be cleared,
164 * while OUTOMEM will stay high until the underlying cause is
165 * cleared.
Eric Anholtd5b1a782015-11-30 12:13:37 -0800166 */
167 V3D_WRITE(V3D_INTCTL, intctl);
168
169 if (intctl & V3D_INT_OUTOMEM) {
170 /* Disable OUTOMEM until the work is done. */
171 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
172 schedule_work(&vc4->overflow_mem_work);
173 status = IRQ_HANDLED;
174 }
175
Varad Gautamca26d282016-02-17 19:08:21 +0530176 if (intctl & V3D_INT_FLDONE) {
177 spin_lock(&vc4->job_lock);
178 vc4_irq_finish_bin_job(dev);
179 spin_unlock(&vc4->job_lock);
180 status = IRQ_HANDLED;
181 }
182
Eric Anholtd5b1a782015-11-30 12:13:37 -0800183 if (intctl & V3D_INT_FRDONE) {
184 spin_lock(&vc4->job_lock);
Varad Gautamca26d282016-02-17 19:08:21 +0530185 vc4_irq_finish_render_job(dev);
Eric Anholtd5b1a782015-11-30 12:13:37 -0800186 spin_unlock(&vc4->job_lock);
187 status = IRQ_HANDLED;
188 }
189
190 return status;
191}
192
193void
194vc4_irq_preinstall(struct drm_device *dev)
195{
196 struct vc4_dev *vc4 = to_vc4_dev(dev);
197
198 init_waitqueue_head(&vc4->job_wait_queue);
199 INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
200
201 /* Clear any pending interrupts someone might have left around
202 * for us.
203 */
204 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
205}
206
207int
208vc4_irq_postinstall(struct drm_device *dev)
209{
210 struct vc4_dev *vc4 = to_vc4_dev(dev);
211
212 /* Enable both the render done and out of memory interrupts. */
213 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
214
215 return 0;
216}
217
218void
219vc4_irq_uninstall(struct drm_device *dev)
220{
221 struct vc4_dev *vc4 = to_vc4_dev(dev);
222
223 /* Disable sending interrupts for our driver's IRQs. */
224 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
225
226 /* Clear any pending interrupts we might have left. */
227 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
228
229 cancel_work_sync(&vc4->overflow_mem_work);
230}
231
232/** Reinitializes interrupt registers when a GPU reset is performed. */
233void vc4_irq_reset(struct drm_device *dev)
234{
235 struct vc4_dev *vc4 = to_vc4_dev(dev);
236 unsigned long irqflags;
237
238 /* Acknowledge any stale IRQs. */
239 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
240
241 /*
242 * Turn all our interrupts on. Binner out of memory is the
243 * only one we expect to trigger at this point, since we've
244 * just come from poweron and haven't supplied any overflow
245 * memory yet.
246 */
247 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
248
249 spin_lock_irqsave(&vc4->job_lock, irqflags);
Varad Gautamca26d282016-02-17 19:08:21 +0530250 vc4_cancel_bin_job(dev);
251 vc4_irq_finish_render_job(dev);
Eric Anholtd5b1a782015-11-30 12:13:37 -0800252 spin_unlock_irqrestore(&vc4->job_lock, irqflags);
253}