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Sujith394cf0a2009-02-09 13:26:54 +05301/*
Sujithcee075a2009-03-13 09:07:23 +05302 * Copyright (c) 2008-2009 Atheros Communications Inc.
Sujith394cf0a2009-02-09 13:26:54 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef MAC_H
18#define MAC_H
19
Gabor Juhosa8c96d32009-03-06 09:08:51 +010020#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
Sujith394cf0a2009-02-09 13:26:54 +053021 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
23
24#define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
26
27#define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
29
30#define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
34
35#define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
39 AR_GI##_index : 0) \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
41
42#define CCK_SIFS_TIME 10
43#define CCK_PREAMBLE_BITS 144
44#define CCK_PLCP_BITS 48
45
46#define OFDM_SIFS_TIME 16
47#define OFDM_PREAMBLE_TIME 20
48#define OFDM_PLCP_BITS 22
49#define OFDM_SYMBOL_TIME 4
50
51#define OFDM_SIFS_TIME_HALF 32
52#define OFDM_PREAMBLE_TIME_HALF 40
53#define OFDM_PLCP_BITS_HALF 22
54#define OFDM_SYMBOL_TIME_HALF 8
55
56#define OFDM_SIFS_TIME_QUARTER 64
57#define OFDM_PREAMBLE_TIME_QUARTER 80
58#define OFDM_PLCP_BITS_QUARTER 22
59#define OFDM_SYMBOL_TIME_QUARTER 16
60
61#define INIT_AIFS 2
62#define INIT_CWMIN 15
63#define INIT_CWMIN_11B 31
64#define INIT_CWMAX 1023
65#define INIT_SH_RETRY 10
66#define INIT_LG_RETRY 10
67#define INIT_SSH_RETRY 32
68#define INIT_SLG_RETRY 32
69
70#define ATH9K_SLOT_TIME_6 6
71#define ATH9K_SLOT_TIME_9 9
72#define ATH9K_SLOT_TIME_20 20
73
74#define ATH9K_TXERR_XRETRY 0x01
75#define ATH9K_TXERR_FILT 0x02
76#define ATH9K_TXERR_FIFO 0x04
77#define ATH9K_TXERR_XTXOP 0x08
78#define ATH9K_TXERR_TIMER_EXPIRED 0x10
Luis R. Rodrigueze7824a52009-11-24 02:53:25 -050079#define ATH9K_TX_ACKED 0x20
Felix Fietkau5b479a02009-12-24 14:04:32 +010080#define ATH9K_TXERR_MASK \
81 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
82 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
Sujith394cf0a2009-02-09 13:26:54 +053083
84#define ATH9K_TX_BA 0x01
85#define ATH9K_TX_PWRMGMT 0x02
86#define ATH9K_TX_DESC_CFG_ERR 0x04
87#define ATH9K_TX_DATA_UNDERRUN 0x08
88#define ATH9K_TX_DELIM_UNDERRUN 0x10
89#define ATH9K_TX_SW_ABORTED 0x40
90#define ATH9K_TX_SW_FILTERED 0x80
91
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -050092/* 64 bytes */
Sujith394cf0a2009-02-09 13:26:54 +053093#define MIN_TX_FIFO_THRESHOLD 0x1
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -050094
95/*
96 * Single stream device AR9285 and AR9271 require 2 KB
97 * to work around a hardware issue, all other devices
98 * have can use the max 4 KB limit.
99 */
Sujith394cf0a2009-02-09 13:26:54 +0530100#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
Sujith394cf0a2009-02-09 13:26:54 +0530101
102struct ath_tx_status {
103 u32 ts_tstamp;
104 u16 ts_seqnum;
105 u8 ts_status;
106 u8 ts_ratecode;
107 u8 ts_rateindex;
108 int8_t ts_rssi;
109 u8 ts_shortretry;
110 u8 ts_longretry;
111 u8 ts_virtcol;
112 u8 ts_antenna;
113 u8 ts_flags;
114 int8_t ts_rssi_ctl0;
115 int8_t ts_rssi_ctl1;
116 int8_t ts_rssi_ctl2;
117 int8_t ts_rssi_ext0;
118 int8_t ts_rssi_ext1;
119 int8_t ts_rssi_ext2;
120 u8 pad[3];
121 u32 ba_low;
122 u32 ba_high;
123 u32 evm0;
124 u32 evm1;
125 u32 evm2;
126};
127
128struct ath_rx_status {
129 u32 rs_tstamp;
130 u16 rs_datalen;
131 u8 rs_status;
132 u8 rs_phyerr;
133 int8_t rs_rssi;
134 u8 rs_keyix;
135 u8 rs_rate;
136 u8 rs_antenna;
137 u8 rs_more;
138 int8_t rs_rssi_ctl0;
139 int8_t rs_rssi_ctl1;
140 int8_t rs_rssi_ctl2;
141 int8_t rs_rssi_ext0;
142 int8_t rs_rssi_ext1;
143 int8_t rs_rssi_ext2;
144 u8 rs_isaggr;
145 u8 rs_moreaggr;
146 u8 rs_num_delims;
147 u8 rs_flags;
148 u32 evm0;
149 u32 evm1;
150 u32 evm2;
151};
152
153#define ATH9K_RXERR_CRC 0x01
154#define ATH9K_RXERR_PHY 0x02
155#define ATH9K_RXERR_FIFO 0x04
156#define ATH9K_RXERR_DECRYPT 0x08
157#define ATH9K_RXERR_MIC 0x10
158
159#define ATH9K_RX_MORE 0x01
160#define ATH9K_RX_MORE_AGGR 0x02
161#define ATH9K_RX_GI 0x04
162#define ATH9K_RX_2040 0x08
163#define ATH9K_RX_DELIM_CRC_PRE 0x10
164#define ATH9K_RX_DELIM_CRC_POST 0x20
165#define ATH9K_RX_DECRYPT_BUSY 0x40
166
167#define ATH9K_RXKEYIX_INVALID ((u8)-1)
168#define ATH9K_TXKEYIX_INVALID ((u32)-1)
169
Sujith1395d3f2010-01-08 10:36:11 +0530170enum ath9k_phyerr {
171 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
172 ATH9K_PHYERR_TIMING = 1, /* Timing error */
173 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
174 ATH9K_PHYERR_RATE = 3, /* Illegal rate */
175 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
176 ATH9K_PHYERR_RADAR = 5, /* Radar detect */
177 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
178 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
179
180 ATH9K_PHYERR_OFDM_TIMING = 17,
181 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
182 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
183 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
184 ATH9K_PHYERR_OFDM_POWER_DROP = 21,
185 ATH9K_PHYERR_OFDM_SERVICE = 22,
186 ATH9K_PHYERR_OFDM_RESTART = 23,
187 ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
188
189 ATH9K_PHYERR_CCK_TIMING = 25,
190 ATH9K_PHYERR_CCK_HEADER_CRC = 26,
191 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
192 ATH9K_PHYERR_CCK_SERVICE = 30,
193 ATH9K_PHYERR_CCK_RESTART = 31,
194 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32,
195 ATH9K_PHYERR_CCK_POWER_DROP = 33,
196
197 ATH9K_PHYERR_HT_CRC_ERROR = 34,
198 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35,
199 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36,
200
201 ATH9K_PHYERR_MAX = 37,
202};
203
Sujith394cf0a2009-02-09 13:26:54 +0530204struct ath_desc {
205 u32 ds_link;
206 u32 ds_data;
207 u32 ds_ctl0;
208 u32 ds_ctl1;
209 u32 ds_hw[20];
210 union {
211 struct ath_tx_status tx;
212 struct ath_rx_status rx;
213 void *stats;
214 } ds_us;
215 void *ds_vdata;
216} __packed;
217
218#define ds_txstat ds_us.tx
219#define ds_rxstat ds_us.rx
220#define ds_stat ds_us.stats
221
222#define ATH9K_TXDESC_CLRDMASK 0x0001
223#define ATH9K_TXDESC_NOACK 0x0002
224#define ATH9K_TXDESC_RTSENA 0x0004
225#define ATH9K_TXDESC_CTSENA 0x0008
226/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
227 * the descriptor its marked on. We take a tx interrupt to reap
228 * descriptors when the h/w hits an EOL condition or
229 * when the descriptor is specifically marked to generate
230 * an interrupt with this flag. Descriptors should be
231 * marked periodically to insure timely replenishing of the
232 * supply needed for sending frames. Defering interrupts
233 * reduces system load and potentially allows more concurrent
234 * work to be done but if done to aggressively can cause
235 * senders to backup. When the hardware queue is left too
236 * large rate control information may also be too out of
237 * date. An Alternative for this is TX interrupt mitigation
238 * but this needs more testing. */
239#define ATH9K_TXDESC_INTREQ 0x0010
240#define ATH9K_TXDESC_VEOL 0x0020
241#define ATH9K_TXDESC_EXT_ONLY 0x0040
242#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
243#define ATH9K_TXDESC_VMF 0x0100
244#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
245#define ATH9K_TXDESC_CAB 0x0400
246
247#define ATH9K_RXDESC_INTREQ 0x0020
248
249struct ar5416_desc {
250 u32 ds_link;
251 u32 ds_data;
252 u32 ds_ctl0;
253 u32 ds_ctl1;
254 union {
255 struct {
256 u32 ctl2;
257 u32 ctl3;
258 u32 ctl4;
259 u32 ctl5;
260 u32 ctl6;
261 u32 ctl7;
262 u32 ctl8;
263 u32 ctl9;
264 u32 ctl10;
265 u32 ctl11;
266 u32 status0;
267 u32 status1;
268 u32 status2;
269 u32 status3;
270 u32 status4;
271 u32 status5;
272 u32 status6;
273 u32 status7;
274 u32 status8;
275 u32 status9;
276 } tx;
277 struct {
278 u32 status0;
279 u32 status1;
280 u32 status2;
281 u32 status3;
282 u32 status4;
283 u32 status5;
284 u32 status6;
285 u32 status7;
286 u32 status8;
287 } rx;
288 } u;
289} __packed;
290
291#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
292#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
293
294#define ds_ctl2 u.tx.ctl2
295#define ds_ctl3 u.tx.ctl3
296#define ds_ctl4 u.tx.ctl4
297#define ds_ctl5 u.tx.ctl5
298#define ds_ctl6 u.tx.ctl6
299#define ds_ctl7 u.tx.ctl7
300#define ds_ctl8 u.tx.ctl8
301#define ds_ctl9 u.tx.ctl9
302#define ds_ctl10 u.tx.ctl10
303#define ds_ctl11 u.tx.ctl11
304
305#define ds_txstatus0 u.tx.status0
306#define ds_txstatus1 u.tx.status1
307#define ds_txstatus2 u.tx.status2
308#define ds_txstatus3 u.tx.status3
309#define ds_txstatus4 u.tx.status4
310#define ds_txstatus5 u.tx.status5
311#define ds_txstatus6 u.tx.status6
312#define ds_txstatus7 u.tx.status7
313#define ds_txstatus8 u.tx.status8
314#define ds_txstatus9 u.tx.status9
315
316#define ds_rxstatus0 u.rx.status0
317#define ds_rxstatus1 u.rx.status1
318#define ds_rxstatus2 u.rx.status2
319#define ds_rxstatus3 u.rx.status3
320#define ds_rxstatus4 u.rx.status4
321#define ds_rxstatus5 u.rx.status5
322#define ds_rxstatus6 u.rx.status6
323#define ds_rxstatus7 u.rx.status7
324#define ds_rxstatus8 u.rx.status8
325
326#define AR_FrameLen 0x00000fff
327#define AR_VirtMoreFrag 0x00001000
328#define AR_TxCtlRsvd00 0x0000e000
329#define AR_XmitPower 0x003f0000
330#define AR_XmitPower_S 16
331#define AR_RTSEnable 0x00400000
332#define AR_VEOL 0x00800000
333#define AR_ClrDestMask 0x01000000
334#define AR_TxCtlRsvd01 0x1e000000
335#define AR_TxIntrReq 0x20000000
336#define AR_DestIdxValid 0x40000000
337#define AR_CTSEnable 0x80000000
338
339#define AR_BufLen 0x00000fff
340#define AR_TxMore 0x00001000
341#define AR_DestIdx 0x000fe000
342#define AR_DestIdx_S 13
343#define AR_FrameType 0x00f00000
344#define AR_FrameType_S 20
345#define AR_NoAck 0x01000000
346#define AR_InsertTS 0x02000000
347#define AR_CorruptFCS 0x04000000
348#define AR_ExtOnly 0x08000000
349#define AR_ExtAndCtl 0x10000000
350#define AR_MoreAggr 0x20000000
351#define AR_IsAggr 0x40000000
352
353#define AR_BurstDur 0x00007fff
354#define AR_BurstDur_S 0
355#define AR_DurUpdateEna 0x00008000
356#define AR_XmitDataTries0 0x000f0000
357#define AR_XmitDataTries0_S 16
358#define AR_XmitDataTries1 0x00f00000
359#define AR_XmitDataTries1_S 20
360#define AR_XmitDataTries2 0x0f000000
361#define AR_XmitDataTries2_S 24
362#define AR_XmitDataTries3 0xf0000000
363#define AR_XmitDataTries3_S 28
364
365#define AR_XmitRate0 0x000000ff
366#define AR_XmitRate0_S 0
367#define AR_XmitRate1 0x0000ff00
368#define AR_XmitRate1_S 8
369#define AR_XmitRate2 0x00ff0000
370#define AR_XmitRate2_S 16
371#define AR_XmitRate3 0xff000000
372#define AR_XmitRate3_S 24
373
374#define AR_PacketDur0 0x00007fff
375#define AR_PacketDur0_S 0
376#define AR_RTSCTSQual0 0x00008000
377#define AR_PacketDur1 0x7fff0000
378#define AR_PacketDur1_S 16
379#define AR_RTSCTSQual1 0x80000000
380
381#define AR_PacketDur2 0x00007fff
382#define AR_PacketDur2_S 0
383#define AR_RTSCTSQual2 0x00008000
384#define AR_PacketDur3 0x7fff0000
385#define AR_PacketDur3_S 16
386#define AR_RTSCTSQual3 0x80000000
387
388#define AR_AggrLen 0x0000ffff
389#define AR_AggrLen_S 0
390#define AR_TxCtlRsvd60 0x00030000
391#define AR_PadDelim 0x03fc0000
392#define AR_PadDelim_S 18
393#define AR_EncrType 0x0c000000
394#define AR_EncrType_S 26
395#define AR_TxCtlRsvd61 0xf0000000
396
397#define AR_2040_0 0x00000001
398#define AR_GI0 0x00000002
399#define AR_ChainSel0 0x0000001c
400#define AR_ChainSel0_S 2
401#define AR_2040_1 0x00000020
402#define AR_GI1 0x00000040
403#define AR_ChainSel1 0x00000380
404#define AR_ChainSel1_S 7
405#define AR_2040_2 0x00000400
406#define AR_GI2 0x00000800
407#define AR_ChainSel2 0x00007000
408#define AR_ChainSel2_S 12
409#define AR_2040_3 0x00008000
410#define AR_GI3 0x00010000
411#define AR_ChainSel3 0x000e0000
412#define AR_ChainSel3_S 17
413#define AR_RTSCTSRate 0x0ff00000
414#define AR_RTSCTSRate_S 20
415#define AR_TxCtlRsvd70 0xf0000000
416
417#define AR_TxRSSIAnt00 0x000000ff
418#define AR_TxRSSIAnt00_S 0
419#define AR_TxRSSIAnt01 0x0000ff00
420#define AR_TxRSSIAnt01_S 8
421#define AR_TxRSSIAnt02 0x00ff0000
422#define AR_TxRSSIAnt02_S 16
423#define AR_TxStatusRsvd00 0x3f000000
424#define AR_TxBaStatus 0x40000000
425#define AR_TxStatusRsvd01 0x80000000
426
Luis R. Rodrigueze7824a52009-11-24 02:53:25 -0500427/*
428 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
429 * transmitted successfully. If clear, no ACK or BA was received to indicate
430 * successful transmission when we were expecting an ACK or BA.
431 */
Sujith394cf0a2009-02-09 13:26:54 +0530432#define AR_FrmXmitOK 0x00000001
433#define AR_ExcessiveRetries 0x00000002
434#define AR_FIFOUnderrun 0x00000004
435#define AR_Filtered 0x00000008
436#define AR_RTSFailCnt 0x000000f0
437#define AR_RTSFailCnt_S 4
438#define AR_DataFailCnt 0x00000f00
439#define AR_DataFailCnt_S 8
440#define AR_VirtRetryCnt 0x0000f000
441#define AR_VirtRetryCnt_S 12
442#define AR_TxDelimUnderrun 0x00010000
443#define AR_TxDataUnderrun 0x00020000
444#define AR_DescCfgErr 0x00040000
445#define AR_TxTimerExpired 0x00080000
446#define AR_TxStatusRsvd10 0xfff00000
447
448#define AR_SendTimestamp ds_txstatus2
449#define AR_BaBitmapLow ds_txstatus3
450#define AR_BaBitmapHigh ds_txstatus4
451
452#define AR_TxRSSIAnt10 0x000000ff
453#define AR_TxRSSIAnt10_S 0
454#define AR_TxRSSIAnt11 0x0000ff00
455#define AR_TxRSSIAnt11_S 8
456#define AR_TxRSSIAnt12 0x00ff0000
457#define AR_TxRSSIAnt12_S 16
458#define AR_TxRSSICombined 0xff000000
459#define AR_TxRSSICombined_S 24
460
461#define AR_TxEVM0 ds_txstatus5
462#define AR_TxEVM1 ds_txstatus6
463#define AR_TxEVM2 ds_txstatus7
464
465#define AR_TxDone 0x00000001
466#define AR_SeqNum 0x00001ffe
467#define AR_SeqNum_S 1
468#define AR_TxStatusRsvd80 0x0001e000
469#define AR_TxOpExceeded 0x00020000
470#define AR_TxStatusRsvd81 0x001c0000
471#define AR_FinalTxIdx 0x00600000
472#define AR_FinalTxIdx_S 21
473#define AR_TxStatusRsvd82 0x01800000
474#define AR_PowerMgmt 0x02000000
475#define AR_TxStatusRsvd83 0xfc000000
476
477#define AR_RxCTLRsvd00 0xffffffff
478
479#define AR_BufLen 0x00000fff
480#define AR_RxCtlRsvd00 0x00001000
481#define AR_RxIntrReq 0x00002000
482#define AR_RxCtlRsvd01 0xffffc000
483
484#define AR_RxRSSIAnt00 0x000000ff
485#define AR_RxRSSIAnt00_S 0
486#define AR_RxRSSIAnt01 0x0000ff00
487#define AR_RxRSSIAnt01_S 8
488#define AR_RxRSSIAnt02 0x00ff0000
489#define AR_RxRSSIAnt02_S 16
490#define AR_RxRate 0xff000000
491#define AR_RxRate_S 24
492#define AR_RxStatusRsvd00 0xff000000
493
494#define AR_DataLen 0x00000fff
495#define AR_RxMore 0x00001000
496#define AR_NumDelim 0x003fc000
497#define AR_NumDelim_S 14
498#define AR_RxStatusRsvd10 0xff800000
499
500#define AR_RcvTimestamp ds_rxstatus2
501
502#define AR_GI 0x00000001
503#define AR_2040 0x00000002
504#define AR_Parallel40 0x00000004
505#define AR_Parallel40_S 2
506#define AR_RxStatusRsvd30 0x000000f8
507#define AR_RxAntenna 0xffffff00
508#define AR_RxAntenna_S 8
509
510#define AR_RxRSSIAnt10 0x000000ff
511#define AR_RxRSSIAnt10_S 0
512#define AR_RxRSSIAnt11 0x0000ff00
513#define AR_RxRSSIAnt11_S 8
514#define AR_RxRSSIAnt12 0x00ff0000
515#define AR_RxRSSIAnt12_S 16
516#define AR_RxRSSICombined 0xff000000
517#define AR_RxRSSICombined_S 24
518
519#define AR_RxEVM0 ds_rxstatus4
520#define AR_RxEVM1 ds_rxstatus5
521#define AR_RxEVM2 ds_rxstatus6
522
523#define AR_RxDone 0x00000001
524#define AR_RxFrameOK 0x00000002
525#define AR_CRCErr 0x00000004
526#define AR_DecryptCRCErr 0x00000008
527#define AR_PHYErr 0x00000010
528#define AR_MichaelErr 0x00000020
529#define AR_PreDelimCRCErr 0x00000040
530#define AR_RxStatusRsvd70 0x00000080
531#define AR_RxKeyIdxValid 0x00000100
532#define AR_KeyIdx 0x0000fe00
533#define AR_KeyIdx_S 9
534#define AR_PHYErrCode 0x0000ff00
535#define AR_PHYErrCode_S 8
536#define AR_RxMoreAggr 0x00010000
537#define AR_RxAggr 0x00020000
538#define AR_PostDelimCRCErr 0x00040000
539#define AR_RxStatusRsvd71 0x3ff80000
540#define AR_DecryptBusyErr 0x40000000
541#define AR_KeyMiss 0x80000000
542
543enum ath9k_tx_queue {
544 ATH9K_TX_QUEUE_INACTIVE = 0,
545 ATH9K_TX_QUEUE_DATA,
546 ATH9K_TX_QUEUE_BEACON,
547 ATH9K_TX_QUEUE_CAB,
548 ATH9K_TX_QUEUE_UAPSD,
549 ATH9K_TX_QUEUE_PSPOLL
550};
551
552#define ATH9K_NUM_TX_QUEUES 10
553
554enum ath9k_tx_queue_subtype {
555 ATH9K_WME_AC_BK = 0,
556 ATH9K_WME_AC_BE,
557 ATH9K_WME_AC_VI,
558 ATH9K_WME_AC_VO,
559 ATH9K_WME_UPSD
560};
561
562enum ath9k_tx_queue_flags {
563 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
564 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
565 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
566 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
567 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
568 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
569 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
570 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
571 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
572};
573
574#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
575#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
576
577#define ATH9K_DECOMP_MASK_SIZE 128
578#define ATH9K_READY_TIME_LO_BOUND 50
579#define ATH9K_READY_TIME_HI_BOUND 96
580
581enum ath9k_pkt_type {
582 ATH9K_PKT_TYPE_NORMAL = 0,
583 ATH9K_PKT_TYPE_ATIM,
584 ATH9K_PKT_TYPE_PSPOLL,
585 ATH9K_PKT_TYPE_BEACON,
586 ATH9K_PKT_TYPE_PROBE_RESP,
587 ATH9K_PKT_TYPE_CHIRP,
588 ATH9K_PKT_TYPE_GRP_POLL,
589};
590
591struct ath9k_tx_queue_info {
592 u32 tqi_ver;
593 enum ath9k_tx_queue tqi_type;
594 enum ath9k_tx_queue_subtype tqi_subtype;
595 enum ath9k_tx_queue_flags tqi_qflags;
596 u32 tqi_priority;
597 u32 tqi_aifs;
598 u32 tqi_cwmin;
599 u32 tqi_cwmax;
600 u16 tqi_shretry;
601 u16 tqi_lgretry;
602 u32 tqi_cbrPeriod;
603 u32 tqi_cbrOverflowLimit;
604 u32 tqi_burstTime;
605 u32 tqi_readyTime;
606 u32 tqi_physCompBuf;
607 u32 tqi_intFlags;
608};
609
610enum ath9k_rx_filter {
611 ATH9K_RX_FILTER_UCAST = 0x00000001,
612 ATH9K_RX_FILTER_MCAST = 0x00000002,
613 ATH9K_RX_FILTER_BCAST = 0x00000004,
614 ATH9K_RX_FILTER_CONTROL = 0x00000008,
615 ATH9K_RX_FILTER_BEACON = 0x00000010,
616 ATH9K_RX_FILTER_PROM = 0x00000020,
617 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
Sujith394cf0a2009-02-09 13:26:54 +0530618 ATH9K_RX_FILTER_PHYERR = 0x00000100,
Vasanthakumar Thiagarajandbaaa142009-02-19 15:41:52 +0530619 ATH9K_RX_FILTER_MYBEACON = 0x00000200,
Sujith7ea310b2009-09-03 12:08:43 +0530620 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
Vasanthakumar Thiagarajandbaaa142009-02-19 15:41:52 +0530621 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
Sujith394cf0a2009-02-09 13:26:54 +0530622 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
Jouni Malinenb93bce22009-03-03 19:23:30 +0200623 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
Sujith394cf0a2009-02-09 13:26:54 +0530624};
625
626#define ATH9K_RATESERIES_RTS_CTS 0x0001
627#define ATH9K_RATESERIES_2040 0x0002
628#define ATH9K_RATESERIES_HALFGI 0x0004
629
630struct ath9k_11n_rate_series {
631 u32 Tries;
632 u32 Rate;
633 u32 PktDuration;
634 u32 ChSel;
635 u32 RateFlags;
636};
637
638struct ath9k_keyval {
639 u8 kv_type;
640 u8 kv_pad;
641 u16 kv_len;
Jouni Malinen672903b2009-03-02 15:06:31 +0200642 u8 kv_val[16]; /* TK */
643 u8 kv_mic[8]; /* Michael MIC key */
644 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
645 * supports both MIC keys in the same key cache entry;
646 * in that case, kv_mic is the RX key) */
Sujith394cf0a2009-02-09 13:26:54 +0530647};
648
649enum ath9k_key_type {
650 ATH9K_KEY_TYPE_CLEAR,
651 ATH9K_KEY_TYPE_WEP,
652 ATH9K_KEY_TYPE_AES,
653 ATH9K_KEY_TYPE_TKIP,
654};
655
656enum ath9k_cipher {
657 ATH9K_CIPHER_WEP = 0,
658 ATH9K_CIPHER_AES_OCB = 1,
659 ATH9K_CIPHER_AES_CCM = 2,
660 ATH9K_CIPHER_CKIP = 3,
661 ATH9K_CIPHER_TKIP = 4,
662 ATH9K_CIPHER_CLR = 5,
663 ATH9K_CIPHER_MIC = 127
664};
665
Sujithcbe61d82009-02-09 13:27:12 +0530666struct ath_hw;
Sujith394cf0a2009-02-09 13:26:54 +0530667struct ath9k_channel;
Sujith394cf0a2009-02-09 13:26:54 +0530668
Sujithcbe61d82009-02-09 13:27:12 +0530669u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
Sujith54e4cec2009-08-07 09:45:09 +0530670void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
671void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
Sujithcbe61d82009-02-09 13:27:12 +0530672u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
673bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
674bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
Sujith54e4cec2009-08-07 09:45:09 +0530675void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530676 u32 segLen, bool firstSeg,
677 bool lastSeg, const struct ath_desc *ds0);
Sujithcbe61d82009-02-09 13:27:12 +0530678void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
679int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds);
680void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530681 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
682 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
Sujithcbe61d82009-02-09 13:27:12 +0530683void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530684 struct ath_desc *lastds,
685 u32 durUpdateEn, u32 rtsctsRate,
686 u32 rtsctsDuration,
687 struct ath9k_11n_rate_series series[],
688 u32 nseries, u32 flags);
Sujithcbe61d82009-02-09 13:27:12 +0530689void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530690 u32 aggrLen);
Sujithcbe61d82009-02-09 13:27:12 +0530691void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530692 u32 numDelims);
Sujithcbe61d82009-02-09 13:27:12 +0530693void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
694void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
695void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530696 u32 burstDuration);
Sujithcbe61d82009-02-09 13:27:12 +0530697void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530698 u32 vmf);
Sujithcbe61d82009-02-09 13:27:12 +0530699void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
700bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
Sujith394cf0a2009-02-09 13:26:54 +0530701 const struct ath9k_tx_queue_info *qinfo);
Sujithcbe61d82009-02-09 13:27:12 +0530702bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
Sujith394cf0a2009-02-09 13:26:54 +0530703 struct ath9k_tx_queue_info *qinfo);
Sujithcbe61d82009-02-09 13:27:12 +0530704int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
Sujith394cf0a2009-02-09 13:26:54 +0530705 const struct ath9k_tx_queue_info *qinfo);
Sujithcbe61d82009-02-09 13:27:12 +0530706bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
707bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
708int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530709 u32 pa, struct ath_desc *nds, u64 tsf);
Sujith54e4cec2009-08-07 09:45:09 +0530710void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
Sujith394cf0a2009-02-09 13:26:54 +0530711 u32 size, u32 flags);
Sujithcbe61d82009-02-09 13:27:12 +0530712bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
713void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
714void ath9k_hw_rxena(struct ath_hw *ah);
715void ath9k_hw_startpcureceive(struct ath_hw *ah);
716void ath9k_hw_stoppcurecv(struct ath_hw *ah);
717bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
Luis R. Rodriguez536b3a72009-10-06 21:19:11 -0400718int ath9k_hw_beaconq_setup(struct ath_hw *ah);
Sujith394cf0a2009-02-09 13:26:54 +0530719
720#endif /* MAC_H */