blob: c3ef1ad26b6a29b0f86124fc7fcb2276aa08a034 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -06001/dts-v1/;
2
Grant Likely8e267f32011-07-19 17:26:54 -06003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Harmony evaluation board";
7 compatible = "nvidia,harmony", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -060011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
32 "spia", "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc";
69 nvidia,function = "i2c2";
70 };
71 dta {
72 nvidia,pins = "dta", "dtd";
73 nvidia,function = "sdio2";
74 };
75 dtb {
76 nvidia,pins = "dtb", "dtc", "dte";
77 nvidia,function = "rsvd1";
78 };
79 dtf {
80 nvidia,pins = "dtf";
81 nvidia,function = "i2c3";
82 };
83 gmc {
84 nvidia,pins = "gmc";
85 nvidia,function = "uartd";
86 };
87 gpu7 {
88 nvidia,pins = "gpu7";
89 nvidia,function = "rtck";
90 };
91 gpv {
92 nvidia,pins = "gpv", "slxa", "slxk";
93 nvidia,function = "pcie";
94 };
95 hdint {
96 nvidia,pins = "hdint", "pta";
97 nvidia,function = "hdmi";
98 };
99 i2cp {
100 nvidia,pins = "i2cp";
101 nvidia,function = "i2cp";
102 };
103 irrx {
104 nvidia,pins = "irrx", "irtx";
105 nvidia,function = "uarta";
106 };
107 kbca {
108 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
109 "kbce", "kbcf";
110 nvidia,function = "kbc";
111 };
112 lcsn {
113 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
114 "ld3", "ld4", "ld5", "ld6", "ld7",
115 "ld8", "ld9", "ld10", "ld11", "ld12",
116 "ld13", "ld14", "ld15", "ld16", "ld17",
117 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
118 "lhs", "lm0", "lm1", "lpp", "lpw0",
119 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
120 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
121 "lvs";
122 nvidia,function = "displaya";
123 };
124 owc {
125 nvidia,pins = "owc", "spdi", "spdo", "uac";
126 nvidia,function = "rsvd2";
127 };
128 pmc {
129 nvidia,pins = "pmc";
130 nvidia,function = "pwr_on";
131 };
132 rm {
133 nvidia,pins = "rm";
134 nvidia,function = "i2c1";
135 };
136 sdb {
137 nvidia,pins = "sdb", "sdc", "sdd";
138 nvidia,function = "pwm";
139 };
140 sdio1 {
141 nvidia,pins = "sdio1";
142 nvidia,function = "sdio1";
143 };
144 slxc {
145 nvidia,pins = "slxc", "slxd";
146 nvidia,function = "spdif";
147 };
148 spid {
149 nvidia,pins = "spid", "spie", "spif";
150 nvidia,function = "spi1";
151 };
152 spig {
153 nvidia,pins = "spig", "spih";
154 nvidia,function = "spi2_alt";
155 };
156 uaa {
157 nvidia,pins = "uaa", "uab", "uda";
158 nvidia,function = "ulpi";
159 };
160 uad {
161 nvidia,pins = "uad";
162 nvidia,function = "irda";
163 };
164 uca {
165 nvidia,pins = "uca", "ucb";
166 nvidia,function = "uartc";
167 };
168 conf_ata {
169 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600170 "cdev1", "cdev2", "dap1", "dtb", "gma",
171 "gmb", "gmc", "gmd", "gme", "gpu7",
172 "gpv", "i2cp", "pta", "rm", "slxa",
173 "slxk", "spia", "spib", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600174 nvidia,pull = <0>;
175 nvidia,tristate = <0>;
176 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600177 conf_ck32 {
178 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
179 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
180 nvidia,pull = <0>;
181 };
Stephen Warren563da212012-04-13 16:35:20 -0600182 conf_csus {
183 nvidia,pins = "csus", "spid", "spif";
184 nvidia,pull = <1>;
185 nvidia,tristate = <1>;
186 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600187 conf_crtp {
188 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
189 "dtc", "dte", "dtf", "gpu", "sdio1",
190 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600191 "uda";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600192 nvidia,pull = <0>;
193 nvidia,tristate = <1>;
194 };
195 conf_ddc {
196 nvidia,pins = "ddc", "dta", "dtd", "kbca",
197 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
198 "sdc";
199 nvidia,pull = <2>;
200 nvidia,tristate = <0>;
201 };
202 conf_hdint {
203 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
204 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
205 "lvp0", "owc", "sdb";
206 nvidia,tristate = <1>;
207 };
208 conf_irrx {
209 nvidia,pins = "irrx", "irtx", "sdd", "spic",
210 "spie", "spih", "uaa", "uab", "uad",
211 "uca", "ucb";
212 nvidia,pull = <2>;
213 nvidia,tristate = <1>;
214 };
215 conf_lc {
216 nvidia,pins = "lc", "ls";
217 nvidia,pull = <2>;
218 };
219 conf_ld0 {
220 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
221 "ld5", "ld6", "ld7", "ld8", "ld9",
222 "ld10", "ld11", "ld12", "ld13", "ld14",
223 "ld15", "ld16", "ld17", "ldi", "lhp0",
224 "lhp1", "lhp2", "lhs", "lm0", "lpp",
225 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
226 "lvs", "pmc";
227 nvidia,tristate = <0>;
228 };
229 conf_ld17_0 {
230 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
231 "ld23_22";
232 nvidia,pull = <1>;
233 };
234 };
235 };
236
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600237 i2s@70002800 {
238 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600239 };
240
241 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600242 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600243 clock-frequency = <216000000>;
244 };
245
Grant Likely8e267f32011-07-19 17:26:54 -0600246 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600247 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600248 clock-frequency = <400000>;
249
Stephen Warren797acf72012-01-11 16:09:57 -0700250 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600251 compatible = "wlf,wm8903";
252 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700253 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600254 interrupts = <187 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600255
256 gpio-controller;
257 #gpio-cells = <2>;
258
Stephen Warren797acf72012-01-11 16:09:57 -0700259 micdet-cfg = <0>;
260 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600261 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600262 };
263 };
264
265 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600266 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600267 clock-frequency = <400000>;
268 };
269
270 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600271 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600272 clock-frequency = <400000>;
273 };
274
275 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600276 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600277 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000278
279 pmic: tps6586x@34 {
280 compatible = "ti,tps6586x";
281 reg = <0x34>;
282 interrupts = <0 86 0x4>;
283
Stephen Warrenbe972c32012-09-11 11:40:04 -0600284 ti,system-power-controller;
285
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000286 #gpio-cells = <2>;
287 gpio-controller;
288
289 sys-supply = <&vdd_5v0_reg>;
290 vin-sm0-supply = <&sys_reg>;
291 vin-sm1-supply = <&sys_reg>;
292 vin-sm2-supply = <&sys_reg>;
293 vinldo01-supply = <&sm2_reg>;
294 vinldo23-supply = <&sm2_reg>;
295 vinldo4-supply = <&sm2_reg>;
296 vinldo678-supply = <&sm2_reg>;
297 vinldo9-supply = <&sm2_reg>;
298
299 regulators {
300 #address-cells = <1>;
301 #size-cells = <0>;
302
303 sys_reg: regulator@0 {
304 reg = <0>;
305 regulator-compatible = "sys";
306 regulator-name = "vdd_sys";
307 regulator-always-on;
308 };
309
310 regulator@1 {
311 reg = <1>;
312 regulator-compatible = "sm0";
313 regulator-name = "vdd_sm0,vdd_core";
314 regulator-min-microvolt = <1200000>;
315 regulator-max-microvolt = <1200000>;
316 regulator-always-on;
317 };
318
319 regulator@2 {
320 reg = <2>;
321 regulator-compatible = "sm1";
322 regulator-name = "vdd_sm1,vdd_cpu";
323 regulator-min-microvolt = <1000000>;
324 regulator-max-microvolt = <1000000>;
325 regulator-always-on;
326 };
327
328 sm2_reg: regulator@3 {
329 reg = <3>;
330 regulator-compatible = "sm2";
331 regulator-name = "vdd_sm2,vin_ldo*";
332 regulator-min-microvolt = <3700000>;
333 regulator-max-microvolt = <3700000>;
334 regulator-always-on;
335 };
336
337 regulator@4 {
338 reg = <4>;
339 regulator-compatible = "ldo0";
340 regulator-name = "vdd_ldo0,vddio_pex_clk";
341 regulator-min-microvolt = <3300000>;
342 regulator-max-microvolt = <3300000>;
343 };
344
345 regulator@5 {
346 reg = <5>;
347 regulator-compatible = "ldo1";
348 regulator-name = "vdd_ldo1,avdd_pll*";
349 regulator-min-microvolt = <1100000>;
350 regulator-max-microvolt = <1100000>;
351 regulator-always-on;
352 };
353
354 regulator@6 {
355 reg = <6>;
356 regulator-compatible = "ldo2";
357 regulator-name = "vdd_ldo2,vdd_rtc";
358 regulator-min-microvolt = <1200000>;
359 regulator-max-microvolt = <1200000>;
360 };
361
362 regulator@7 {
363 reg = <7>;
364 regulator-compatible = "ldo3";
365 regulator-name = "vdd_ldo3,avdd_usb*";
366 regulator-min-microvolt = <3300000>;
367 regulator-max-microvolt = <3300000>;
368 regulator-always-on;
369 };
370
371 regulator@8 {
372 reg = <8>;
373 regulator-compatible = "ldo4";
374 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
375 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <1800000>;
377 regulator-always-on;
378 };
379
380 regulator@9 {
381 reg = <9>;
382 regulator-compatible = "ldo5";
383 regulator-name = "vdd_ldo5,vcore_mmc";
384 regulator-min-microvolt = <2850000>;
385 regulator-max-microvolt = <2850000>;
386 regulator-always-on;
387 };
388
389 regulator@10 {
390 reg = <10>;
391 regulator-compatible = "ldo6";
392 regulator-name = "vdd_ldo6,avdd_vdac";
393 regulator-min-microvolt = <1800000>;
394 regulator-max-microvolt = <1800000>;
395 };
396
397 regulator@11 {
398 reg = <11>;
399 regulator-compatible = "ldo7";
Stephen Warren740418e2012-09-20 15:20:39 -0600400 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000401 regulator-min-microvolt = <3300000>;
402 regulator-max-microvolt = <3300000>;
403 };
404
405 regulator@12 {
406 reg = <12>;
407 regulator-compatible = "ldo8";
408 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
409 regulator-min-microvolt = <1800000>;
410 regulator-max-microvolt = <1800000>;
411 };
412
413 regulator@13 {
414 reg = <13>;
415 regulator-compatible = "ldo9";
416 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
417 regulator-min-microvolt = <2850000>;
418 regulator-max-microvolt = <2850000>;
419 regulator-always-on;
420 };
421
422 regulator@14 {
423 reg = <14>;
424 regulator-compatible = "ldo_rtc";
425 regulator-name = "vdd_rtc_out,vdd_cell";
426 regulator-min-microvolt = <3300000>;
427 regulator-max-microvolt = <3300000>;
428 regulator-always-on;
429 };
430 };
431 };
Grant Likely8e267f32011-07-19 17:26:54 -0600432 };
433
Stephen Warrenc04abb32012-05-11 17:03:26 -0600434 pmc {
435 nvidia,invert-interrupt;
436 };
437
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600438 usb@c5000000 {
439 status = "okay";
440 };
441
Stephen Warrenc04abb32012-05-11 17:03:26 -0600442 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600443 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600444 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
445 };
446
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600447 usb@c5008000 {
448 status = "okay";
Stephen Warren797acf72012-01-11 16:09:57 -0700449 };
Grant Likely8e267f32011-07-19 17:26:54 -0600450
Stephen Warrenc04abb32012-05-11 17:03:26 -0600451 sdhci@c8000200 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600452 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600453 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
454 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
455 power-gpios = <&gpio 155 0>; /* gpio PT3 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200456 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600457 };
458
Stephen Warrenc04abb32012-05-11 17:03:26 -0600459 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600460 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600461 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
462 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
463 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200464 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600465 };
466
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000467 regulators {
468 compatible = "simple-bus";
469 #address-cells = <1>;
470 #size-cells = <0>;
471
472 vdd_5v0_reg: regulator@0 {
473 compatible = "regulator-fixed";
474 reg = <0>;
475 regulator-name = "vdd_5v0";
476 regulator-min-microvolt = <5000000>;
477 regulator-max-microvolt = <5000000>;
478 regulator-always-on;
479 };
480
481 regulator@1 {
482 compatible = "regulator-fixed";
483 reg = <1>;
484 regulator-name = "vdd_1v5";
485 regulator-min-microvolt = <1500000>;
486 regulator-max-microvolt = <1500000>;
487 gpio = <&pmic 0 0>;
488 };
489
490 regulator@2 {
491 compatible = "regulator-fixed";
492 reg = <2>;
493 regulator-name = "vdd_1v2";
494 regulator-min-microvolt = <1200000>;
495 regulator-max-microvolt = <1200000>;
496 gpio = <&pmic 1 0>;
497 enable-active-high;
498 };
499
500 regulator@3 {
501 compatible = "regulator-fixed";
502 reg = <3>;
503 regulator-name = "vdd_1v05";
504 regulator-min-microvolt = <1050000>;
505 regulator-max-microvolt = <1050000>;
506 gpio = <&pmic 2 0>;
507 enable-active-high;
508 /* Hack until board-harmony-pcie.c is removed */
509 status = "disabled";
510 };
511
512 regulator@4 {
513 compatible = "regulator-fixed";
514 reg = <4>;
515 regulator-name = "vdd_pnl";
516 regulator-min-microvolt = <2800000>;
517 regulator-max-microvolt = <2800000>;
518 gpio = <&gpio 22 0>; /* gpio PC6 */
519 enable-active-high;
520 };
521
522 regulator@5 {
523 compatible = "regulator-fixed";
524 reg = <5>;
525 regulator-name = "vdd_bl";
526 regulator-min-microvolt = <2800000>;
527 regulator-max-microvolt = <2800000>;
528 gpio = <&gpio 176 0>; /* gpio PW0 */
529 enable-active-high;
530 };
531 };
532
Stephen Warren797acf72012-01-11 16:09:57 -0700533 sound {
534 compatible = "nvidia,tegra-audio-wm8903-harmony",
535 "nvidia,tegra-audio-wm8903";
536 nvidia,model = "NVIDIA Tegra Harmony";
537
538 nvidia,audio-routing =
539 "Headphone Jack", "HPOUTR",
540 "Headphone Jack", "HPOUTL",
541 "Int Spk", "ROP",
542 "Int Spk", "RON",
543 "Int Spk", "LOP",
544 "Int Spk", "LON",
545 "Mic Jack", "MICBIAS",
546 "IN1L", "Mic Jack";
547
548 nvidia,i2s-controller = <&tegra_i2s1>;
549 nvidia,audio-codec = <&wm8903>;
550
551 nvidia,spkr-en-gpios = <&wm8903 2 0>;
552 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
553 nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
554 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
Grant Likely8e267f32011-07-19 17:26:54 -0600555 };
Grant Likely8e267f32011-07-19 17:26:54 -0600556};