blob: 6f926fd2162b20380034add765471f2f72b7f2b0 [file] [log] [blame]
Nobuhiro Iwamatsu4cec1a32008-06-06 17:04:56 +09001/*
2 * linux/arch/sh/boards/renesas/sh7763rdp/setup.c
3 *
4 * Renesas Solutions sh7763rdp board
5 *
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
16#include <linux/input.h>
17#include <linux/mtd/physmap.h>
Nobuhiro Iwamatsu674063c2008-08-08 14:30:06 +090018#include <linux/fb.h>
Nobuhiro Iwamatsu0a766a62008-08-08 14:29:58 +090019#include <linux/io.h>
Paul Mundt7639a452008-10-20 13:02:48 +090020#include <mach/sh7763rdp.h>
Nobuhiro Iwamatsu0a766a62008-08-08 14:29:58 +090021#include <asm/sh_eth.h>
Nobuhiro Iwamatsu674063c2008-08-08 14:30:06 +090022#include <asm/sh7760fb.h>
Nobuhiro Iwamatsu4cec1a32008-06-06 17:04:56 +090023
24/* NOR Flash */
25static struct mtd_partition sh7763rdp_nor_flash_partitions[] = {
26 {
27 .name = "U-Boot",
28 .offset = 0,
29 .size = (2 * 128 * 1024),
30 .mask_flags = MTD_WRITEABLE, /* Read-only */
31 }, {
32 .name = "Linux-Kernel",
33 .offset = MTDPART_OFS_APPEND,
34 .size = (20 * 128 * 1024),
35 }, {
36 .name = "Root Filesystem",
37 .offset = MTDPART_OFS_APPEND,
38 .size = MTDPART_SIZ_FULL,
39 },
40};
41
42static struct physmap_flash_data sh7763rdp_nor_flash_data = {
43 .width = 2,
44 .parts = sh7763rdp_nor_flash_partitions,
45 .nr_parts = ARRAY_SIZE(sh7763rdp_nor_flash_partitions),
46};
47
48static struct resource sh7763rdp_nor_flash_resources[] = {
49 [0] = {
50 .name = "NOR Flash",
51 .start = 0,
52 .end = (64 * 1024 * 1024),
53 .flags = IORESOURCE_MEM,
54 },
55};
56
57static struct platform_device sh7763rdp_nor_flash_device = {
58 .name = "physmap-flash",
59 .resource = sh7763rdp_nor_flash_resources,
60 .num_resources = ARRAY_SIZE(sh7763rdp_nor_flash_resources),
61 .dev = {
62 .platform_data = &sh7763rdp_nor_flash_data,
63 },
64};
65
Nobuhiro Iwamatsu0a766a62008-08-08 14:29:58 +090066/* SH-Ether */
67static struct resource sh_eth_resources[] = {
68 {
69 .start = 0xFEE00800, /* use eth1 */
70 .end = 0xFEE00F7C - 1,
71 .flags = IORESOURCE_MEM,
72 }, {
73 .start = 58, /* irq number */
74 .end = 58,
75 .flags = IORESOURCE_IRQ,
76 },
77};
78
79static struct sh_eth_plat_data sh7763_eth_pdata = {
80 .phy = 1,
81 .edmac_endian = EDMAC_LITTLE_ENDIAN,
82};
83
84static struct platform_device sh7763rdp_eth_device = {
85 .name = "sh-eth",
86 .resource = sh_eth_resources,
87 .num_resources = ARRAY_SIZE(sh_eth_resources),
88 .dev = {
89 .platform_data = &sh7763_eth_pdata,
90 },
91};
92
Nobuhiro Iwamatsu674063c2008-08-08 14:30:06 +090093/* SH7763 LCDC */
94static struct resource sh7763rdp_fb_resources[] = {
95 {
96 .start = 0xFFE80000,
97 .end = 0xFFE80442 - 1,
98 .flags = IORESOURCE_MEM,
99 },
100};
101
102static struct fb_videomode sh7763fb_videomode = {
103 .refresh = 60,
104 .name = "VGA Monitor",
105 .xres = 640,
106 .yres = 480,
107 .pixclock = 10000,
108 .left_margin = 80,
109 .right_margin = 24,
110 .upper_margin = 30,
111 .lower_margin = 1,
112 .hsync_len = 96,
113 .vsync_len = 1,
114 .sync = 0,
115 .vmode = FB_VMODE_NONINTERLACED,
116 .flag = FBINFO_FLAG_DEFAULT,
117};
118
119static struct sh7760fb_platdata sh7763fb_def_pdata = {
120 .def_mode = &sh7763fb_videomode,
121 .ldmtr = (LDMTR_TFT_COLOR_16|LDMTR_MCNT),
122 .lddfr = LDDFR_16BPP_RGB565,
123 .ldpmmr = 0x0000,
124 .ldpspr = 0xFFFF,
125 .ldaclnr = 0x0001,
126 .ldickr = 0x1102,
127 .rotate = 0,
128 .novsync = 0,
129 .blank = NULL,
130};
131
132static struct platform_device sh7763rdp_fb_device = {
133 .name = "sh7760-lcdc",
134 .resource = sh7763rdp_fb_resources,
135 .num_resources = ARRAY_SIZE(sh7763rdp_fb_resources),
136 .dev = {
137 .platform_data = &sh7763fb_def_pdata,
138 },
139};
140
Nobuhiro Iwamatsu4cec1a32008-06-06 17:04:56 +0900141static struct platform_device *sh7763rdp_devices[] __initdata = {
142 &sh7763rdp_nor_flash_device,
Nobuhiro Iwamatsu0a766a62008-08-08 14:29:58 +0900143 &sh7763rdp_eth_device,
Nobuhiro Iwamatsu674063c2008-08-08 14:30:06 +0900144 &sh7763rdp_fb_device,
Nobuhiro Iwamatsu4cec1a32008-06-06 17:04:56 +0900145};
146
147static int __init sh7763rdp_devices_setup(void)
148{
149 return platform_add_devices(sh7763rdp_devices,
150 ARRAY_SIZE(sh7763rdp_devices));
151}
Nobuhiro Iwamatsu0a766a62008-08-08 14:29:58 +0900152device_initcall(sh7763rdp_devices_setup);
Nobuhiro Iwamatsu4cec1a32008-06-06 17:04:56 +0900153
154static void __init sh7763rdp_setup(char **cmdline_p)
155{
156 /* Board version check */
157 if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
158 printk(KERN_INFO "RTE Standard Configuration\n");
159 else
160 printk(KERN_INFO "RTA Standard Configuration\n");
161
162 /* USB pin select bits (clear bit 5-2 to 0) */
163 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
164 /* USBH setup port I controls to other (clear bits 4-9 to 0) */
165 ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR);
166
167 /* Select USB Host controller */
168 ctrl_outw(0x00, USB_USBHSC);
169
170 /* For LCD */
171 /* set PTJ7-1, bits 15-2 of PJCR to 0 */
172 ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR);
173 /* set PTI5, bits 11-10 of PICR to 0 */
174 ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR);
175 ctrl_outw(0, PORT_PKCR);
176 ctrl_outw(0, PORT_PLCR);
177 /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
178 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
179 /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
180 ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
181
182 /* For HAC */
183 /* bit3-0 0100:HAC & SSI1 enable */
184 ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
185 /* bit14 1:SSI_HAC_CLK enable */
186 ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
187
188 /* SH-Ether */
189 ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
190 ctrl_outw(0x0, PORT_PFCR);
191 ctrl_outw(0x0, PORT_PFCR);
192 ctrl_outw(0x0, PORT_PFCR);
193
194 /* MMC */
195 /*selects SCIF and MMC other functions */
196 ctrl_outw(0x0001, PORT_PSEL0);
197 /* MMC clock operates */
198 ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1);
199 ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR);
200 ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
201}
202
203static struct sh_machine_vector mv_sh7763rdp __initmv = {
204 .mv_name = "sh7763drp",
205 .mv_setup = sh7763rdp_setup,
206 .mv_nr_irqs = 112,
207 .mv_init_irq = init_sh7763rdp_IRQ,
208};