Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 11 | #include <linux/host1x.h> |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 12 | #include <linux/idr.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 13 | #include <linux/iommu.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 14 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 15 | #include <drm/drm_atomic.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 16 | #include <drm/drm_atomic_helper.h> |
| 17 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 18 | #include "drm.h" |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 19 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | |
| 21 | #define DRIVER_NAME "tegra" |
| 22 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 23 | #define DRIVER_DATE "20120330" |
| 24 | #define DRIVER_MAJOR 0 |
| 25 | #define DRIVER_MINOR 0 |
| 26 | #define DRIVER_PATCHLEVEL 0 |
| 27 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 28 | #define CARVEOUT_SZ SZ_64M |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 29 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 30 | |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 31 | struct tegra_drm_file { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 32 | struct idr contexts; |
| 33 | struct mutex lock; |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 34 | }; |
| 35 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 36 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
| 37 | struct drm_atomic_state *state) |
| 38 | { |
| 39 | tegra->commit.state = state; |
| 40 | schedule_work(&tegra->commit.work); |
| 41 | } |
| 42 | |
| 43 | static void tegra_atomic_complete(struct tegra_drm *tegra, |
| 44 | struct drm_atomic_state *state) |
| 45 | { |
| 46 | struct drm_device *drm = tegra->drm; |
| 47 | |
| 48 | /* |
| 49 | * Everything below can be run asynchronously without the need to grab |
| 50 | * any modeset locks at all under one condition: It must be guaranteed |
| 51 | * that the asynchronous work has either been cancelled (if the driver |
| 52 | * supports it, which at least requires that the framebuffers get |
| 53 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed |
| 54 | * before the new state gets committed on the software side with |
| 55 | * drm_atomic_helper_swap_state(). |
| 56 | * |
| 57 | * This scheme allows new atomic state updates to be prepared and |
| 58 | * checked in parallel to the asynchronous completion of the previous |
| 59 | * update. Which is important since compositors need to figure out the |
| 60 | * composition of the next frame right after having submitted the |
| 61 | * current layout. |
| 62 | */ |
| 63 | |
Daniel Vetter | 1af434a | 2015-02-22 12:24:19 +0100 | [diff] [blame] | 64 | drm_atomic_helper_commit_modeset_disables(drm, state); |
Daniel Vetter | 1af434a | 2015-02-22 12:24:19 +0100 | [diff] [blame] | 65 | drm_atomic_helper_commit_modeset_enables(drm, state); |
Liu Ying | 2b58e98 | 2016-08-29 17:12:03 +0800 | [diff] [blame] | 66 | drm_atomic_helper_commit_planes(drm, state, |
| 67 | DRM_PLANE_COMMIT_ACTIVE_ONLY); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 68 | |
| 69 | drm_atomic_helper_wait_for_vblanks(drm, state); |
| 70 | |
| 71 | drm_atomic_helper_cleanup_planes(drm, state); |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 72 | drm_atomic_state_put(state); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static void tegra_atomic_work(struct work_struct *work) |
| 76 | { |
| 77 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, |
| 78 | commit.work); |
| 79 | |
| 80 | tegra_atomic_complete(tegra, tegra->commit.state); |
| 81 | } |
| 82 | |
| 83 | static int tegra_atomic_commit(struct drm_device *drm, |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 84 | struct drm_atomic_state *state, bool nonblock) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 85 | { |
| 86 | struct tegra_drm *tegra = drm->dev_private; |
| 87 | int err; |
| 88 | |
| 89 | err = drm_atomic_helper_prepare_planes(drm, state); |
| 90 | if (err) |
| 91 | return err; |
| 92 | |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 93 | /* serialize outstanding nonblocking commits */ |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 94 | mutex_lock(&tegra->commit.lock); |
| 95 | flush_work(&tegra->commit.work); |
| 96 | |
| 97 | /* |
| 98 | * This is the point of no return - everything below never fails except |
| 99 | * when the hw goes bonghits. Which means we can commit the new state on |
| 100 | * the software side now. |
| 101 | */ |
| 102 | |
Daniel Vetter | 5e84c26 | 2016-06-10 00:06:32 +0200 | [diff] [blame] | 103 | drm_atomic_helper_swap_state(state, true); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 104 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 105 | drm_atomic_state_get(state); |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 106 | if (nonblock) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 107 | tegra_atomic_schedule(tegra, state); |
| 108 | else |
| 109 | tegra_atomic_complete(tegra, state); |
| 110 | |
| 111 | mutex_unlock(&tegra->commit.lock); |
| 112 | return 0; |
| 113 | } |
| 114 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 115 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
| 116 | .fb_create = tegra_fb_create, |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 117 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 118 | .output_poll_changed = tegra_fb_output_poll_changed, |
| 119 | #endif |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 120 | .atomic_check = drm_atomic_helper_check, |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 121 | .atomic_commit = tegra_atomic_commit, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 124 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 125 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 126 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 127 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 128 | int err; |
| 129 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 130 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 131 | if (!tegra) |
Terje Bergstrom | 692e6d7 | 2013-03-22 16:34:07 +0200 | [diff] [blame] | 132 | return -ENOMEM; |
| 133 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 134 | if (iommu_present(&platform_bus_type)) { |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 135 | u64 carveout_start, carveout_end, gem_start, gem_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 136 | struct iommu_domain_geometry *geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 137 | unsigned long order; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 138 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 139 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
Dan Carpenter | bf19b88 | 2014-12-04 14:00:35 +0300 | [diff] [blame] | 140 | if (!tegra->domain) { |
| 141 | err = -ENOMEM; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 142 | goto free; |
| 143 | } |
| 144 | |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 145 | geometry = &tegra->domain->geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 146 | gem_start = geometry->aperture_start; |
| 147 | gem_end = geometry->aperture_end - CARVEOUT_SZ; |
| 148 | carveout_start = gem_end + 1; |
| 149 | carveout_end = geometry->aperture_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 150 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 151 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 152 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
| 153 | carveout_start >> order, |
| 154 | carveout_end >> order); |
| 155 | |
| 156 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 157 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 158 | |
| 159 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 160 | mutex_init(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 161 | |
| 162 | DRM_DEBUG("IOMMU apertures:\n"); |
| 163 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 164 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, |
| 165 | carveout_end); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 166 | } |
| 167 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 168 | mutex_init(&tegra->clients_lock); |
| 169 | INIT_LIST_HEAD(&tegra->clients); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 170 | |
| 171 | mutex_init(&tegra->commit.lock); |
| 172 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); |
| 173 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 174 | drm->dev_private = tegra; |
| 175 | tegra->drm = drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 176 | |
| 177 | drm_mode_config_init(drm); |
| 178 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 179 | drm->mode_config.min_width = 0; |
| 180 | drm->mode_config.min_height = 0; |
| 181 | |
| 182 | drm->mode_config.max_width = 4096; |
| 183 | drm->mode_config.max_height = 4096; |
| 184 | |
Alexandre Courbot | 5e91144 | 2016-11-08 16:50:42 +0900 | [diff] [blame] | 185 | drm->mode_config.allow_fb_modifiers = true; |
| 186 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 187 | drm->mode_config.funcs = &tegra_drm_mode_funcs; |
| 188 | |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 189 | err = tegra_drm_fb_prepare(drm); |
| 190 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 191 | goto config; |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 192 | |
| 193 | drm_kms_helper_poll_init(drm); |
| 194 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 195 | err = host1x_device_init(device); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 196 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 197 | goto fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 198 | |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 199 | /* |
| 200 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 201 | * core, so we need to set this manually in order to allow the |
| 202 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 203 | */ |
Ville Syrjälä | 4423843 | 2013-10-04 14:53:37 +0300 | [diff] [blame] | 204 | drm->irq_enabled = true; |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 205 | |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 206 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 207 | drm->max_vblank_count = 0xffffffff; |
| 208 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 209 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 210 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 211 | goto device; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 212 | |
Thierry Reding | 31930d4 | 2015-07-02 17:04:06 +0200 | [diff] [blame] | 213 | drm_mode_config_reset(drm); |
| 214 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 215 | err = tegra_drm_fb_init(drm); |
| 216 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 217 | goto vblank; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 218 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 219 | return 0; |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 220 | |
| 221 | vblank: |
| 222 | drm_vblank_cleanup(drm); |
| 223 | device: |
| 224 | host1x_device_exit(device); |
| 225 | fbdev: |
| 226 | drm_kms_helper_poll_fini(drm); |
| 227 | tegra_drm_fb_free(drm); |
| 228 | config: |
| 229 | drm_mode_config_cleanup(drm); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 230 | |
| 231 | if (tegra->domain) { |
| 232 | iommu_domain_free(tegra->domain); |
| 233 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 234 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 235 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 236 | } |
| 237 | free: |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 238 | kfree(tegra); |
| 239 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 240 | } |
| 241 | |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 242 | static void tegra_drm_unload(struct drm_device *drm) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 243 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 244 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 245 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 246 | int err; |
| 247 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 248 | drm_kms_helper_poll_fini(drm); |
| 249 | tegra_drm_fb_exit(drm); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 250 | drm_mode_config_cleanup(drm); |
Thierry Reding | 4aa3df7 | 2014-11-24 16:27:13 +0100 | [diff] [blame] | 251 | drm_vblank_cleanup(drm); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 252 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 253 | err = host1x_device_exit(device); |
| 254 | if (err < 0) |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 255 | return; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 256 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 257 | if (tegra->domain) { |
| 258 | iommu_domain_free(tegra->domain); |
| 259 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 260 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 261 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 262 | } |
| 263 | |
Thierry Reding | 1053f4dd | 2014-11-04 16:17:55 +0100 | [diff] [blame] | 264 | kfree(tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 268 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 269 | struct tegra_drm_file *fpriv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 270 | |
| 271 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 272 | if (!fpriv) |
| 273 | return -ENOMEM; |
| 274 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 275 | idr_init(&fpriv->contexts); |
| 276 | mutex_init(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 277 | filp->driver_priv = fpriv; |
| 278 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 279 | return 0; |
| 280 | } |
| 281 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 282 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 283 | { |
| 284 | context->client->ops->close_channel(context); |
| 285 | kfree(context); |
| 286 | } |
| 287 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 288 | static void tegra_drm_lastclose(struct drm_device *drm) |
| 289 | { |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 290 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 291 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 292 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 293 | tegra_fbdev_restore_mode(tegra->fbdev); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 294 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 295 | } |
| 296 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 297 | static struct host1x_bo * |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 298 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 299 | { |
| 300 | struct drm_gem_object *gem; |
| 301 | struct tegra_bo *bo; |
| 302 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 303 | gem = drm_gem_object_lookup(file, handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 304 | if (!gem) |
| 305 | return NULL; |
| 306 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 307 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 308 | |
| 309 | bo = to_tegra_bo(gem); |
| 310 | return &bo->base; |
| 311 | } |
| 312 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 313 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 314 | struct drm_tegra_reloc __user *src, |
| 315 | struct drm_device *drm, |
| 316 | struct drm_file *file) |
| 317 | { |
| 318 | u32 cmdbuf, target; |
| 319 | int err; |
| 320 | |
| 321 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 322 | if (err < 0) |
| 323 | return err; |
| 324 | |
| 325 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 326 | if (err < 0) |
| 327 | return err; |
| 328 | |
| 329 | err = get_user(target, &src->target.handle); |
| 330 | if (err < 0) |
| 331 | return err; |
| 332 | |
David Ung | 31f40f8 | 2015-01-20 18:37:35 -0800 | [diff] [blame] | 333 | err = get_user(dest->target.offset, &src->target.offset); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 334 | if (err < 0) |
| 335 | return err; |
| 336 | |
| 337 | err = get_user(dest->shift, &src->shift); |
| 338 | if (err < 0) |
| 339 | return err; |
| 340 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 341 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 342 | if (!dest->cmdbuf.bo) |
| 343 | return -ENOENT; |
| 344 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 345 | dest->target.bo = host1x_bo_lookup(file, target); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 346 | if (!dest->target.bo) |
| 347 | return -ENOENT; |
| 348 | |
| 349 | return 0; |
| 350 | } |
| 351 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 352 | static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest, |
| 353 | struct drm_tegra_waitchk __user *src, |
| 354 | struct drm_file *file) |
| 355 | { |
| 356 | u32 cmdbuf; |
| 357 | int err; |
| 358 | |
| 359 | err = get_user(cmdbuf, &src->handle); |
| 360 | if (err < 0) |
| 361 | return err; |
| 362 | |
| 363 | err = get_user(dest->offset, &src->offset); |
| 364 | if (err < 0) |
| 365 | return err; |
| 366 | |
| 367 | err = get_user(dest->syncpt_id, &src->syncpt); |
| 368 | if (err < 0) |
| 369 | return err; |
| 370 | |
| 371 | err = get_user(dest->thresh, &src->thresh); |
| 372 | if (err < 0) |
| 373 | return err; |
| 374 | |
| 375 | dest->bo = host1x_bo_lookup(file, cmdbuf); |
| 376 | if (!dest->bo) |
| 377 | return -ENOENT; |
| 378 | |
| 379 | return 0; |
| 380 | } |
| 381 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 382 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 383 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 384 | struct drm_file *file) |
| 385 | { |
| 386 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 387 | unsigned int num_relocs = args->num_relocs; |
| 388 | unsigned int num_waitchks = args->num_waitchks; |
| 389 | struct drm_tegra_cmdbuf __user *cmdbufs = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 390 | (void __user *)(uintptr_t)args->cmdbufs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 391 | struct drm_tegra_reloc __user *relocs = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 392 | (void __user *)(uintptr_t)args->relocs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 393 | struct drm_tegra_waitchk __user *waitchks = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 394 | (void __user *)(uintptr_t)args->waitchks; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 395 | struct drm_tegra_syncpt syncpt; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 396 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
| 397 | struct host1x_syncpt *sp; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 398 | struct host1x_job *job; |
| 399 | int err; |
| 400 | |
| 401 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 402 | if (args->num_syncpts != 1) |
| 403 | return -EINVAL; |
| 404 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 405 | /* We don't yet support waitchks */ |
| 406 | if (args->num_waitchks != 0) |
| 407 | return -EINVAL; |
| 408 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 409 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
| 410 | args->num_relocs, args->num_waitchks); |
| 411 | if (!job) |
| 412 | return -ENOMEM; |
| 413 | |
| 414 | job->num_relocs = args->num_relocs; |
| 415 | job->num_waitchk = args->num_waitchks; |
| 416 | job->client = (u32)args->context; |
| 417 | job->class = context->client->base.class; |
| 418 | job->serialize = true; |
| 419 | |
| 420 | while (num_cmdbufs) { |
| 421 | struct drm_tegra_cmdbuf cmdbuf; |
| 422 | struct host1x_bo *bo; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 423 | struct tegra_bo *obj; |
| 424 | u64 offset; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 425 | |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 426 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
| 427 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 428 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 429 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 430 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 431 | /* |
| 432 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 433 | * value means the words count is malformed. |
| 434 | */ |
| 435 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 436 | err = -EINVAL; |
| 437 | goto fail; |
| 438 | } |
| 439 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 440 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 441 | if (!bo) { |
| 442 | err = -ENOENT; |
| 443 | goto fail; |
| 444 | } |
| 445 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 446 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 447 | obj = host1x_to_tegra_bo(bo); |
| 448 | |
| 449 | /* |
| 450 | * Gather buffer base address must be 4-bytes aligned, |
| 451 | * unaligned offset is malformed and cause commands stream |
| 452 | * corruption on the buffer address relocation. |
| 453 | */ |
| 454 | if (offset & 3 || offset >= obj->gem.size) { |
| 455 | err = -EINVAL; |
| 456 | goto fail; |
| 457 | } |
| 458 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 459 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 460 | num_cmdbufs--; |
| 461 | cmdbufs++; |
| 462 | } |
| 463 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 464 | /* copy and resolve relocations from submit */ |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 465 | while (num_relocs--) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 466 | struct host1x_reloc *reloc; |
| 467 | struct tegra_bo *obj; |
| 468 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 469 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
| 470 | &relocs[num_relocs], drm, |
| 471 | file); |
| 472 | if (err < 0) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 473 | goto fail; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 474 | |
| 475 | reloc = &job->relocarray[num_relocs]; |
| 476 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
| 477 | |
| 478 | /* |
| 479 | * The unaligned cmdbuf offset will cause an unaligned write |
| 480 | * during of the relocations patching, corrupting the commands |
| 481 | * stream. |
| 482 | */ |
| 483 | if (reloc->cmdbuf.offset & 3 || |
| 484 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 485 | err = -EINVAL; |
| 486 | goto fail; |
| 487 | } |
| 488 | |
| 489 | obj = host1x_to_tegra_bo(reloc->target.bo); |
| 490 | |
| 491 | if (reloc->target.offset >= obj->gem.size) { |
| 492 | err = -EINVAL; |
| 493 | goto fail; |
| 494 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 495 | } |
| 496 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 497 | /* copy and resolve waitchks from submit */ |
| 498 | while (num_waitchks--) { |
| 499 | struct host1x_waitchk *wait = &job->waitchk[num_waitchks]; |
| 500 | struct tegra_bo *obj; |
| 501 | |
| 502 | err = host1x_waitchk_copy_from_user(wait, |
| 503 | &waitchks[num_waitchks], |
| 504 | file); |
| 505 | if (err < 0) |
| 506 | goto fail; |
| 507 | |
| 508 | obj = host1x_to_tegra_bo(wait->bo); |
| 509 | |
| 510 | /* |
| 511 | * The unaligned offset will cause an unaligned write during |
| 512 | * of the waitchks patching, corrupting the commands stream. |
| 513 | */ |
| 514 | if (wait->offset & 3 || |
| 515 | wait->offset >= obj->gem.size) { |
| 516 | err = -EINVAL; |
| 517 | goto fail; |
| 518 | } |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 519 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 520 | |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 521 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
| 522 | sizeof(syncpt))) { |
| 523 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 524 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 525 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 526 | |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 527 | /* check whether syncpoint ID is valid */ |
| 528 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 529 | if (!sp) { |
| 530 | err = -ENOENT; |
| 531 | goto fail; |
| 532 | } |
| 533 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 534 | job->is_addr_reg = context->client->ops->is_addr_reg; |
Dmitry Osipenko | 0f563a4 | 2017-06-15 02:18:37 +0300 | [diff] [blame] | 535 | job->is_valid_class = context->client->ops->is_valid_class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 536 | job->syncpt_incrs = syncpt.incrs; |
| 537 | job->syncpt_id = syncpt.id; |
| 538 | job->timeout = 10000; |
| 539 | |
| 540 | if (args->timeout && args->timeout < 10000) |
| 541 | job->timeout = args->timeout; |
| 542 | |
| 543 | err = host1x_job_pin(job, context->client->base.dev); |
| 544 | if (err) |
| 545 | goto fail; |
| 546 | |
| 547 | err = host1x_job_submit(job); |
| 548 | if (err) |
| 549 | goto fail_submit; |
| 550 | |
| 551 | args->fence = job->syncpt_end; |
| 552 | |
| 553 | host1x_job_put(job); |
| 554 | return 0; |
| 555 | |
| 556 | fail_submit: |
| 557 | host1x_job_unpin(job); |
| 558 | fail: |
| 559 | host1x_job_put(job); |
| 560 | return err; |
| 561 | } |
| 562 | |
| 563 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 564 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 565 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 566 | struct drm_file *file) |
| 567 | { |
| 568 | struct drm_tegra_gem_create *args = data; |
| 569 | struct tegra_bo *bo; |
| 570 | |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 571 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 572 | &args->handle); |
| 573 | if (IS_ERR(bo)) |
| 574 | return PTR_ERR(bo); |
| 575 | |
| 576 | return 0; |
| 577 | } |
| 578 | |
| 579 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 580 | struct drm_file *file) |
| 581 | { |
| 582 | struct drm_tegra_gem_mmap *args = data; |
| 583 | struct drm_gem_object *gem; |
| 584 | struct tegra_bo *bo; |
| 585 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 586 | gem = drm_gem_object_lookup(file, args->handle); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 587 | if (!gem) |
| 588 | return -EINVAL; |
| 589 | |
| 590 | bo = to_tegra_bo(gem); |
| 591 | |
David Herrmann | 2bc7b0c | 2013-08-13 14:19:58 +0200 | [diff] [blame] | 592 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 593 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 594 | drm_gem_object_put_unlocked(gem); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 595 | |
| 596 | return 0; |
| 597 | } |
| 598 | |
| 599 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 600 | struct drm_file *file) |
| 601 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 602 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 603 | struct drm_tegra_syncpt_read *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 604 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 605 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 606 | sp = host1x_syncpt_get(host, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 607 | if (!sp) |
| 608 | return -EINVAL; |
| 609 | |
| 610 | args->value = host1x_syncpt_read_min(sp); |
| 611 | return 0; |
| 612 | } |
| 613 | |
| 614 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 615 | struct drm_file *file) |
| 616 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 617 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 618 | struct drm_tegra_syncpt_incr *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 619 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 620 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 621 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 622 | if (!sp) |
| 623 | return -EINVAL; |
| 624 | |
Arto Merilainen | ebae30b | 2013-05-29 13:26:08 +0300 | [diff] [blame] | 625 | return host1x_syncpt_incr(sp); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 629 | struct drm_file *file) |
| 630 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 631 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 632 | struct drm_tegra_syncpt_wait *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 633 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 634 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 635 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 636 | if (!sp) |
| 637 | return -EINVAL; |
| 638 | |
| 639 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, |
| 640 | &args->value); |
| 641 | } |
| 642 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 643 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 644 | struct tegra_drm_client *client, |
| 645 | struct tegra_drm_context *context) |
| 646 | { |
| 647 | int err; |
| 648 | |
| 649 | err = client->ops->open_channel(client, context); |
| 650 | if (err < 0) |
| 651 | return err; |
| 652 | |
Dmitry Osipenko | d6c153e | 2017-06-15 02:18:25 +0300 | [diff] [blame] | 653 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 654 | if (err < 0) { |
| 655 | client->ops->close_channel(context); |
| 656 | return err; |
| 657 | } |
| 658 | |
| 659 | context->client = client; |
| 660 | context->id = err; |
| 661 | |
| 662 | return 0; |
| 663 | } |
| 664 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 665 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 666 | struct drm_file *file) |
| 667 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 668 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 669 | struct tegra_drm *tegra = drm->dev_private; |
| 670 | struct drm_tegra_open_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 671 | struct tegra_drm_context *context; |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 672 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 673 | int err = -ENODEV; |
| 674 | |
| 675 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 676 | if (!context) |
| 677 | return -ENOMEM; |
| 678 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 679 | mutex_lock(&fpriv->lock); |
| 680 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 681 | list_for_each_entry(client, &tegra->clients, list) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 682 | if (client->base.class == args->client) { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 683 | err = tegra_client_open(fpriv, client, context); |
| 684 | if (err < 0) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 685 | break; |
| 686 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 687 | args->context = context->id; |
| 688 | break; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 689 | } |
| 690 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 691 | if (err < 0) |
| 692 | kfree(context); |
| 693 | |
| 694 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 695 | return err; |
| 696 | } |
| 697 | |
| 698 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 699 | struct drm_file *file) |
| 700 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 701 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 702 | struct drm_tegra_close_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 703 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 704 | int err = 0; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 705 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 706 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 707 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 708 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 709 | if (!context) { |
| 710 | err = -EINVAL; |
| 711 | goto unlock; |
| 712 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 713 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 714 | idr_remove(&fpriv->contexts, context->id); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 715 | tegra_drm_context_free(context); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 716 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 717 | unlock: |
| 718 | mutex_unlock(&fpriv->lock); |
| 719 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 720 | } |
| 721 | |
| 722 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 723 | struct drm_file *file) |
| 724 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 725 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 726 | struct drm_tegra_get_syncpt *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 727 | struct tegra_drm_context *context; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 728 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 729 | int err = 0; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 730 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 731 | mutex_lock(&fpriv->lock); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 732 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 733 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 734 | if (!context) { |
| 735 | err = -ENODEV; |
| 736 | goto unlock; |
| 737 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 738 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 739 | if (args->index >= context->client->base.num_syncpts) { |
| 740 | err = -EINVAL; |
| 741 | goto unlock; |
| 742 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 743 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 744 | syncpt = context->client->base.syncpts[args->index]; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 745 | args->id = host1x_syncpt_id(syncpt); |
| 746 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 747 | unlock: |
| 748 | mutex_unlock(&fpriv->lock); |
| 749 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | static int tegra_submit(struct drm_device *drm, void *data, |
| 753 | struct drm_file *file) |
| 754 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 755 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 756 | struct drm_tegra_submit *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 757 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 758 | int err; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 759 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 760 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 761 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 762 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 763 | if (!context) { |
| 764 | err = -ENODEV; |
| 765 | goto unlock; |
| 766 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 767 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 768 | err = context->client->ops->submit(context, args, drm, file); |
| 769 | |
| 770 | unlock: |
| 771 | mutex_unlock(&fpriv->lock); |
| 772 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 773 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 774 | |
| 775 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 776 | struct drm_file *file) |
| 777 | { |
| 778 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 779 | struct drm_tegra_get_syncpt_base *args = data; |
| 780 | struct tegra_drm_context *context; |
| 781 | struct host1x_syncpt_base *base; |
| 782 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 783 | int err = 0; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 784 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 785 | mutex_lock(&fpriv->lock); |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 786 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 787 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 788 | if (!context) { |
| 789 | err = -ENODEV; |
| 790 | goto unlock; |
| 791 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 792 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 793 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 794 | err = -EINVAL; |
| 795 | goto unlock; |
| 796 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 797 | |
| 798 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 799 | |
| 800 | base = host1x_syncpt_get_base(syncpt); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 801 | if (!base) { |
| 802 | err = -ENXIO; |
| 803 | goto unlock; |
| 804 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 805 | |
| 806 | args->id = host1x_syncpt_base_id(base); |
| 807 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 808 | unlock: |
| 809 | mutex_unlock(&fpriv->lock); |
| 810 | return err; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 811 | } |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 812 | |
| 813 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 814 | struct drm_file *file) |
| 815 | { |
| 816 | struct drm_tegra_gem_set_tiling *args = data; |
| 817 | enum tegra_bo_tiling_mode mode; |
| 818 | struct drm_gem_object *gem; |
| 819 | unsigned long value = 0; |
| 820 | struct tegra_bo *bo; |
| 821 | |
| 822 | switch (args->mode) { |
| 823 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 824 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 825 | |
| 826 | if (args->value != 0) |
| 827 | return -EINVAL; |
| 828 | |
| 829 | break; |
| 830 | |
| 831 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 832 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 833 | |
| 834 | if (args->value != 0) |
| 835 | return -EINVAL; |
| 836 | |
| 837 | break; |
| 838 | |
| 839 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 840 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 841 | |
| 842 | if (args->value > 5) |
| 843 | return -EINVAL; |
| 844 | |
| 845 | value = args->value; |
| 846 | break; |
| 847 | |
| 848 | default: |
| 849 | return -EINVAL; |
| 850 | } |
| 851 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 852 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 853 | if (!gem) |
| 854 | return -ENOENT; |
| 855 | |
| 856 | bo = to_tegra_bo(gem); |
| 857 | |
| 858 | bo->tiling.mode = mode; |
| 859 | bo->tiling.value = value; |
| 860 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 861 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 862 | |
| 863 | return 0; |
| 864 | } |
| 865 | |
| 866 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 867 | struct drm_file *file) |
| 868 | { |
| 869 | struct drm_tegra_gem_get_tiling *args = data; |
| 870 | struct drm_gem_object *gem; |
| 871 | struct tegra_bo *bo; |
| 872 | int err = 0; |
| 873 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 874 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 875 | if (!gem) |
| 876 | return -ENOENT; |
| 877 | |
| 878 | bo = to_tegra_bo(gem); |
| 879 | |
| 880 | switch (bo->tiling.mode) { |
| 881 | case TEGRA_BO_TILING_MODE_PITCH: |
| 882 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 883 | args->value = 0; |
| 884 | break; |
| 885 | |
| 886 | case TEGRA_BO_TILING_MODE_TILED: |
| 887 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 888 | args->value = 0; |
| 889 | break; |
| 890 | |
| 891 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 892 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 893 | args->value = bo->tiling.value; |
| 894 | break; |
| 895 | |
| 896 | default: |
| 897 | err = -EINVAL; |
| 898 | break; |
| 899 | } |
| 900 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 901 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 902 | |
| 903 | return err; |
| 904 | } |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 905 | |
| 906 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 907 | struct drm_file *file) |
| 908 | { |
| 909 | struct drm_tegra_gem_set_flags *args = data; |
| 910 | struct drm_gem_object *gem; |
| 911 | struct tegra_bo *bo; |
| 912 | |
| 913 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 914 | return -EINVAL; |
| 915 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 916 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 917 | if (!gem) |
| 918 | return -ENOENT; |
| 919 | |
| 920 | bo = to_tegra_bo(gem); |
| 921 | bo->flags = 0; |
| 922 | |
| 923 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 924 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 925 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 926 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 927 | |
| 928 | return 0; |
| 929 | } |
| 930 | |
| 931 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 932 | struct drm_file *file) |
| 933 | { |
| 934 | struct drm_tegra_gem_get_flags *args = data; |
| 935 | struct drm_gem_object *gem; |
| 936 | struct tegra_bo *bo; |
| 937 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 938 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 939 | if (!gem) |
| 940 | return -ENOENT; |
| 941 | |
| 942 | bo = to_tegra_bo(gem); |
| 943 | args->flags = 0; |
| 944 | |
| 945 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 946 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 947 | |
Cihangir Akturk | 7664b2f | 2017-08-11 15:33:07 +0300 | [diff] [blame^] | 948 | drm_gem_object_put_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 949 | |
| 950 | return 0; |
| 951 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 952 | #endif |
| 953 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 954 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 955 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Daniel Vetter | f8c4714 | 2015-09-08 13:56:30 +0200 | [diff] [blame] | 956 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), |
| 957 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), |
| 958 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), |
| 959 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), |
| 960 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), |
| 961 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), |
| 962 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), |
| 963 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), |
| 964 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), |
| 965 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), |
| 966 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), |
| 967 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), |
| 968 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), |
| 969 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 970 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 971 | }; |
| 972 | |
| 973 | static const struct file_operations tegra_drm_fops = { |
| 974 | .owner = THIS_MODULE, |
| 975 | .open = drm_open, |
| 976 | .release = drm_release, |
| 977 | .unlocked_ioctl = drm_ioctl, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 978 | .mmap = tegra_drm_mmap, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 979 | .poll = drm_poll, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 980 | .read = drm_read, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 981 | .compat_ioctl = drm_compat_ioctl, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 982 | .llseek = noop_llseek, |
| 983 | }; |
| 984 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 985 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 986 | { |
| 987 | struct tegra_drm_context *context = p; |
| 988 | |
| 989 | tegra_drm_context_free(context); |
| 990 | |
| 991 | return 0; |
| 992 | } |
| 993 | |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 994 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 995 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 996 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 997 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 998 | mutex_lock(&fpriv->lock); |
| 999 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 1000 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 1001 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 1002 | idr_destroy(&fpriv->contexts); |
| 1003 | mutex_destroy(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 1004 | kfree(fpriv); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1005 | } |
| 1006 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1007 | #ifdef CONFIG_DEBUG_FS |
| 1008 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 1009 | { |
| 1010 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1011 | struct drm_device *drm = node->minor->dev; |
| 1012 | struct drm_framebuffer *fb; |
| 1013 | |
| 1014 | mutex_lock(&drm->mode_config.fb_lock); |
| 1015 | |
| 1016 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 1017 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 1018 | fb->base.id, fb->width, fb->height, |
| 1019 | fb->format->depth, |
Ville Syrjälä | 272725c | 2016-12-14 23:32:20 +0200 | [diff] [blame] | 1020 | fb->format->cpp[0] * 8, |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 1021 | drm_framebuffer_read_refcount(fb)); |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | mutex_unlock(&drm->mode_config.fb_lock); |
| 1025 | |
| 1026 | return 0; |
| 1027 | } |
| 1028 | |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1029 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 1030 | { |
| 1031 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1032 | struct drm_device *drm = node->minor->dev; |
| 1033 | struct tegra_drm *tegra = drm->dev_private; |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1034 | struct drm_printer p = drm_seq_file_printer(s); |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1035 | |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 1036 | mutex_lock(&tegra->mm_lock); |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1037 | drm_mm_print(&tegra->mm, &p); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 1038 | mutex_unlock(&tegra->mm_lock); |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1039 | |
| 1040 | return 0; |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1041 | } |
| 1042 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1043 | static struct drm_info_list tegra_debugfs_list[] = { |
| 1044 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1045 | { "iova", tegra_debugfs_iova, 0 }, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1046 | }; |
| 1047 | |
| 1048 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1049 | { |
| 1050 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1051 | ARRAY_SIZE(tegra_debugfs_list), |
| 1052 | minor->debugfs_root, minor); |
| 1053 | } |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1054 | #endif |
| 1055 | |
Thierry Reding | 9b57f5f | 2013-11-08 13:17:14 +0100 | [diff] [blame] | 1056 | static struct drm_driver tegra_drm_driver = { |
Thierry Reding | ad90659 | 2015-09-24 18:38:09 +0200 | [diff] [blame] | 1057 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
| 1058 | DRIVER_ATOMIC, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1059 | .load = tegra_drm_load, |
| 1060 | .unload = tegra_drm_unload, |
| 1061 | .open = tegra_drm_open, |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 1062 | .postclose = tegra_drm_postclose, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1063 | .lastclose = tegra_drm_lastclose, |
| 1064 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1065 | #if defined(CONFIG_DEBUG_FS) |
| 1066 | .debugfs_init = tegra_debugfs_init, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1067 | #endif |
| 1068 | |
Daniel Vetter | 1ddbdbd | 2016-04-26 19:30:00 +0200 | [diff] [blame] | 1069 | .gem_free_object_unlocked = tegra_bo_free_object, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1070 | .gem_vm_ops = &tegra_bo_vm_ops, |
Thierry Reding | 3800391 | 2013-12-12 10:00:43 +0100 | [diff] [blame] | 1071 | |
| 1072 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1073 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1074 | .gem_prime_export = tegra_gem_prime_export, |
| 1075 | .gem_prime_import = tegra_gem_prime_import, |
| 1076 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1077 | .dumb_create = tegra_bo_dumb_create, |
| 1078 | .dumb_map_offset = tegra_bo_dumb_map_offset, |
Daniel Vetter | 43387b3 | 2013-07-16 09:12:04 +0200 | [diff] [blame] | 1079 | .dumb_destroy = drm_gem_dumb_destroy, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1080 | |
| 1081 | .ioctls = tegra_drm_ioctls, |
| 1082 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1083 | .fops = &tegra_drm_fops, |
| 1084 | |
| 1085 | .name = DRIVER_NAME, |
| 1086 | .desc = DRIVER_DESC, |
| 1087 | .date = DRIVER_DATE, |
| 1088 | .major = DRIVER_MAJOR, |
| 1089 | .minor = DRIVER_MINOR, |
| 1090 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1091 | }; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1092 | |
| 1093 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1094 | struct tegra_drm_client *client) |
| 1095 | { |
| 1096 | mutex_lock(&tegra->clients_lock); |
| 1097 | list_add_tail(&client->list, &tegra->clients); |
| 1098 | mutex_unlock(&tegra->clients_lock); |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
| 1103 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1104 | struct tegra_drm_client *client) |
| 1105 | { |
| 1106 | mutex_lock(&tegra->clients_lock); |
| 1107 | list_del_init(&client->list); |
| 1108 | mutex_unlock(&tegra->clients_lock); |
| 1109 | |
| 1110 | return 0; |
| 1111 | } |
| 1112 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 1113 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, |
| 1114 | dma_addr_t *dma) |
| 1115 | { |
| 1116 | struct iova *alloc; |
| 1117 | void *virt; |
| 1118 | gfp_t gfp; |
| 1119 | int err; |
| 1120 | |
| 1121 | if (tegra->domain) |
| 1122 | size = iova_align(&tegra->carveout.domain, size); |
| 1123 | else |
| 1124 | size = PAGE_ALIGN(size); |
| 1125 | |
| 1126 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1127 | if (!tegra->domain) { |
| 1128 | /* |
| 1129 | * Many units only support 32-bit addresses, even on 64-bit |
| 1130 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1131 | * virtual address space, force allocations to be in the |
| 1132 | * lower 32-bit range. |
| 1133 | */ |
| 1134 | gfp |= GFP_DMA; |
| 1135 | } |
| 1136 | |
| 1137 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1138 | if (!virt) |
| 1139 | return ERR_PTR(-ENOMEM); |
| 1140 | |
| 1141 | if (!tegra->domain) { |
| 1142 | /* |
| 1143 | * If IOMMU is disabled, devices address physical memory |
| 1144 | * directly. |
| 1145 | */ |
| 1146 | *dma = virt_to_phys(virt); |
| 1147 | return virt; |
| 1148 | } |
| 1149 | |
| 1150 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1151 | size >> tegra->carveout.shift, |
| 1152 | tegra->carveout.limit, true); |
| 1153 | if (!alloc) { |
| 1154 | err = -EBUSY; |
| 1155 | goto free_pages; |
| 1156 | } |
| 1157 | |
| 1158 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1159 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1160 | size, IOMMU_READ | IOMMU_WRITE); |
| 1161 | if (err < 0) |
| 1162 | goto free_iova; |
| 1163 | |
| 1164 | return virt; |
| 1165 | |
| 1166 | free_iova: |
| 1167 | __free_iova(&tegra->carveout.domain, alloc); |
| 1168 | free_pages: |
| 1169 | free_pages((unsigned long)virt, get_order(size)); |
| 1170 | |
| 1171 | return ERR_PTR(err); |
| 1172 | } |
| 1173 | |
| 1174 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1175 | dma_addr_t dma) |
| 1176 | { |
| 1177 | if (tegra->domain) |
| 1178 | size = iova_align(&tegra->carveout.domain, size); |
| 1179 | else |
| 1180 | size = PAGE_ALIGN(size); |
| 1181 | |
| 1182 | if (tegra->domain) { |
| 1183 | iommu_unmap(tegra->domain, dma, size); |
| 1184 | free_iova(&tegra->carveout.domain, |
| 1185 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1186 | } |
| 1187 | |
| 1188 | free_pages((unsigned long)virt, get_order(size)); |
| 1189 | } |
| 1190 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1191 | static int host1x_drm_probe(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1192 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1193 | struct drm_driver *driver = &tegra_drm_driver; |
| 1194 | struct drm_device *drm; |
| 1195 | int err; |
| 1196 | |
| 1197 | drm = drm_dev_alloc(driver, &dev->dev); |
Tom Gundersen | 0f28860 | 2016-09-21 16:59:19 +0200 | [diff] [blame] | 1198 | if (IS_ERR(drm)) |
| 1199 | return PTR_ERR(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1200 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1201 | dev_set_drvdata(&dev->dev, drm); |
| 1202 | |
| 1203 | err = drm_dev_register(drm, 0); |
| 1204 | if (err < 0) |
| 1205 | goto unref; |
| 1206 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1207 | return 0; |
| 1208 | |
| 1209 | unref: |
| 1210 | drm_dev_unref(drm); |
| 1211 | return err; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1212 | } |
| 1213 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1214 | static int host1x_drm_remove(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1215 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1216 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1217 | |
| 1218 | drm_dev_unregister(drm); |
| 1219 | drm_dev_unref(drm); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1220 | |
| 1221 | return 0; |
| 1222 | } |
| 1223 | |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1224 | #ifdef CONFIG_PM_SLEEP |
| 1225 | static int host1x_drm_suspend(struct device *dev) |
| 1226 | { |
| 1227 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1228 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1229 | |
| 1230 | drm_kms_helper_poll_disable(drm); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1231 | tegra_drm_fb_suspend(drm); |
| 1232 | |
| 1233 | tegra->state = drm_atomic_helper_suspend(drm); |
| 1234 | if (IS_ERR(tegra->state)) { |
| 1235 | tegra_drm_fb_resume(drm); |
| 1236 | drm_kms_helper_poll_enable(drm); |
| 1237 | return PTR_ERR(tegra->state); |
| 1238 | } |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1239 | |
| 1240 | return 0; |
| 1241 | } |
| 1242 | |
| 1243 | static int host1x_drm_resume(struct device *dev) |
| 1244 | { |
| 1245 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1246 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1247 | |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1248 | drm_atomic_helper_resume(drm, tegra->state); |
| 1249 | tegra_drm_fb_resume(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1250 | drm_kms_helper_poll_enable(drm); |
| 1251 | |
| 1252 | return 0; |
| 1253 | } |
| 1254 | #endif |
| 1255 | |
Thierry Reding | a13f1dc | 2015-08-11 13:22:44 +0200 | [diff] [blame] | 1256 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1257 | host1x_drm_resume); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1258 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1259 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1260 | { .compatible = "nvidia,tegra20-dc", }, |
| 1261 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1262 | { .compatible = "nvidia,tegra20-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1263 | { .compatible = "nvidia,tegra20-gr3d", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1264 | { .compatible = "nvidia,tegra30-dc", }, |
| 1265 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1266 | { .compatible = "nvidia,tegra30-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1267 | { .compatible = "nvidia,tegra30-gr3d", }, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1268 | { .compatible = "nvidia,tegra114-dsi", }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1269 | { .compatible = "nvidia,tegra114-hdmi", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1270 | { .compatible = "nvidia,tegra114-gr3d", }, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1271 | { .compatible = "nvidia,tegra124-dc", }, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1272 | { .compatible = "nvidia,tegra124-sor", }, |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1273 | { .compatible = "nvidia,tegra124-hdmi", }, |
Thierry Reding | 7d33858 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1274 | { .compatible = "nvidia,tegra124-dsi", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1275 | { .compatible = "nvidia,tegra124-vic", }, |
Thierry Reding | c06c793 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1276 | { .compatible = "nvidia,tegra132-dsi", }, |
Thierry Reding | 5b4f516 | 2015-03-27 10:31:58 +0100 | [diff] [blame] | 1277 | { .compatible = "nvidia,tegra210-dc", }, |
Thierry Reding | ddfb406 | 2015-04-08 16:56:22 +0200 | [diff] [blame] | 1278 | { .compatible = "nvidia,tegra210-dsi", }, |
Thierry Reding | 3309ac8 | 2015-07-30 10:32:46 +0200 | [diff] [blame] | 1279 | { .compatible = "nvidia,tegra210-sor", }, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1280 | { .compatible = "nvidia,tegra210-sor1", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1281 | { .compatible = "nvidia,tegra210-vic", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1282 | { /* sentinel */ } |
| 1283 | }; |
| 1284 | |
| 1285 | static struct host1x_driver host1x_drm_driver = { |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1286 | .driver = { |
| 1287 | .name = "drm", |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1288 | .pm = &host1x_drm_pm_ops, |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1289 | }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1290 | .probe = host1x_drm_probe, |
| 1291 | .remove = host1x_drm_remove, |
| 1292 | .subdevs = host1x_drm_subdevs, |
| 1293 | }; |
| 1294 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1295 | static struct platform_driver * const drivers[] = { |
| 1296 | &tegra_dc_driver, |
| 1297 | &tegra_hdmi_driver, |
| 1298 | &tegra_dsi_driver, |
| 1299 | &tegra_dpaux_driver, |
| 1300 | &tegra_sor_driver, |
| 1301 | &tegra_gr2d_driver, |
| 1302 | &tegra_gr3d_driver, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1303 | &tegra_vic_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1304 | }; |
| 1305 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1306 | static int __init host1x_drm_init(void) |
| 1307 | { |
| 1308 | int err; |
| 1309 | |
| 1310 | err = host1x_driver_register(&host1x_drm_driver); |
| 1311 | if (err < 0) |
| 1312 | return err; |
| 1313 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1314 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1315 | if (err < 0) |
| 1316 | goto unregister_host1x; |
| 1317 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1318 | return 0; |
| 1319 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1320 | unregister_host1x: |
| 1321 | host1x_driver_unregister(&host1x_drm_driver); |
| 1322 | return err; |
| 1323 | } |
| 1324 | module_init(host1x_drm_init); |
| 1325 | |
| 1326 | static void __exit host1x_drm_exit(void) |
| 1327 | { |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1328 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1329 | host1x_driver_unregister(&host1x_drm_driver); |
| 1330 | } |
| 1331 | module_exit(host1x_drm_exit); |
| 1332 | |
| 1333 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1334 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1335 | MODULE_LICENSE("GPL v2"); |