blob: ebb58959f4183e39ea1c8c6a99c61b77efcb78c1 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26 /*
27 * Modularization
28 */
29
30#include <linux/module.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031#include <linux/fb.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
33#include "drmP.h"
34#include "drm.h"
35#include "drm_crtc.h"
36#include "drm_crtc_helper.h"
37#include "radeon_drm.h"
38#include "radeon.h"
39
Dave Airlie785b93e2009-08-28 15:46:53 +100040#include "drm_fb_helper.h"
41
Jerome Glisse771fe6b2009-06-05 14:42:42 +020042struct radeon_fb_device {
Dave Airlie785b93e2009-08-28 15:46:53 +100043 struct drm_fb_helper helper;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020044 struct radeon_framebuffer *rfb;
Dave Airlie785b93e2009-08-28 15:46:53 +100045 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020046};
47
Dave Airlie785b93e2009-08-28 15:46:53 +100048static int radeon_fb_check_var(struct fb_var_screeninfo *var,
49 struct fb_info *info)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020050{
Jerome Glisse771fe6b2009-06-05 14:42:42 +020051 int ret;
Dave Airlie785b93e2009-08-28 15:46:53 +100052 ret = drm_fb_helper_check_var(var, info);
53 if (ret)
54 return ret;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020055
Dave Airlie785b93e2009-08-28 15:46:53 +100056 /* big endian override for radeon endian workaround */
57#ifdef __BIG_ENDIAN
58 {
59 int depth;
60 switch (var->bits_per_pixel) {
61 case 16:
62 depth = (var->green.length == 6) ? 16 : 15;
63 break;
64 case 32:
65 depth = (var->transp.length > 0) ? 32 : 24;
66 break;
67 default:
68 depth = var->bits_per_pixel;
69 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020070 }
Dave Airlie785b93e2009-08-28 15:46:53 +100071 switch (depth) {
72 case 8:
73 var->red.offset = 0;
74 var->green.offset = 0;
75 var->blue.offset = 0;
76 var->red.length = 8;
77 var->green.length = 8;
78 var->blue.length = 8;
79 var->transp.length = 0;
80 var->transp.offset = 0;
81 break;
82 case 24:
83 var->red.offset = 8;
84 var->green.offset = 16;
85 var->blue.offset = 24;
86 var->red.length = 8;
87 var->green.length = 8;
88 var->blue.length = 8;
89 var->transp.length = 0;
90 var->transp.offset = 0;
91 break;
92 case 32:
93 var->red.offset = 8;
94 var->green.offset = 16;
95 var->blue.offset = 24;
96 var->red.length = 8;
97 var->green.length = 8;
98 var->blue.length = 8;
99 var->transp.length = 8;
100 var->transp.offset = 0;
101 break;
102 default:
103 return -EINVAL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200104 }
105 }
Dave Airlie785b93e2009-08-28 15:46:53 +1000106#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200107 return 0;
108}
109
110static struct fb_ops radeonfb_ops = {
111 .owner = THIS_MODULE,
Dave Airlie785b93e2009-08-28 15:46:53 +1000112 .fb_check_var = radeon_fb_check_var,
113 .fb_set_par = drm_fb_helper_set_par,
114 .fb_setcolreg = drm_fb_helper_setcolreg,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200115 .fb_fillrect = cfb_fillrect,
116 .fb_copyarea = cfb_copyarea,
117 .fb_imageblit = cfb_imageblit,
Dave Airlie785b93e2009-08-28 15:46:53 +1000118 .fb_pan_display = drm_fb_helper_pan_display,
119 .fb_blank = drm_fb_helper_blank,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200120};
121
122/**
123 * Curretly it is assumed that the old framebuffer is reused.
124 *
125 * LOCKING
126 * caller should hold the mode config lock.
127 *
128 */
129int radeonfb_resize(struct drm_device *dev, struct drm_crtc *crtc)
130{
131 struct fb_info *info;
132 struct drm_framebuffer *fb;
133 struct drm_display_mode *mode = crtc->desired_mode;
134
135 fb = crtc->fb;
136 if (fb == NULL) {
137 return 1;
138 }
139 info = fb->fbdev;
140 if (info == NULL) {
141 return 1;
142 }
143 if (mode == NULL) {
144 return 1;
145 }
146 info->var.xres = mode->hdisplay;
147 info->var.right_margin = mode->hsync_start - mode->hdisplay;
148 info->var.hsync_len = mode->hsync_end - mode->hsync_start;
149 info->var.left_margin = mode->htotal - mode->hsync_end;
150 info->var.yres = mode->vdisplay;
151 info->var.lower_margin = mode->vsync_start - mode->vdisplay;
152 info->var.vsync_len = mode->vsync_end - mode->vsync_start;
153 info->var.upper_margin = mode->vtotal - mode->vsync_end;
154 info->var.pixclock = 10000000 / mode->htotal * 1000 / mode->vtotal * 100;
155 /* avoid overflow */
156 info->var.pixclock = info->var.pixclock * 1000 / mode->vrefresh;
157
158 return 0;
159}
160EXPORT_SYMBOL(radeonfb_resize);
161
Dave Airliee024e112009-06-24 09:48:08 +1000162static int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163{
164 int aligned = width;
Dave Airliee024e112009-06-24 09:48:08 +1000165 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200166 int pitch_mask = 0;
167
168 switch (bpp / 8) {
169 case 1:
170 pitch_mask = align_large ? 255 : 127;
171 break;
172 case 2:
173 pitch_mask = align_large ? 127 : 31;
174 break;
175 case 3:
176 case 4:
177 pitch_mask = align_large ? 63 : 15;
178 break;
179 }
180
181 aligned += pitch_mask;
182 aligned &= ~pitch_mask;
183 return aligned;
184}
185
Dave Airlie785b93e2009-08-28 15:46:53 +1000186static struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
187 .gamma_set = radeon_crtc_fb_gamma_set,
188};
189
190int radeonfb_create(struct drm_device *dev,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200191 uint32_t fb_width, uint32_t fb_height,
192 uint32_t surface_width, uint32_t surface_height,
Dave Airlie785b93e2009-08-28 15:46:53 +1000193 struct drm_framebuffer **fb_p)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194{
Dave Airlie785b93e2009-08-28 15:46:53 +1000195 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 struct fb_info *info;
197 struct radeon_fb_device *rfbdev;
Jerome Glissef92e93e2009-06-22 18:15:58 +0200198 struct drm_framebuffer *fb = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 struct radeon_framebuffer *rfb;
200 struct drm_mode_fb_cmd mode_cmd;
201 struct drm_gem_object *gobj = NULL;
202 struct radeon_object *robj = NULL;
203 struct device *device = &rdev->pdev->dev;
204 int size, aligned_size, ret;
Jerome Glissef92e93e2009-06-22 18:15:58 +0200205 u64 fb_gpuaddr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200206 void *fbptr = NULL;
Jerome Glissef92e93e2009-06-22 18:15:58 +0200207 unsigned long tmp;
Dave Airliee024e112009-06-24 09:48:08 +1000208 bool fb_tiled = false; /* useful for testing */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209
210 mode_cmd.width = surface_width;
211 mode_cmd.height = surface_height;
212 mode_cmd.bpp = 32;
213 /* need to align pitch with crtc limits */
Dave Airliee024e112009-06-24 09:48:08 +1000214 mode_cmd.pitch = radeon_align_pitch(rdev, mode_cmd.width, mode_cmd.bpp, fb_tiled) * ((mode_cmd.bpp + 1) / 8);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200215 mode_cmd.depth = 24;
216
217 size = mode_cmd.pitch * mode_cmd.height;
218 aligned_size = ALIGN(size, PAGE_SIZE);
219
220 ret = radeon_gem_object_create(rdev, aligned_size, 0,
Jerome Glissef92e93e2009-06-22 18:15:58 +0200221 RADEON_GEM_DOMAIN_VRAM,
222 false, ttm_bo_type_kernel,
223 false, &gobj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200224 if (ret) {
Jerome Glissef92e93e2009-06-22 18:15:58 +0200225 printk(KERN_ERR "failed to allocate framebuffer (%d %d)\n",
226 surface_width, surface_height);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227 ret = -ENOMEM;
228 goto out;
229 }
230 robj = gobj->driver_private;
231
Dave Airliee024e112009-06-24 09:48:08 +1000232 if (fb_tiled)
233 radeon_object_set_tiling_flags(robj, RADEON_TILING_MACRO|RADEON_TILING_SURFACE, mode_cmd.pitch);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234 mutex_lock(&rdev->ddev->struct_mutex);
235 fb = radeon_framebuffer_create(rdev->ddev, &mode_cmd, gobj);
236 if (fb == NULL) {
237 DRM_ERROR("failed to allocate fb.\n");
238 ret = -ENOMEM;
239 goto out_unref;
240 }
Jerome Glissef92e93e2009-06-22 18:15:58 +0200241 ret = radeon_object_pin(robj, RADEON_GEM_DOMAIN_VRAM, &fb_gpuaddr);
242 if (ret) {
243 printk(KERN_ERR "failed to pin framebuffer\n");
244 ret = -ENOMEM;
245 goto out_unref;
246 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200247
248 list_add(&fb->filp_head, &rdev->ddev->mode_config.fb_kernel_list);
249
Dave Airlie785b93e2009-08-28 15:46:53 +1000250 *fb_p = fb;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200251 rfb = to_radeon_framebuffer(fb);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200252 rdev->fbdev_rfb = rfb;
Jerome Glissef92e93e2009-06-22 18:15:58 +0200253 rdev->fbdev_robj = robj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254
255 info = framebuffer_alloc(sizeof(struct radeon_fb_device), device);
256 if (info == NULL) {
257 ret = -ENOMEM;
258 goto out_unref;
259 }
Dave Airlie785b93e2009-08-28 15:46:53 +1000260
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261 rfbdev = info->par;
Dave Airlie785b93e2009-08-28 15:46:53 +1000262 rfbdev->helper.funcs = &radeon_fb_helper_funcs;
263 rfbdev->helper.dev = dev;
264 ret = drm_fb_helper_init_crtc_count(&rfbdev->helper, 2,
265 RADEONFB_CONN_LIMIT);
266 if (ret)
267 goto out_unref;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200268
Dave Airliee024e112009-06-24 09:48:08 +1000269 if (fb_tiled)
270 radeon_object_check_tiling(robj, 0, 0);
271
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200272 ret = radeon_object_kmap(robj, &fbptr);
273 if (ret) {
274 goto out_unref;
275 }
276
Dave Airliebf8e8282009-08-17 10:20:47 +1000277 memset_io(fbptr, 0, aligned_size);
278
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200279 strcpy(info->fix.id, "radeondrmfb");
Dave Airlie785b93e2009-08-28 15:46:53 +1000280
281 drm_fb_helper_fill_fix(info, fb->pitch);
282
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200283 info->flags = FBINFO_DEFAULT;
284 info->fbops = &radeonfb_ops;
Dave Airlie785b93e2009-08-28 15:46:53 +1000285
Jerome Glissef92e93e2009-06-22 18:15:58 +0200286 tmp = fb_gpuaddr - rdev->mc.vram_location;
287 info->fix.smem_start = rdev->mc.aper_base + tmp;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200288 info->fix.smem_len = size;
289 info->screen_base = fbptr;
290 info->screen_size = size;
Dave Airlie785b93e2009-08-28 15:46:53 +1000291
292 drm_fb_helper_fill_var(info, fb, fb_width, fb_height);
Dave Airlieed8f0d92009-07-29 17:07:38 +1000293
294 /* setup aperture base/size for vesafb takeover */
295 info->aperture_base = rdev->ddev->mode_config.fb_base;
296 info->aperture_size = rdev->mc.real_vram_size;
297
Michel Dänzer696d4df2009-06-23 16:12:53 +0200298 info->fix.mmio_start = 0;
299 info->fix.mmio_len = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200300 info->pixmap.size = 64*1024;
301 info->pixmap.buf_align = 8;
302 info->pixmap.access_align = 32;
303 info->pixmap.flags = FB_PIXMAP_SYSTEM;
304 info->pixmap.scan_align = 1;
305 if (info->screen_base == NULL) {
306 ret = -ENOSPC;
307 goto out_unref;
308 }
309 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
310 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
311 DRM_INFO("size %lu\n", (unsigned long)size);
312 DRM_INFO("fb depth is %d\n", fb->depth);
313 DRM_INFO(" pitch is %d\n", fb->pitch);
314
Dave Airlie785b93e2009-08-28 15:46:53 +1000315#ifdef __BIG_ENDIAN
316 /* fill var sets defaults for this stuff - override
317 on big endian */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200318 switch (fb->depth) {
319 case 8:
320 info->var.red.offset = 0;
321 info->var.green.offset = 0;
322 info->var.blue.offset = 0;
323 info->var.red.length = 8; /* 8bit DAC */
324 info->var.green.length = 8;
325 info->var.blue.length = 8;
326 info->var.transp.offset = 0;
327 info->var.transp.length = 0;
328 break;
Michel Dänzer61b576d2009-06-24 00:12:55 +1000329 case 24:
330 info->var.red.offset = 8;
331 info->var.green.offset = 16;
332 info->var.blue.offset = 24;
333 info->var.red.length = 8;
334 info->var.green.length = 8;
335 info->var.blue.length = 8;
336 info->var.transp.offset = 0;
337 info->var.transp.length = 0;
338 break;
339 case 32:
340 info->var.red.offset = 8;
341 info->var.green.offset = 16;
342 info->var.blue.offset = 24;
343 info->var.red.length = 8;
344 info->var.green.length = 8;
345 info->var.blue.length = 8;
346 info->var.transp.offset = 0;
347 info->var.transp.length = 8;
348 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200349 default:
350 break;
351 }
Dave Airlie785b93e2009-08-28 15:46:53 +1000352#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200353
354 fb->fbdev = info;
355 rfbdev->rfb = rfb;
356 rfbdev->rdev = rdev;
357
358 mutex_unlock(&rdev->ddev->struct_mutex);
359 return 0;
360
361out_unref:
362 if (robj) {
363 radeon_object_kunmap(robj);
364 }
Jerome Glissef92e93e2009-06-22 18:15:58 +0200365 if (fb && ret) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200366 list_del(&fb->filp_head);
367 drm_gem_object_unreference(gobj);
368 drm_framebuffer_cleanup(fb);
369 kfree(fb);
370 }
371 drm_gem_object_unreference(gobj);
372 mutex_unlock(&rdev->ddev->struct_mutex);
373out:
374 return ret;
375}
376
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200377int radeonfb_probe(struct drm_device *dev)
378{
379 int ret;
Dave Airlie785b93e2009-08-28 15:46:53 +1000380 ret = drm_fb_helper_single_fb_probe(dev, &radeonfb_create);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200381 return ret;
382}
383EXPORT_SYMBOL(radeonfb_probe);
384
385int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb)
386{
387 struct fb_info *info;
388 struct radeon_framebuffer *rfb = to_radeon_framebuffer(fb);
389 struct radeon_object *robj;
390
391 if (!fb) {
392 return -EINVAL;
393 }
394 info = fb->fbdev;
395 if (info) {
Dave Airlie785b93e2009-08-28 15:46:53 +1000396 struct radeon_fb_device *rfbdev = info->par;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200397 robj = rfb->obj->driver_private;
398 unregister_framebuffer(info);
399 radeon_object_kunmap(robj);
Jerome Glissef92e93e2009-06-22 18:15:58 +0200400 radeon_object_unpin(robj);
Dave Airlie785b93e2009-08-28 15:46:53 +1000401 drm_fb_helper_free(&rfbdev->helper);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200402 framebuffer_release(info);
403 }
404
405 printk(KERN_INFO "unregistered panic notifier\n");
Dave Airlie785b93e2009-08-28 15:46:53 +1000406
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200407 return 0;
408}
409EXPORT_SYMBOL(radeonfb_remove);
410MODULE_LICENSE("GPL");