Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Sascha Hauer | b5f3294 | 2009-09-22 16:46:02 -0700 | [diff] [blame] | 2 | |
| 3 | #ifndef __MACH_SPI_H_ |
| 4 | #define __MACH_SPI_H_ |
| 5 | |
| 6 | /* |
| 7 | * struct spi_imx_master - device.platform_data for SPI controller devices. |
Trent Piepho | fe1bd78 | 2018-04-02 13:06:05 -0700 | [diff] [blame] | 8 | * @chipselect: Array of chipselects for this master or NULL. Numbers >= 0 |
| 9 | * mean GPIO pins, -ENOENT means internal CSPI chipselect |
| 10 | * matching the position in the array. E.g., if chipselect[1] = |
| 11 | * -ENOENT then a SPI slave using chip select 1 will use the |
| 12 | * native SS1 line of the CSPI. Omitting the array will use |
| 13 | * all native chip selects. |
| 14 | |
| 15 | * Normally you want to use gpio based chip selects as the CSPI |
| 16 | * module tries to be intelligent about when to assert the |
| 17 | * chipselect: The CSPI module deasserts the chipselect once it |
| 18 | * runs out of input data. The other problem is that it is not |
| 19 | * possible to mix between high active and low active chipselects |
| 20 | * on one single bus using the internal chipselects. |
| 21 | * Unfortunately, on some SoCs, Freescale decided to put some |
Sascha Hauer | b5f3294 | 2009-09-22 16:46:02 -0700 | [diff] [blame] | 22 | * chipselects on dedicated pins which are not usable as gpios, |
| 23 | * so we have to support the internal chipselects. |
Trent Piepho | fe1bd78 | 2018-04-02 13:06:05 -0700 | [diff] [blame] | 24 | * |
| 25 | * @num_chipselect: If @chipselect is specified, ARRAY_SIZE(chipselect), |
| 26 | * otherwise the number of native chip selects. |
Sascha Hauer | b5f3294 | 2009-09-22 16:46:02 -0700 | [diff] [blame] | 27 | */ |
| 28 | struct spi_imx_master { |
| 29 | int *chipselect; |
| 30 | int num_chipselect; |
| 31 | }; |
| 32 | |
Sascha Hauer | b5f3294 | 2009-09-22 16:46:02 -0700 | [diff] [blame] | 33 | #endif /* __MACH_SPI_H_*/ |