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gerrit-public.fairphone.software / kernel / msm-5.4 / 7e3e68bcfd7713fb1470070c8fa0f108609dd76b / . / drivers / media / dvb-frontends / cxd2841er.c
blob: 900186ba8e6201d428e22f1627fb7faa3bce7d7f [file] [log] [blame]
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1/*
2 * cxd2841er.c
3 *
4 * Sony CXD2441ER digital demodulator driver
5 *
6 * Copyright 2012 Sony Corporation
7 * Copyright (C) 2014 NetUP Inc.
8 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
9 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/string.h>
25#include <linux/slab.h>
26#include <linux/bitops.h>
27#include <linux/math64.h>
28#include <linux/log2.h>
29#include <linux/dynamic_debug.h>
30
31#include "dvb_math.h"
32#include "dvb_frontend.h"
33#include "cxd2841er.h"
34#include "cxd2841er_priv.h"
35
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]36#define MAX_WRITE_REGSIZE 16
37
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]38enum cxd2841er_state {
39 STATE_SHUTDOWN = 0,
40 STATE_SLEEP_S,
41 STATE_ACTIVE_S,
42 STATE_SLEEP_TC,
43 STATE_ACTIVE_TC
44};
45
46struct cxd2841er_priv {
47 struct dvb_frontend frontend;
48 struct i2c_adapter *i2c;
49 u8 i2c_addr_slvx;
50 u8 i2c_addr_slvt;
51 const struct cxd2841er_config *config;
52 enum cxd2841er_state state;
53 u8 system;
54};
55
56static const struct cxd2841er_cnr_data s_cn_data[] = {
57 { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
58 { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
59 { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
60 { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
61 { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
62 { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
63 { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
64 { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
65 { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
66 { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
67 { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
68 { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
69 { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
70 { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
71 { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
72 { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
73 { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
74 { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
75 { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
76 { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
77 { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
78 { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
79 { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
80 { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
81 { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
82 { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
83 { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
84 { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
85 { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
86 { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
87 { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
88 { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
89 { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
90 { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
91 { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
92 { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
93 { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
94 { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
95 { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
96 { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
97 { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
98 { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
99 { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
100 { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
101 { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
102 { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
103 { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
104 { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
105 { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
106 { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
107 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
108 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
109 { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
110 { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
111 { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
112 { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
113 { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
114 { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
115 { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
116 { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
117 { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
118 { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
119 { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
120 { 0x0015, 19900 }, { 0x0014, 20000 },
121};
122
123static const struct cxd2841er_cnr_data s2_cn_data[] = {
124 { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
125 { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
126 { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
127 { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
128 { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
129 { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
130 { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
131 { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
132 { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
133 { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
134 { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
135 { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
136 { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
137 { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
138 { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
139 { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
140 { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
141 { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
142 { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
143 { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
144 { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
145 { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
146 { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
147 { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
148 { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
149 { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
150 { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
151 { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
152 { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
153 { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
154 { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
155 { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
156 { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
157 { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
158 { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
159 { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
160 { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
161 { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
162 { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
163 { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
164 { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
165 { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
166 { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
167 { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
168 { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
169 { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
170 { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
171 { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
172 { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
173 { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
174 { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
175 { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
176 { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
177 { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
178 { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
179 { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
180 { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
181 { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
182 { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
183 { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
184 { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
185 { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
186 { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
187 { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
188};
189
190#define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
191
192static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
193 u8 addr, u8 reg, u8 write,
194 const u8 *data, u32 len)
195{
196 dev_dbg(&priv->i2c->dev,
197 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
198 (write == 0 ? "read" : "write"), addr, reg, len);
199 print_hex_dump_bytes("cxd2841er: I2C data: ",
200 DUMP_PREFIX_OFFSET, data, len);
201}
202
203static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
204 u8 addr, u8 reg, const u8 *data, u32 len)
205{
206 int ret;
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]207 u8 buf[MAX_WRITE_REGSIZE + 1];
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]208 u8 i2c_addr = (addr == I2C_SLVX ?
209 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
210 struct i2c_msg msg[1] = {
211 {
212 .addr = i2c_addr,
213 .flags = 0,
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]214 .len = len + 1,
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]215 .buf = buf,
216 }
217 };
218
Mauro Carvalho Chehabd13a7b62015-08-11 15:22:36 -0300[diff] [blame]219 if (len + 1 >= sizeof(buf)) {
220 dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
221 reg, len + 1);
222 return -E2BIG;
223 }
224
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]225 cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
226 buf[0] = reg;
227 memcpy(&buf[1], data, len);
228
229 ret = i2c_transfer(priv->i2c, msg, 1);
230 if (ret >= 0 && ret != 1)
231 ret = -EIO;
232 if (ret < 0) {
233 dev_warn(&priv->i2c->dev,
234 "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
235 KBUILD_MODNAME, ret, i2c_addr, reg, len);
236 return ret;
237 }
238 return 0;
239}
240
241static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
242 u8 addr, u8 reg, u8 val)
243{
244 return cxd2841er_write_regs(priv, addr, reg, &val, 1);
245}
246
247static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
248 u8 addr, u8 reg, u8 *val, u32 len)
249{
250 int ret;
251 u8 i2c_addr = (addr == I2C_SLVX ?
252 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
253 struct i2c_msg msg[2] = {
254 {
255 .addr = i2c_addr,
256 .flags = 0,
257 .len = 1,
258 .buf = &reg,
259 }, {
260 .addr = i2c_addr,
261 .flags = I2C_M_RD,
262 .len = len,
263 .buf = val,
264 }
265 };
266
267 ret = i2c_transfer(priv->i2c, &msg[0], 1);
268 if (ret >= 0 && ret != 1)
269 ret = -EIO;
270 if (ret < 0) {
271 dev_warn(&priv->i2c->dev,
272 "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
273 KBUILD_MODNAME, ret, i2c_addr, reg);
274 return ret;
275 }
276 ret = i2c_transfer(priv->i2c, &msg[1], 1);
277 if (ret >= 0 && ret != 1)
278 ret = -EIO;
279 if (ret < 0) {
280 dev_warn(&priv->i2c->dev,
281 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
282 KBUILD_MODNAME, ret, i2c_addr, reg);
283 return ret;
284 }
285 return 0;
286}
287
288static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
289 u8 addr, u8 reg, u8 *val)
290{
291 return cxd2841er_read_regs(priv, addr, reg, val, 1);
292}
293
294static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
295 u8 addr, u8 reg, u8 data, u8 mask)
296{
297 int res;
298 u8 rdata;
299
300 if (mask != 0xff) {
301 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
302 if (res)
303 return res;
304 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
305 }
306 return cxd2841er_write_reg(priv, addr, reg, data);
307}
308
309static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
310 u32 symbol_rate)
311{
312 u32 reg_value = 0;
313 u8 data[3] = {0, 0, 0};
314
315 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
316 /*
317 * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
318 * = ((symbolRateKSps * 2^14) + 500) / 1000
319 * = ((symbolRateKSps * 16384) + 500) / 1000
320 */
321 reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
322 if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
323 dev_err(&priv->i2c->dev,
324 "%s(): reg_value is out of range\n", __func__);
325 return -EINVAL;
326 }
327 data[0] = (u8)((reg_value >> 16) & 0x0F);
328 data[1] = (u8)((reg_value >> 8) & 0xFF);
329 data[2] = (u8)(reg_value & 0xFF);
330 /* Set SLV-T Bank : 0xAE */
331 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
332 cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
333 return 0;
334}
335
336static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
337 u8 system);
338
339static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
340 u8 system, u32 symbol_rate)
341{
342 int ret;
343 u8 data[4] = { 0, 0, 0, 0 };
344
345 if (priv->state != STATE_SLEEP_S) {
346 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
347 __func__, (int)priv->state);
348 return -EINVAL;
349 }
350 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
351 cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
352 /* Set demod mode */
353 if (system == SYS_DVBS) {
354 data[0] = 0x0A;
355 } else if (system == SYS_DVBS2) {
356 data[0] = 0x0B;
357 } else {
358 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
359 __func__, system);
360 return -EINVAL;
361 }
362 /* Set SLV-X Bank : 0x00 */
363 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
364 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
365 /* DVB-S/S2 */
366 data[0] = 0x00;
367 /* Set SLV-T Bank : 0x00 */
368 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
369 /* Enable S/S2 auto detection 1 */
370 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
371 /* Set SLV-T Bank : 0xAE */
372 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
373 /* Enable S/S2 auto detection 2 */
374 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
375 /* Set SLV-T Bank : 0x00 */
376 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
377 /* Enable demod clock */
378 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
379 /* Enable ADC clock */
380 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
381 /* Enable ADC 1 */
382 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
383 /* Enable ADC 2 */
384 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
385 /* Set SLV-X Bank : 0x00 */
386 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
387 /* Enable ADC 3 */
388 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
389 /* Set SLV-T Bank : 0xA3 */
390 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
391 cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
392 data[0] = 0x07;
393 data[1] = 0x3B;
394 data[2] = 0x08;
395 data[3] = 0xC5;
396 /* Set SLV-T Bank : 0xAB */
397 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
398 cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
399 data[0] = 0x05;
400 data[1] = 0x80;
401 data[2] = 0x0A;
402 data[3] = 0x80;
403 cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
404 data[0] = 0x0C;
405 data[1] = 0xCC;
406 cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
407 /* Set demod parameter */
408 ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
409 if (ret != 0)
410 return ret;
411 /* Set SLV-T Bank : 0x00 */
412 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
413 /* disable Hi-Z setting 1 */
414 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
415 /* disable Hi-Z setting 2 */
416 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
417 priv->state = STATE_ACTIVE_S;
418 return 0;
419}
420
421static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
422 u32 bandwidth);
423
424static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
425 u32 bandwidth);
426
427static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
428 u32 bandwidth);
429
430static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
431 struct dtv_frontend_properties *p)
432{
433 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
434 if (priv->state != STATE_ACTIVE_S &&
435 priv->state != STATE_ACTIVE_TC) {
436 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
437 __func__, priv->state);
438 return -EINVAL;
439 }
440 /* Set SLV-T Bank : 0x00 */
441 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
442 /* disable TS output */
443 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
444 if (priv->state == STATE_ACTIVE_S)
445 return cxd2841er_dvbs2_set_symbol_rate(
446 priv, p->symbol_rate / 1000);
447 else if (priv->state == STATE_ACTIVE_TC) {
448 switch (priv->system) {
449 case SYS_DVBT:
450 return cxd2841er_sleep_tc_to_active_t_band(
451 priv, p->bandwidth_hz);
452 case SYS_DVBT2:
453 return cxd2841er_sleep_tc_to_active_t2_band(
454 priv, p->bandwidth_hz);
455 case SYS_DVBC_ANNEX_A:
456 return cxd2841er_sleep_tc_to_active_c_band(
457 priv, 8000000);
458 }
459 }
460 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
461 __func__, priv->system);
462 return -EINVAL;
463}
464
465static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
466{
467 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
468 if (priv->state != STATE_ACTIVE_S) {
469 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
470 __func__, priv->state);
471 return -EINVAL;
472 }
473 /* Set SLV-T Bank : 0x00 */
474 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
475 /* disable TS output */
476 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
477 /* enable Hi-Z setting 1 */
478 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
479 /* enable Hi-Z setting 2 */
480 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
481 /* Set SLV-X Bank : 0x00 */
482 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
483 /* disable ADC 1 */
484 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
485 /* Set SLV-T Bank : 0x00 */
486 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
487 /* disable ADC clock */
488 cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
489 /* disable ADC 2 */
490 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
491 /* disable ADC 3 */
492 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
493 /* SADC Bias ON */
494 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
495 /* disable demod clock */
496 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
497 /* Set SLV-T Bank : 0xAE */
498 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
499 /* disable S/S2 auto detection1 */
500 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
501 /* Set SLV-T Bank : 0x00 */
502 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
503 /* disable S/S2 auto detection2 */
504 cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
505 priv->state = STATE_SLEEP_S;
506 return 0;
507}
508
509static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
510{
511 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
512 if (priv->state != STATE_SLEEP_S) {
513 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
514 __func__, priv->state);
515 return -EINVAL;
516 }
517 /* Set SLV-T Bank : 0x00 */
518 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
519 /* Disable DSQOUT */
520 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
521 /* Disable DSQIN */
522 cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
523 /* Set SLV-X Bank : 0x00 */
524 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
525 /* Disable oscillator */
526 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
527 /* Set demod mode */
528 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
529 priv->state = STATE_SHUTDOWN;
530 return 0;
531}
532
533static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
534{
535 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
536 if (priv->state != STATE_SLEEP_TC) {
537 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
538 __func__, priv->state);
539 return -EINVAL;
540 }
541 /* Set SLV-X Bank : 0x00 */
542 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
543 /* Disable oscillator */
544 cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
545 /* Set demod mode */
546 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
547 priv->state = STATE_SHUTDOWN;
548 return 0;
549}
550
551static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
552{
553 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
554 if (priv->state != STATE_ACTIVE_TC) {
555 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
556 __func__, priv->state);
557 return -EINVAL;
558 }
559 /* Set SLV-T Bank : 0x00 */
560 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
561 /* disable TS output */
562 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
563 /* enable Hi-Z setting 1 */
564 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
565 /* enable Hi-Z setting 2 */
566 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
567 /* Set SLV-X Bank : 0x00 */
568 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
569 /* disable ADC 1 */
570 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
571 /* Set SLV-T Bank : 0x00 */
572 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
573 /* Disable ADC 2 */
574 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
575 /* Disable ADC 3 */
576 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
577 /* Disable ADC clock */
578 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
579 /* Disable RF level monitor */
580 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
581 /* Disable demod clock */
582 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
583 priv->state = STATE_SLEEP_TC;
584 return 0;
585}
586
587static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
588{
589 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
590 if (priv->state != STATE_ACTIVE_TC) {
591 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
592 __func__, priv->state);
593 return -EINVAL;
594 }
595 /* Set SLV-T Bank : 0x00 */
596 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
597 /* disable TS output */
598 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
599 /* enable Hi-Z setting 1 */
600 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
601 /* enable Hi-Z setting 2 */
602 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
603 /* Cancel DVB-T2 setting */
604 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
605 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
606 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
607 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
608 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
609 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
610 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
611 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
612 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
613 /* Set SLV-X Bank : 0x00 */
614 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
615 /* disable ADC 1 */
616 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
617 /* Set SLV-T Bank : 0x00 */
618 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
619 /* Disable ADC 2 */
620 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
621 /* Disable ADC 3 */
622 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
623 /* Disable ADC clock */
624 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
625 /* Disable RF level monitor */
626 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
627 /* Disable demod clock */
628 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
629 priv->state = STATE_SLEEP_TC;
630 return 0;
631}
632
633static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
634{
635 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
636 if (priv->state != STATE_ACTIVE_TC) {
637 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
638 __func__, priv->state);
639 return -EINVAL;
640 }
641 /* Set SLV-T Bank : 0x00 */
642 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
643 /* disable TS output */
644 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
645 /* enable Hi-Z setting 1 */
646 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
647 /* enable Hi-Z setting 2 */
648 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
649 /* Cancel DVB-C setting */
650 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
651 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
652 /* Set SLV-X Bank : 0x00 */
653 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
654 /* disable ADC 1 */
655 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
656 /* Set SLV-T Bank : 0x00 */
657 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
658 /* Disable ADC 2 */
659 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
660 /* Disable ADC 3 */
661 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
662 /* Disable ADC clock */
663 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
664 /* Disable RF level monitor */
665 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
666 /* Disable demod clock */
667 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
668 priv->state = STATE_SLEEP_TC;
669 return 0;
670}
671
672static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
673{
674 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
675 if (priv->state != STATE_SHUTDOWN) {
676 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
677 __func__, priv->state);
678 return -EINVAL;
679 }
680 /* Set SLV-X Bank : 0x00 */
681 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
682 /* Clear all demodulator registers */
683 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
684 usleep_range(3000, 5000);
685 /* Set SLV-X Bank : 0x00 */
686 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
687 /* Set demod SW reset */
688 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
689 /* Set X'tal clock to 20.5Mhz */
690 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
691 /* Set demod mode */
692 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
693 /* Clear demod SW reset */
694 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
695 usleep_range(1000, 2000);
696 /* Set SLV-T Bank : 0x00 */
697 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
698 /* enable DSQOUT */
699 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
700 /* enable DSQIN */
701 cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
702 /* TADC Bias On */
703 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
704 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
705 /* SADC Bias On */
706 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
707 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
708 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
709 priv->state = STATE_SLEEP_S;
710 return 0;
711}
712
713static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
714{
715 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
716 if (priv->state != STATE_SHUTDOWN) {
717 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
718 __func__, priv->state);
719 return -EINVAL;
720 }
721 /* Set SLV-X Bank : 0x00 */
722 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
723 /* Clear all demodulator registers */
724 cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
725 usleep_range(3000, 5000);
726 /* Set SLV-X Bank : 0x00 */
727 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
728 /* Set demod SW reset */
729 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
730 /* Set X'tal clock to 20.5Mhz */
731 cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
732 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
733 /* Clear demod SW reset */
734 cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
735 usleep_range(1000, 2000);
736 /* Set SLV-T Bank : 0x00 */
737 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
738 /* TADC Bias On */
739 cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
740 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
741 /* SADC Bias On */
742 cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
743 cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
744 cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
745 priv->state = STATE_SLEEP_TC;
746 return 0;
747}
748
749static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
750{
751 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
752 /* Set SLV-T Bank : 0x00 */
753 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
754 /* SW Reset */
755 cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
756 /* Enable TS output */
757 cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
758 return 0;
759}
760
761/* Set TS parallel mode */
762static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
763 u8 system)
764{
765 u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
766
767 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
768 /* Set SLV-T Bank : 0x00 */
769 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
770 cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
771 cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
772 cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
773 dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
774 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
775
776 /*
777 * slave Bank Addr Bit default Name
778 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD
779 */
780 cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
781 /*
782 * Disable TS IF Clock
783 * slave Bank Addr Bit default Name
784 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
785 */
786 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
787 /*
788 * slave Bank Addr Bit default Name
789 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF
790 */
791 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
792 /*
793 * Enable TS IF Clock
794 * slave Bank Addr Bit default Name
795 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN
796 */
797 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
798
799 if (system == SYS_DVBT) {
800 /* Enable parity period for DVB-T */
801 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
802 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
803 } else if (system == SYS_DVBC_ANNEX_A) {
804 /* Enable parity period for DVB-C */
805 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
806 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
807 }
808}
809
810static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
811{
812 u8 chip_id;
813
814 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
815 cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
816 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
817 return chip_id;
818}
819
820static int cxd2841er_read_status_s(struct dvb_frontend *fe,
821 enum fe_status *status)
822{
823 u8 reg = 0;
824 struct cxd2841er_priv *priv = fe->demodulator_priv;
825
826 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
827 *status = 0;
828 if (priv->state != STATE_ACTIVE_S) {
829 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
830 __func__, priv->state);
831 return -EINVAL;
832 }
833 /* Set SLV-T Bank : 0xA0 */
834 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
835 /*
836 * slave Bank Addr Bit Signal name
837 * <SLV-T> A0h 11h [2] ITSLOCK
838 */
839 cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
840 if (reg & 0x04) {
841 *status = FE_HAS_SIGNAL
842 | FE_HAS_CARRIER
843 | FE_HAS_VITERBI
844 | FE_HAS_SYNC
845 | FE_HAS_LOCK;
846 }
847 dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
848 return 0;
849}
850
851static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
852 u8 *sync, u8 *tslock, u8 *unlock)
853{
854 u8 data = 0;
855
856 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
857 if (priv->state != STATE_ACTIVE_TC)
858 return -EINVAL;
859 if (priv->system == SYS_DVBT) {
860 /* Set SLV-T Bank : 0x10 */
861 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
862 } else {
863 /* Set SLV-T Bank : 0x20 */
864 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
865 }
866 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
867 if ((data & 0x07) == 0x07) {
868 dev_dbg(&priv->i2c->dev,
869 "%s(): invalid hardware state detected\n", __func__);
870 *sync = 0;
871 *tslock = 0;
872 *unlock = 0;
873 } else {
874 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
875 *tslock = ((data & 0x20) ? 1 : 0);
876 *unlock = ((data & 0x10) ? 1 : 0);
877 }
878 return 0;
879}
880
881static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
882{
883 u8 data;
884
885 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
886 if (priv->state != STATE_ACTIVE_TC)
887 return -EINVAL;
888 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
889 cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
890 if ((data & 0x01) == 0) {
891 *tslock = 0;
892 } else {
893 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
894 *tslock = ((data & 0x20) ? 1 : 0);
895 }
896 return 0;
897}
898
899static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
900 enum fe_status *status)
901{
902 int ret = 0;
903 u8 sync = 0;
904 u8 tslock = 0;
905 u8 unlock = 0;
906 struct cxd2841er_priv *priv = fe->demodulator_priv;
907
908 *status = 0;
909 if (priv->state == STATE_ACTIVE_TC) {
910 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
911 ret = cxd2841er_read_status_t_t2(
912 priv, &sync, &tslock, &unlock);
913 if (ret)
914 goto done;
915 if (unlock)
916 goto done;
917 if (sync)
918 *status = FE_HAS_SIGNAL |
919 FE_HAS_CARRIER |
920 FE_HAS_VITERBI |
921 FE_HAS_SYNC;
922 if (tslock)
923 *status |= FE_HAS_LOCK;
924 } else if (priv->system == SYS_DVBC_ANNEX_A) {
925 ret = cxd2841er_read_status_c(priv, &tslock);
926 if (ret)
927 goto done;
928 if (tslock)
929 *status = FE_HAS_SIGNAL |
930 FE_HAS_CARRIER |
931 FE_HAS_VITERBI |
932 FE_HAS_SYNC |
933 FE_HAS_LOCK;
934 }
935 }
936done:
937 dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
938 return ret;
939}
940
941static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
942 int *offset)
943{
944 u8 data[3];
945 u8 is_hs_mode;
946 s32 cfrl_ctrlval;
947 s32 temp_div, temp_q, temp_r;
948
949 if (priv->state != STATE_ACTIVE_S) {
950 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
951 __func__, priv->state);
952 return -EINVAL;
953 }
954 /*
955 * Get High Sampling Rate mode
956 * slave Bank Addr Bit Signal name
957 * <SLV-T> A0h 10h [0] ITRL_LOCK
958 */
959 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
960 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
961 if (data[0] & 0x01) {
962 /*
963 * slave Bank Addr Bit Signal name
964 * <SLV-T> A0h 50h [4] IHSMODE
965 */
966 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
967 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
968 } else {
969 dev_dbg(&priv->i2c->dev,
970 "%s(): unable to detect sampling rate mode\n",
971 __func__);
972 return -EINVAL;
973 }
974 /*
975 * slave Bank Addr Bit Signal name
976 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16]
977 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8]
978 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0]
979 */
980 cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
981 cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
982 (((u32)data[1] & 0xFF) << 8) |
983 ((u32)data[2] & 0xFF), 20);
984 temp_div = (is_hs_mode ? 1048576 : 1572864);
985 if (cfrl_ctrlval > 0) {
986 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
987 temp_div, &temp_r);
988 } else {
989 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
990 temp_div, &temp_r);
991 }
992 if (temp_r >= temp_div / 2)
993 temp_q++;
994 if (cfrl_ctrlval > 0)
995 temp_q *= -1;
996 *offset = temp_q;
997 return 0;
998}
999
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1000static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1001 u32 bandwidth, int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1002{
1003 u8 data[4];
1004
1005 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1006 if (priv->state != STATE_ACTIVE_TC) {
1007 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1008 __func__, priv->state);
1009 return -EINVAL;
1010 }
1011 if (priv->system != SYS_DVBT2) {
1012 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1013 __func__, priv->system);
1014 return -EINVAL;
1015 }
1016 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1017 cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1018 *offset = -1 * sign_extend32(
1019 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1020 ((u32)data[2] << 8) | (u32)data[3], 27);
1021 switch (bandwidth) {
1022 case 1712000:
1023 *offset /= 582;
1024 break;
1025 case 5000000:
1026 case 6000000:
1027 case 7000000:
1028 case 8000000:
1029 *offset *= (bandwidth / 1000000);
1030 *offset /= 940;
1031 break;
1032 default:
1033 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1034 __func__, bandwidth);
1035 return -EINVAL;
1036 }
1037 return 0;
1038}
1039
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1040static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1041 int *offset)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1042{
1043 u8 data[2];
1044
1045 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1046 if (priv->state != STATE_ACTIVE_TC) {
1047 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1048 __func__, priv->state);
1049 return -EINVAL;
1050 }
1051 if (priv->system != SYS_DVBC_ANNEX_A) {
1052 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1053 __func__, priv->system);
1054 return -EINVAL;
1055 }
1056 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1057 cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1058 *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1059 | (u32)data[1], 13), 16384);
1060 return 0;
1061}
1062
1063static int cxd2841er_read_packet_errors_t(
1064 struct cxd2841er_priv *priv, u32 *penum)
1065{
1066 u8 data[3];
1067
1068 *penum = 0;
1069 if (priv->state != STATE_ACTIVE_TC) {
1070 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1071 __func__, priv->state);
1072 return -EINVAL;
1073 }
1074 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1075 cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1076 if (data[2] & 0x01)
1077 *penum = ((u32)data[0] << 8) | (u32)data[1];
1078 return 0;
1079}
1080
1081static int cxd2841er_read_packet_errors_t2(
1082 struct cxd2841er_priv *priv, u32 *penum)
1083{
1084 u8 data[3];
1085
1086 *penum = 0;
1087 if (priv->state != STATE_ACTIVE_TC) {
1088 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1089 __func__, priv->state);
1090 return -EINVAL;
1091 }
1092 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1093 cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1094 if (data[0] & 0x01)
1095 *penum = ((u32)data[1] << 8) | (u32)data[2];
1096 return 0;
1097}
1098
1099static u32 cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv)
1100{
1101 u8 data[11];
1102 u32 bit_error, bit_count;
1103 u32 temp_q, temp_r;
1104
1105 /* Set SLV-T Bank : 0xA0 */
1106 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1107 /*
1108 * slave Bank Addr Bit Signal name
1109 * <SLV-T> A0h 35h [0] IFVBER_VALID
1110 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16]
1111 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8]
1112 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0]
1113 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16]
1114 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8]
1115 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0]
1116 */
1117 cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1118 if (data[0] & 0x01) {
1119 bit_error = ((u32)(data[1] & 0x3F) << 16) |
1120 ((u32)(data[2] & 0xFF) << 8) |
1121 (u32)(data[3] & 0xFF);
1122 bit_count = ((u32)(data[8] & 0x3F) << 16) |
1123 ((u32)(data[9] & 0xFF) << 8) |
1124 (u32)(data[10] & 0xFF);
1125 /*
1126 * BER = bitError / bitCount
1127 * = (bitError * 10^7) / bitCount
1128 * = ((bitError * 625 * 125 * 128) / bitCount
1129 */
1130 if ((bit_count == 0) || (bit_error > bit_count)) {
1131 dev_dbg(&priv->i2c->dev,
1132 "%s(): invalid bit_error %d, bit_count %d\n",
1133 __func__, bit_error, bit_count);
1134 return 0;
1135 }
1136 temp_q = div_u64_rem(10000000ULL * bit_error,
1137 bit_count, &temp_r);
1138 if (bit_count != 1 && temp_r >= bit_count / 2)
1139 temp_q++;
1140 return temp_q;
1141 }
1142 dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1143 return 0;
1144}
1145
1146
1147static u32 cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv)
1148{
1149 u8 data[5];
1150 u32 bit_error, period;
1151 u32 temp_q, temp_r;
1152 u32 result = 0;
1153
1154 /* Set SLV-T Bank : 0xB2 */
1155 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1156 /*
1157 * slave Bank Addr Bit Signal name
1158 * <SLV-T> B2h 30h [0] IFLBER_VALID
1159 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24]
1160 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16]
1161 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8]
1162 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0]
1163 */
1164 cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1165 if (data[0] & 0x01) {
1166 /* Bit error count */
1167 bit_error = ((u32)(data[1] & 0x0F) << 24) |
1168 ((u32)(data[2] & 0xFF) << 16) |
1169 ((u32)(data[3] & 0xFF) << 8) |
1170 (u32)(data[4] & 0xFF);
1171
1172 /* Set SLV-T Bank : 0xA0 */
1173 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1174 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1175 /* Measurement period */
1176 period = (u32)(1 << (data[0] & 0x0F));
1177 if (period == 0) {
1178 dev_dbg(&priv->i2c->dev,
1179 "%s(): period is 0\n", __func__);
1180 return 0;
1181 }
1182 if (bit_error > (period * 64800)) {
1183 dev_dbg(&priv->i2c->dev,
1184 "%s(): invalid bit_err 0x%x period 0x%x\n",
1185 __func__, bit_error, period);
1186 return 0;
1187 }
1188 /*
1189 * BER = bitError / (period * 64800)
1190 * = (bitError * 10^7) / (period * 64800)
1191 * = (bitError * 10^5) / (period * 648)
1192 * = (bitError * 12500) / (period * 81)
1193 * = (bitError * 10) * 1250 / (period * 81)
1194 */
1195 temp_q = div_u64_rem(12500ULL * bit_error,
1196 period * 81, &temp_r);
1197 if (temp_r >= period * 40)
1198 temp_q++;
1199 result = temp_q;
1200 } else {
1201 dev_dbg(&priv->i2c->dev,
1202 "%s(): no data available\n", __func__);
1203 }
1204 return result;
1205}
1206
1207static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv, u32 *ber)
1208{
1209 u8 data[4];
1210 u32 div, q, r;
1211 u32 bit_err, period_exp, n_ldpc;
1212
1213 *ber = 0;
1214 if (priv->state != STATE_ACTIVE_TC) {
1215 dev_dbg(&priv->i2c->dev,
1216 "%s(): invalid state %d\n", __func__, priv->state);
1217 return -EINVAL;
1218 }
1219 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1220 cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1221 if (!(data[0] & 0x10)) {
1222 dev_dbg(&priv->i2c->dev,
1223 "%s(): no valid BER data\n", __func__);
1224 return 0;
1225 }
1226 bit_err = ((u32)(data[0] & 0x0f) << 24) |
1227 ((u32)data[1] << 16) |
1228 ((u32)data[2] << 8) |
1229 (u32)data[3];
1230 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1231 period_exp = data[0] & 0x0f;
1232 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1233 cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1234 n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1235 if (bit_err > ((1U << period_exp) * n_ldpc)) {
1236 dev_dbg(&priv->i2c->dev,
1237 "%s(): invalid BER value\n", __func__);
1238 return -EINVAL;
1239 }
1240 if (period_exp >= 4) {
1241 div = (1U << (period_exp - 4)) * (n_ldpc / 200);
1242 q = div_u64_rem(3125ULL * bit_err, div, &r);
1243 } else {
1244 div = (1U << period_exp) * (n_ldpc / 200);
1245 q = div_u64_rem(50000ULL * bit_err, div, &r);
1246 }
1247 *ber = (r >= div / 2) ? q + 1 : q;
1248 return 0;
1249}
1250
1251static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv, u32 *ber)
1252{
1253 u8 data[2];
1254 u32 div, q, r;
1255 u32 bit_err, period;
1256
1257 *ber = 0;
1258 if (priv->state != STATE_ACTIVE_TC) {
1259 dev_dbg(&priv->i2c->dev,
1260 "%s(): invalid state %d\n", __func__, priv->state);
1261 return -EINVAL;
1262 }
1263 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1264 cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1265 if (!(data[0] & 0x01)) {
1266 dev_dbg(&priv->i2c->dev,
1267 "%s(): no valid BER data\n", __func__);
1268 return 0;
1269 }
1270 cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1271 bit_err = ((u32)data[0] << 8) | (u32)data[1];
1272 cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1273 period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1274 div = period / 128;
1275 q = div_u64_rem(78125ULL * bit_err, div, &r);
1276 *ber = (r >= div / 2) ? q + 1 : q;
1277 return 0;
1278}
1279
1280static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv, u8 delsys)
1281{
1282 u8 data[3];
1283 u32 res = 0, value;
1284 int min_index, max_index, index;
1285 static const struct cxd2841er_cnr_data *cn_data;
1286
1287 /* Set SLV-T Bank : 0xA1 */
1288 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1289 /*
1290 * slave Bank Addr Bit Signal name
1291 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY
1292 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8]
1293 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0]
1294 */
1295 cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1296 if (data[0] & 0x01) {
1297 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1298 min_index = 0;
1299 if (delsys == SYS_DVBS) {
1300 cn_data = s_cn_data;
1301 max_index = sizeof(s_cn_data) /
1302 sizeof(s_cn_data[0]) - 1;
1303 } else {
1304 cn_data = s2_cn_data;
1305 max_index = sizeof(s2_cn_data) /
1306 sizeof(s2_cn_data[0]) - 1;
1307 }
1308 if (value >= cn_data[min_index].value) {
1309 res = cn_data[min_index].cnr_x1000;
1310 goto done;
1311 }
1312 if (value <= cn_data[max_index].value) {
1313 res = cn_data[max_index].cnr_x1000;
1314 goto done;
1315 }
1316 while ((max_index - min_index) > 1) {
1317 index = (max_index + min_index) / 2;
1318 if (value == cn_data[index].value) {
1319 res = cn_data[index].cnr_x1000;
1320 goto done;
1321 } else if (value > cn_data[index].value)
1322 max_index = index;
1323 else
1324 min_index = index;
1325 if ((max_index - min_index) <= 1) {
1326 if (value == cn_data[max_index].value) {
1327 res = cn_data[max_index].cnr_x1000;
1328 goto done;
1329 } else {
1330 res = cn_data[min_index].cnr_x1000;
1331 goto done;
1332 }
1333 }
1334 }
1335 } else {
1336 dev_dbg(&priv->i2c->dev,
1337 "%s(): no data available\n", __func__);
1338 }
1339done:
1340 return res;
1341}
1342
1343static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1344{
1345 u32 reg;
1346 u8 data[2];
1347
1348 *snr = 0;
1349 if (priv->state != STATE_ACTIVE_TC) {
1350 dev_dbg(&priv->i2c->dev,
1351 "%s(): invalid state %d\n", __func__, priv->state);
1352 return -EINVAL;
1353 }
1354 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1355 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1356 reg = ((u32)data[0] << 8) | (u32)data[1];
1357 if (reg == 0) {
1358 dev_dbg(&priv->i2c->dev,
1359 "%s(): reg value out of range\n", __func__);
1360 return 0;
1361 }
1362 if (reg > 4996)
1363 reg = 4996;
1364 *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1365 return 0;
1366}
1367
Mauro Carvalho Chehabc8946c82015-08-11 15:08:47 -0300[diff] [blame]1368static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]1369{
1370 u32 reg;
1371 u8 data[2];
1372
1373 *snr = 0;
1374 if (priv->state != STATE_ACTIVE_TC) {
1375 dev_dbg(&priv->i2c->dev,
1376 "%s(): invalid state %d\n", __func__, priv->state);
1377 return -EINVAL;
1378 }
1379 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1380 cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1381 reg = ((u32)data[0] << 8) | (u32)data[1];
1382 if (reg == 0) {
1383 dev_dbg(&priv->i2c->dev,
1384 "%s(): reg value out of range\n", __func__);
1385 return 0;
1386 }
1387 if (reg > 10876)
1388 reg = 10876;
1389 *snr = 10000 * ((intlog10(reg) -
1390 intlog10(12600 - reg)) >> 24) + 32000;
1391 return 0;
1392}
1393
1394static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1395 u8 delsys)
1396{
1397 u8 data[2];
1398
1399 cxd2841er_write_reg(
1400 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1401 cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1402 return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1403}
1404
1405static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1406{
1407 u8 data[2];
1408
1409 /* Set SLV-T Bank : 0xA0 */
1410 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1411 /*
1412 * slave Bank Addr Bit Signal name
1413 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8]
1414 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0]
1415 */
1416 cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1417 return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1418}
1419
1420static int cxd2841er_read_ber(struct dvb_frontend *fe, u32 *ber)
1421{
1422 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1423 struct cxd2841er_priv *priv = fe->demodulator_priv;
1424
1425 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1426 *ber = 0;
1427 switch (p->delivery_system) {
1428 case SYS_DVBS:
1429 *ber = cxd2841er_mon_read_ber_s(priv);
1430 break;
1431 case SYS_DVBS2:
1432 *ber = cxd2841er_mon_read_ber_s2(priv);
1433 break;
1434 case SYS_DVBT:
1435 return cxd2841er_read_ber_t(priv, ber);
1436 case SYS_DVBT2:
1437 return cxd2841er_read_ber_t2(priv, ber);
1438 default:
1439 *ber = 0;
1440 break;
1441 }
1442 return 0;
1443}
1444
1445static int cxd2841er_read_signal_strength(struct dvb_frontend *fe,
1446 u16 *strength)
1447{
1448 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1449 struct cxd2841er_priv *priv = fe->demodulator_priv;
1450
1451 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1452 switch (p->delivery_system) {
1453 case SYS_DVBT:
1454 case SYS_DVBT2:
1455 *strength = 65535 - cxd2841er_read_agc_gain_t_t2(
1456 priv, p->delivery_system);
1457 break;
1458 case SYS_DVBS:
1459 case SYS_DVBS2:
1460 *strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1461 break;
1462 default:
1463 *strength = 0;
1464 break;
1465 }
1466 return 0;
1467}
1468
1469static int cxd2841er_read_snr(struct dvb_frontend *fe, u16 *snr)
1470{
1471 u32 tmp = 0;
1472 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1473 struct cxd2841er_priv *priv = fe->demodulator_priv;
1474
1475 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1476 switch (p->delivery_system) {
1477 case SYS_DVBT:
1478 cxd2841er_read_snr_t(priv, &tmp);
1479 break;
1480 case SYS_DVBT2:
1481 cxd2841er_read_snr_t2(priv, &tmp);
1482 break;
1483 case SYS_DVBS:
1484 case SYS_DVBS2:
1485 tmp = cxd2841er_dvbs_read_snr(priv, p->delivery_system);
1486 break;
1487 default:
1488 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
1489 __func__, p->delivery_system);
1490 break;
1491 }
1492 *snr = tmp & 0xffff;
1493 return 0;
1494}
1495
1496static int cxd2841er_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
1497{
1498 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1499 struct cxd2841er_priv *priv = fe->demodulator_priv;
1500
1501 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1502 switch (p->delivery_system) {
1503 case SYS_DVBT:
1504 cxd2841er_read_packet_errors_t(priv, ucblocks);
1505 break;
1506 case SYS_DVBT2:
1507 cxd2841er_read_packet_errors_t2(priv, ucblocks);
1508 break;
1509 default:
1510 *ucblocks = 0;
1511 break;
1512 }
1513 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1514 return 0;
1515}
1516
1517static int cxd2841er_dvbt2_set_profile(
1518 struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
1519{
1520 u8 tune_mode;
1521 u8 seq_not2d_time;
1522
1523 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1524 switch (profile) {
1525 case DVBT2_PROFILE_BASE:
1526 tune_mode = 0x01;
1527 seq_not2d_time = 12;
1528 break;
1529 case DVBT2_PROFILE_LITE:
1530 tune_mode = 0x05;
1531 seq_not2d_time = 40;
1532 break;
1533 case DVBT2_PROFILE_ANY:
1534 tune_mode = 0x00;
1535 seq_not2d_time = 40;
1536 break;
1537 default:
1538 return -EINVAL;
1539 }
1540 /* Set SLV-T Bank : 0x2E */
1541 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
1542 /* Set profile and tune mode */
1543 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
1544 /* Set SLV-T Bank : 0x2B */
1545 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
1546 /* Set early unlock detection time */
1547 cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
1548 return 0;
1549}
1550
1551static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
1552 u8 is_auto, u8 plp_id)
1553{
1554 if (is_auto) {
1555 dev_dbg(&priv->i2c->dev,
1556 "%s() using auto PLP selection\n", __func__);
1557 } else {
1558 dev_dbg(&priv->i2c->dev,
1559 "%s() using manual PLP selection, ID %d\n",
1560 __func__, plp_id);
1561 }
1562 /* Set SLV-T Bank : 0x23 */
1563 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
1564 if (!is_auto) {
1565 /* Manual PLP selection mode. Set the data PLP Id. */
1566 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
1567 }
1568 /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
1569 cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
1570 return 0;
1571}
1572
1573static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
1574 u32 bandwidth)
1575{
1576 u32 iffreq;
1577 u8 b20_9f[5];
1578 u8 b10_a6[14];
1579 u8 b10_b6[3];
1580 u8 b10_d7;
1581
1582 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1583 switch (bandwidth) {
1584 case 8000000:
1585 /* bank 0x20, reg 0x9f */
1586 b20_9f[0] = 0x11;
1587 b20_9f[1] = 0xf0;
1588 b20_9f[2] = 0x00;
1589 b20_9f[3] = 0x00;
1590 b20_9f[4] = 0x00;
1591 /* bank 0x10, reg 0xa6 */
1592 b10_a6[0] = 0x26;
1593 b10_a6[1] = 0xaf;
1594 b10_a6[2] = 0x06;
1595 b10_a6[3] = 0xcd;
1596 b10_a6[4] = 0x13;
1597 b10_a6[5] = 0xbb;
1598 b10_a6[6] = 0x28;
1599 b10_a6[7] = 0xba;
1600 b10_a6[8] = 0x23;
1601 b10_a6[9] = 0xa9;
1602 b10_a6[10] = 0x1f;
1603 b10_a6[11] = 0xa8;
1604 b10_a6[12] = 0x2c;
1605 b10_a6[13] = 0xc8;
1606 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1607 b10_d7 = 0x00;
1608 break;
1609 case 7000000:
1610 /* bank 0x20, reg 0x9f */
1611 b20_9f[0] = 0x14;
1612 b20_9f[1] = 0x80;
1613 b20_9f[2] = 0x00;
1614 b20_9f[3] = 0x00;
1615 b20_9f[4] = 0x00;
1616 /* bank 0x10, reg 0xa6 */
1617 b10_a6[0] = 0x2C;
1618 b10_a6[1] = 0xBD;
1619 b10_a6[2] = 0x02;
1620 b10_a6[3] = 0xCF;
1621 b10_a6[4] = 0x04;
1622 b10_a6[5] = 0xF8;
1623 b10_a6[6] = 0x23;
1624 b10_a6[7] = 0xA6;
1625 b10_a6[8] = 0x29;
1626 b10_a6[9] = 0xB0;
1627 b10_a6[10] = 0x26;
1628 b10_a6[11] = 0xA9;
1629 b10_a6[12] = 0x21;
1630 b10_a6[13] = 0xA5;
1631 iffreq = MAKE_IFFREQ_CONFIG(4.2);
1632 b10_d7 = 0x02;
1633 break;
1634 case 6000000:
1635 /* bank 0x20, reg 0x9f */
1636 b20_9f[0] = 0x17;
1637 b20_9f[1] = 0xEA;
1638 b20_9f[2] = 0xAA;
1639 b20_9f[3] = 0xAA;
1640 b20_9f[4] = 0xAA;
1641 /* bank 0x10, reg 0xa6 */
1642 b10_a6[0] = 0x27;
1643 b10_a6[1] = 0xA7;
1644 b10_a6[2] = 0x28;
1645 b10_a6[3] = 0xB3;
1646 b10_a6[4] = 0x02;
1647 b10_a6[5] = 0xF0;
1648 b10_a6[6] = 0x01;
1649 b10_a6[7] = 0xE8;
1650 b10_a6[8] = 0x00;
1651 b10_a6[9] = 0xCF;
1652 b10_a6[10] = 0x00;
1653 b10_a6[11] = 0xE6;
1654 b10_a6[12] = 0x23;
1655 b10_a6[13] = 0xA4;
1656 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1657 b10_d7 = 0x04;
1658 break;
1659 case 5000000:
1660 /* bank 0x20, reg 0x9f */
1661 b20_9f[0] = 0x1C;
1662 b20_9f[1] = 0xB3;
1663 b20_9f[2] = 0x33;
1664 b20_9f[3] = 0x33;
1665 b20_9f[4] = 0x33;
1666 /* bank 0x10, reg 0xa6 */
1667 b10_a6[0] = 0x27;
1668 b10_a6[1] = 0xA7;
1669 b10_a6[2] = 0x28;
1670 b10_a6[3] = 0xB3;
1671 b10_a6[4] = 0x02;
1672 b10_a6[5] = 0xF0;
1673 b10_a6[6] = 0x01;
1674 b10_a6[7] = 0xE8;
1675 b10_a6[8] = 0x00;
1676 b10_a6[9] = 0xCF;
1677 b10_a6[10] = 0x00;
1678 b10_a6[11] = 0xE6;
1679 b10_a6[12] = 0x23;
1680 b10_a6[13] = 0xA4;
1681 iffreq = MAKE_IFFREQ_CONFIG(3.6);
1682 b10_d7 = 0x06;
1683 break;
1684 case 1712000:
1685 /* bank 0x20, reg 0x9f */
1686 b20_9f[0] = 0x58;
1687 b20_9f[1] = 0xE2;
1688 b20_9f[2] = 0xAF;
1689 b20_9f[3] = 0xE0;
1690 b20_9f[4] = 0xBC;
1691 /* bank 0x10, reg 0xa6 */
1692 b10_a6[0] = 0x25;
1693 b10_a6[1] = 0xA0;
1694 b10_a6[2] = 0x36;
1695 b10_a6[3] = 0x8D;
1696 b10_a6[4] = 0x2E;
1697 b10_a6[5] = 0x94;
1698 b10_a6[6] = 0x28;
1699 b10_a6[7] = 0x9B;
1700 b10_a6[8] = 0x32;
1701 b10_a6[9] = 0x90;
1702 b10_a6[10] = 0x2C;
1703 b10_a6[11] = 0x9D;
1704 b10_a6[12] = 0x29;
1705 b10_a6[13] = 0x99;
1706 iffreq = MAKE_IFFREQ_CONFIG(3.5);
1707 b10_d7 = 0x03;
1708 break;
1709 default:
1710 return -EINVAL;
1711 }
1712 /* Set SLV-T Bank : 0x20 */
1713 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x20);
1714 cxd2841er_write_regs(priv, I2C_SLVT, 0x9f, b20_9f, sizeof(b20_9f));
1715 /* Set SLV-T Bank : 0x27 */
1716 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
1717 cxd2841er_set_reg_bits(
1718 priv, I2C_SLVT, 0x7a,
1719 (bandwidth == 1712000 ? 0x03 : 0x00), 0x0f);
1720 /* Set SLV-T Bank : 0x10 */
1721 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1722 /* Group delay equaliser sett. for ASCOT2E */
1723 cxd2841er_write_regs(priv, I2C_SLVT, 0xa6, b10_a6, sizeof(b10_a6));
1724 /* <IF freq setting> */
1725 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1726 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1727 b10_b6[2] = (u8)(iffreq & 0xff);
1728 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1729 /* System bandwidth setting */
1730 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, b10_d7, 0x07);
1731 return 0;
1732}
1733
1734static int cxd2841er_sleep_tc_to_active_t_band(
1735 struct cxd2841er_priv *priv, u32 bandwidth)
1736{
1737 u8 b13_9c[2] = { 0x01, 0x14 };
1738 u8 bw8mhz_b10_9f[] = { 0x11, 0xF0, 0x00, 0x00, 0x00 };
1739 u8 bw8mhz_b10_a6[] = { 0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB,
1740 0x28, 0xBA, 0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8 };
1741 u8 bw8mhz_b10_d9[] = { 0x01, 0xE0 };
1742 u8 bw8mhz_b17_38[] = { 0x01, 0x02 };
1743 u8 bw7mhz_b10_9f[] = { 0x14, 0x80, 0x00, 0x00, 0x00 };
1744 u8 bw7mhz_b10_a6[] = { 0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8,
1745 0x23, 0xA6, 0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5 };
1746 u8 bw7mhz_b10_d9[] = { 0x12, 0xF8 };
1747 u8 bw7mhz_b17_38[] = { 0x00, 0x03 };
1748 u8 bw6mhz_b10_9f[] = { 0x17, 0xEA, 0xAA, 0xAA, 0xAA };
1749 u8 bw6mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1750 0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1751 u8 bw6mhz_b10_d9[] = { 0x1F, 0xDC };
1752 u8 bw6mhz_b17_38[] = { 0x00, 0x03 };
1753 u8 bw5mhz_b10_9f[] = { 0x1C, 0xB3, 0x33, 0x33, 0x33 };
1754 u8 bw5mhz_b10_a6[] = { 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0,
1755 0x01, 0xE8, 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1756 u8 bw5mhz_b10_d9[] = { 0x26, 0x3C };
1757 u8 bw5mhz_b17_38[] = { 0x00, 0x03 };
1758 u8 b10_b6[3];
1759 u8 d7val;
1760 u32 iffreq;
1761 u8 *b10_9f;
1762 u8 *b10_a6;
1763 u8 *b10_d9;
1764 u8 *b17_38;
1765
1766 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1767 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
1768 /* Echo performance optimization setting */
1769 cxd2841er_write_regs(priv, I2C_SLVT, 0x9c, b13_9c, sizeof(b13_9c));
1770 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1771
1772 switch (bandwidth) {
1773 case 8000000:
1774 b10_9f = bw8mhz_b10_9f;
1775 b10_a6 = bw8mhz_b10_a6;
1776 b10_d9 = bw8mhz_b10_d9;
1777 b17_38 = bw8mhz_b17_38;
1778 d7val = 0;
1779 iffreq = MAKE_IFFREQ_CONFIG(4.80);
1780 break;
1781 case 7000000:
1782 b10_9f = bw7mhz_b10_9f;
1783 b10_a6 = bw7mhz_b10_a6;
1784 b10_d9 = bw7mhz_b10_d9;
1785 b17_38 = bw7mhz_b17_38;
1786 d7val = 2;
1787 iffreq = MAKE_IFFREQ_CONFIG(4.20);
1788 break;
1789 case 6000000:
1790 b10_9f = bw6mhz_b10_9f;
1791 b10_a6 = bw6mhz_b10_a6;
1792 b10_d9 = bw6mhz_b10_d9;
1793 b17_38 = bw6mhz_b17_38;
1794 d7val = 4;
1795 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1796 break;
1797 case 5000000:
1798 b10_9f = bw5mhz_b10_9f;
1799 b10_a6 = bw5mhz_b10_a6;
1800 b10_d9 = bw5mhz_b10_d9;
1801 b17_38 = bw5mhz_b17_38;
1802 d7val = 6;
1803 iffreq = MAKE_IFFREQ_CONFIG(3.60);
1804 break;
1805 default:
1806 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1807 __func__, bandwidth);
1808 return -EINVAL;
1809 }
1810 /* <IF freq setting> */
1811 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1812 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1813 b10_b6[2] = (u8)(iffreq & 0xff);
1814 cxd2841er_write_regs(
1815 priv, I2C_SLVT, 0x9f, b10_9f, sizeof(bw8mhz_b10_9f));
1816 cxd2841er_write_regs(
1817 priv, I2C_SLVT, 0xa6, b10_a6, sizeof(bw8mhz_b10_a6));
1818 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1819 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, d7val, 0x7);
1820 cxd2841er_write_regs(
1821 priv, I2C_SLVT, 0xd9, b10_d9, sizeof(bw8mhz_b10_d9));
1822 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
1823 cxd2841er_write_regs(
1824 priv, I2C_SLVT, 0x38, b17_38, sizeof(bw8mhz_b17_38));
1825 return 0;
1826}
1827
1828static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
1829 u32 bandwidth)
1830{
1831 u8 bw7_8mhz_b10_a6[] = {
1832 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
1833 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
1834 u8 bw6mhz_b10_a6[] = {
1835 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
1836 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
1837 u8 b10_b6[3];
1838 u32 iffreq;
1839
1840 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1841 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1842 switch (bandwidth) {
1843 case 8000000:
1844 case 7000000:
1845 cxd2841er_write_regs(
1846 priv, I2C_SLVT, 0xa6,
1847 bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
1848 iffreq = MAKE_IFFREQ_CONFIG(4.9);
1849 break;
1850 case 6000000:
1851 cxd2841er_write_regs(
1852 priv, I2C_SLVT, 0xa6,
1853 bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
1854 iffreq = MAKE_IFFREQ_CONFIG(3.7);
1855 break;
1856 default:
1857 dev_dbg(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
1858 __func__, bandwidth);
1859 return -EINVAL;
1860 }
1861 /* <IF freq setting> */
1862 b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
1863 b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
1864 b10_b6[2] = (u8)(iffreq & 0xff);
1865 cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
1866 /* Set SLV-T Bank : 0x11 */
1867 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1868 switch (bandwidth) {
1869 case 8000000:
1870 case 7000000:
1871 cxd2841er_set_reg_bits(
1872 priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
1873 break;
1874 case 6000000:
1875 cxd2841er_set_reg_bits(
1876 priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
1877 break;
1878 }
1879 /* Set SLV-T Bank : 0x40 */
1880 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1881 switch (bandwidth) {
1882 case 8000000:
1883 cxd2841er_set_reg_bits(
1884 priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
1885 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x3e);
1886 break;
1887 case 7000000:
1888 cxd2841er_set_reg_bits(
1889 priv, I2C_SLVT, 0x26, 0x09, 0x0f);
1890 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0xd6);
1891 break;
1892 case 6000000:
1893 cxd2841er_set_reg_bits(
1894 priv, I2C_SLVT, 0x26, 0x08, 0x0f);
1895 cxd2841er_write_reg(priv, I2C_SLVT, 0x27, 0x6e);
1896 break;
1897 }
1898 return 0;
1899}
1900
1901static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
1902 u32 bandwidth)
1903{
1904 u8 data[2] = { 0x09, 0x54 };
1905
1906 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1907 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
1908 /* Set SLV-X Bank : 0x00 */
1909 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1910 /* Set demod mode */
1911 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
1912 /* Set SLV-T Bank : 0x00 */
1913 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1914 /* Enable demod clock */
1915 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1916 /* Disable RF level monitor */
1917 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1918 /* Enable ADC clock */
1919 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1920 /* Enable ADC 1 */
1921 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1922 /* xtal freq 20.5MHz */
1923 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1924 /* Enable ADC 4 */
1925 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1926 /* Set SLV-T Bank : 0x10 */
1927 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1928 /* IFAGC gain settings */
1929 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1930 /* Set SLV-T Bank : 0x11 */
1931 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1932 /* BBAGC TARGET level setting */
1933 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1934 /* Set SLV-T Bank : 0x10 */
1935 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1936 /* ASCOT setting ON */
1937 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
1938 /* Set SLV-T Bank : 0x18 */
1939 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
1940 /* Pre-RS BER moniter setting */
1941 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
1942 /* FEC Auto Recovery setting */
1943 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
1944 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
1945 /* Set SLV-T Bank : 0x00 */
1946 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1947 /* TSIF setting */
1948 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
1949 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
1950 cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
1951 /* Set SLV-T Bank : 0x00 */
1952 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1953 /* Disable HiZ Setting 1 */
1954 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
1955 /* Disable HiZ Setting 2 */
1956 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
1957 priv->state = STATE_ACTIVE_TC;
1958 return 0;
1959}
1960
1961static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
1962 u32 bandwidth)
1963{
1964 u8 data[2] = { 0x09, 0x54 };
1965
1966 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1967 cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
1968 /* Set SLV-X Bank : 0x00 */
1969 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
1970 /* Set demod mode */
1971 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
1972 /* Set SLV-T Bank : 0x00 */
1973 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
1974 /* Enable demod clock */
1975 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
1976 /* Disable RF level monitor */
1977 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
1978 /* Enable ADC clock */
1979 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
1980 /* Enable ADC 1 */
1981 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
1982 /* xtal freq 20.5MHz */
1983 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
1984 /* Enable ADC 4 */
1985 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
1986 /* Set SLV-T Bank : 0x10 */
1987 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1988 /* IFAGC gain settings */
1989 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
1990 /* Set SLV-T Bank : 0x11 */
1991 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
1992 /* BBAGC TARGET level setting */
1993 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
1994 /* Set SLV-T Bank : 0x10 */
1995 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1996 /* ASCOT setting ON */
1997 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
1998 /* Set SLV-T Bank : 0x20 */
1999 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2000 /* Acquisition optimization setting */
2001 cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2002 /* Set SLV-T Bank : 0x2b */
2003 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2004 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2005 /* Set SLV-T Bank : 0x00 */
2006 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2007 /* TSIF setting */
2008 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2009 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2010 /* DVB-T2 initial setting */
2011 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2012 cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2013 cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2014 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2015 cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2016 /* Set SLV-T Bank : 0x2a */
2017 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2018 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2019 /* Set SLV-T Bank : 0x2b */
2020 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2021 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2022
2023 cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
2024
2025 /* Set SLV-T Bank : 0x00 */
2026 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2027 /* Disable HiZ Setting 1 */
2028 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2029 /* Disable HiZ Setting 2 */
2030 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2031 priv->state = STATE_ACTIVE_TC;
2032 return 0;
2033}
2034
2035static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
2036 u32 bandwidth)
2037{
2038 u8 data[2] = { 0x09, 0x54 };
2039
2040 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2041 cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
2042 /* Set SLV-X Bank : 0x00 */
2043 cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2044 /* Set demod mode */
2045 cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
2046 /* Set SLV-T Bank : 0x00 */
2047 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2048 /* Enable demod clock */
2049 cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2050 /* Disable RF level monitor */
2051 cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2052 /* Enable ADC clock */
2053 cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2054 /* Enable ADC 1 */
2055 cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2056 /* xtal freq 20.5MHz */
2057 cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2058 /* Enable ADC 4 */
2059 cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2060 /* Set SLV-T Bank : 0x10 */
2061 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2062 /* IFAGC gain settings */
2063 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
2064 /* Set SLV-T Bank : 0x11 */
2065 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2066 /* BBAGC TARGET level setting */
2067 cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
2068 /* Set SLV-T Bank : 0x10 */
2069 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2070 /* ASCOT setting ON */
2071 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2072 /* Set SLV-T Bank : 0x40 */
2073 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2074 /* Demod setting */
2075 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
2076 /* Set SLV-T Bank : 0x00 */
2077 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2078 /* TSIF setting */
2079 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2080 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2081
2082 cxd2841er_sleep_tc_to_active_c_band(priv, 8000000);
2083 /* Set SLV-T Bank : 0x00 */
2084 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2085 /* Disable HiZ Setting 1 */
2086 cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2087 /* Disable HiZ Setting 2 */
2088 cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2089 priv->state = STATE_ACTIVE_TC;
2090 return 0;
2091}
2092
Mauro Carvalho Chehab7e3e68b2016-02-04 12:58:30 -0200[diff] [blame^]2093static int cxd2841er_get_frontend(struct dvb_frontend *fe,
2094 struct dtv_frontend_properties *p)
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2095{
2096 enum fe_status status = 0;
2097 u16 strength = 0, snr = 0;
2098 u32 errors = 0, ber = 0;
2099 struct cxd2841er_priv *priv = fe->demodulator_priv;
Kozlov Sergeya6dc60ff2015-07-28 11:33:03 -0300[diff] [blame]2100
2101 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2102 if (priv->state == STATE_ACTIVE_S)
2103 cxd2841er_read_status_s(fe, &status);
2104 else if (priv->state == STATE_ACTIVE_TC)
2105 cxd2841er_read_status_tc(fe, &status);
2106
2107 if (status & FE_HAS_LOCK) {
2108 cxd2841er_read_signal_strength(fe, &strength);
2109 p->strength.len = 1;
2110 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
2111 p->strength.stat[0].uvalue = strength;
2112 cxd2841er_read_snr(fe, &snr);
2113 p->cnr.len = 1;
2114 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2115 p->cnr.stat[0].svalue = snr;
2116 cxd2841er_read_ucblocks(fe, &errors);
2117 p->block_error.len = 1;
2118 p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2119 p->block_error.stat[0].uvalue = errors;
2120 cxd2841er_read_ber(fe, &ber);
2121 p->post_bit_error.len = 1;
2122 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
2123 p->post_bit_error.stat[0].uvalue = ber;
2124 } else {
2125 p->strength.len = 1;
2126 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2127 p->cnr.len = 1;
2128 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2129 p->block_error.len = 1;
2130 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2131 p->post_bit_error.len = 1;
2132 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2133 }
2134 return 0;
2135}
2136
2137static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
2138{
2139 int ret = 0, i, timeout, carr_offset;
2140 enum fe_status status;
2141 struct cxd2841er_priv *priv = fe->demodulator_priv;
2142 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2143 u32 symbol_rate = p->symbol_rate/1000;
2144
2145 dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d\n",
2146 __func__,
2147 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
2148 p->frequency, symbol_rate);
2149 switch (priv->state) {
2150 case STATE_SLEEP_S:
2151 ret = cxd2841er_sleep_s_to_active_s(
2152 priv, p->delivery_system, symbol_rate);
2153 break;
2154 case STATE_ACTIVE_S:
2155 ret = cxd2841er_retune_active(priv, p);
2156 break;
2157 default:
2158 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2159 __func__, priv->state);
2160 ret = -EINVAL;
2161 goto done;
2162 }
2163 if (ret) {
2164 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
2165 goto done;
2166 }
2167 if (fe->ops.i2c_gate_ctrl)
2168 fe->ops.i2c_gate_ctrl(fe, 1);
2169 if (fe->ops.tuner_ops.set_params)
2170 fe->ops.tuner_ops.set_params(fe);
2171 if (fe->ops.i2c_gate_ctrl)
2172 fe->ops.i2c_gate_ctrl(fe, 0);
2173 cxd2841er_tune_done(priv);
2174 timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
2175 for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
2176 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
2177 (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
2178 cxd2841er_read_status_s(fe, &status);
2179 if (status & FE_HAS_LOCK)
2180 break;
2181 }
2182 if (status & FE_HAS_LOCK) {
2183 if (cxd2841er_get_carrier_offset_s_s2(
2184 priv, &carr_offset)) {
2185 ret = -EINVAL;
2186 goto done;
2187 }
2188 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
2189 __func__, carr_offset);
2190 }
2191done:
2192 return ret;
2193}
2194
2195static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
2196{
2197 int ret = 0, timeout;
2198 enum fe_status status;
2199 struct cxd2841er_priv *priv = fe->demodulator_priv;
2200 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2201
2202 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2203 if (p->delivery_system == SYS_DVBT) {
2204 priv->system = SYS_DVBT;
2205 switch (priv->state) {
2206 case STATE_SLEEP_TC:
2207 ret = cxd2841er_sleep_tc_to_active_t(
2208 priv, p->bandwidth_hz);
2209 break;
2210 case STATE_ACTIVE_TC:
2211 ret = cxd2841er_retune_active(priv, p);
2212 break;
2213 default:
2214 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2215 __func__, priv->state);
2216 ret = -EINVAL;
2217 }
2218 } else if (p->delivery_system == SYS_DVBT2) {
2219 priv->system = SYS_DVBT2;
2220 cxd2841er_dvbt2_set_plp_config(priv,
2221 (int)(p->stream_id > 255), p->stream_id);
2222 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
2223 switch (priv->state) {
2224 case STATE_SLEEP_TC:
2225 ret = cxd2841er_sleep_tc_to_active_t2(priv,
2226 p->bandwidth_hz);
2227 break;
2228 case STATE_ACTIVE_TC:
2229 ret = cxd2841er_retune_active(priv, p);
2230 break;
2231 default:
2232 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2233 __func__, priv->state);
2234 ret = -EINVAL;
2235 }
2236 } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
2237 p->delivery_system == SYS_DVBC_ANNEX_C) {
2238 priv->system = SYS_DVBC_ANNEX_A;
2239 switch (priv->state) {
2240 case STATE_SLEEP_TC:
2241 ret = cxd2841er_sleep_tc_to_active_c(
2242 priv, p->bandwidth_hz);
2243 break;
2244 case STATE_ACTIVE_TC:
2245 ret = cxd2841er_retune_active(priv, p);
2246 break;
2247 default:
2248 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
2249 __func__, priv->state);
2250 ret = -EINVAL;
2251 }
2252 } else {
2253 dev_dbg(&priv->i2c->dev,
2254 "%s(): invalid delivery system %d\n",
2255 __func__, p->delivery_system);
2256 ret = -EINVAL;
2257 }
2258 if (ret)
2259 goto done;
2260 if (fe->ops.i2c_gate_ctrl)
2261 fe->ops.i2c_gate_ctrl(fe, 1);
2262 if (fe->ops.tuner_ops.set_params)
2263 fe->ops.tuner_ops.set_params(fe);
2264 if (fe->ops.i2c_gate_ctrl)
2265 fe->ops.i2c_gate_ctrl(fe, 0);
2266 cxd2841er_tune_done(priv);
2267 timeout = 2500;
2268 while (timeout > 0) {
2269 ret = cxd2841er_read_status_tc(fe, &status);
2270 if (ret)
2271 goto done;
2272 if (status & FE_HAS_LOCK)
2273 break;
2274 msleep(20);
2275 timeout -= 20;
2276 }
2277 if (timeout < 0)
2278 dev_dbg(&priv->i2c->dev,
2279 "%s(): LOCK wait timeout\n", __func__);
2280done:
2281 return ret;
2282}
2283
2284static int cxd2841er_tune_s(struct dvb_frontend *fe,
2285 bool re_tune,
2286 unsigned int mode_flags,
2287 unsigned int *delay,
2288 enum fe_status *status)
2289{
2290 int ret, carrier_offset;
2291 struct cxd2841er_priv *priv = fe->demodulator_priv;
2292 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2293
2294 dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
2295 if (re_tune) {
2296 ret = cxd2841er_set_frontend_s(fe);
2297 if (ret)
2298 return ret;
2299 cxd2841er_read_status_s(fe, status);
2300 if (*status & FE_HAS_LOCK) {
2301 if (cxd2841er_get_carrier_offset_s_s2(
2302 priv, &carrier_offset))
2303 return -EINVAL;
2304 p->frequency += carrier_offset;
2305 ret = cxd2841er_set_frontend_s(fe);
2306 if (ret)
2307 return ret;
2308 }
2309 }
2310 *delay = HZ / 5;
2311 return cxd2841er_read_status_s(fe, status);
2312}
2313
2314static int cxd2841er_tune_tc(struct dvb_frontend *fe,
2315 bool re_tune,
2316 unsigned int mode_flags,
2317 unsigned int *delay,
2318 enum fe_status *status)
2319{
2320 int ret, carrier_offset;
2321 struct cxd2841er_priv *priv = fe->demodulator_priv;
2322 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2323
2324 dev_dbg(&priv->i2c->dev, "%s(): re_tune %d\n", __func__, re_tune);
2325 if (re_tune) {
2326 ret = cxd2841er_set_frontend_tc(fe);
2327 if (ret)
2328 return ret;
2329 cxd2841er_read_status_tc(fe, status);
2330 if (*status & FE_HAS_LOCK) {
2331 switch (priv->system) {
2332 case SYS_DVBT:
2333 case SYS_DVBT2:
2334 ret = cxd2841er_get_carrier_offset_t2(
2335 priv, p->bandwidth_hz,
2336 &carrier_offset);
2337 break;
2338 case SYS_DVBC_ANNEX_A:
2339 ret = cxd2841er_get_carrier_offset_c(
2340 priv, &carrier_offset);
2341 break;
2342 default:
2343 dev_dbg(&priv->i2c->dev,
2344 "%s(): invalid delivery system %d\n",
2345 __func__, priv->system);
2346 return -EINVAL;
2347 }
2348 if (ret)
2349 return ret;
2350 dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
2351 __func__, carrier_offset);
2352 p->frequency += carrier_offset;
2353 ret = cxd2841er_set_frontend_tc(fe);
2354 if (ret)
2355 return ret;
2356 }
2357 }
2358 *delay = HZ / 5;
2359 return cxd2841er_read_status_tc(fe, status);
2360}
2361
2362static int cxd2841er_sleep_s(struct dvb_frontend *fe)
2363{
2364 struct cxd2841er_priv *priv = fe->demodulator_priv;
2365
2366 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2367 cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
2368 cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
2369 return 0;
2370}
2371
2372static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
2373{
2374 struct cxd2841er_priv *priv = fe->demodulator_priv;
2375
2376 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2377 if (priv->state == STATE_ACTIVE_TC) {
2378 switch (priv->system) {
2379 case SYS_DVBT:
2380 cxd2841er_active_t_to_sleep_tc(priv);
2381 break;
2382 case SYS_DVBT2:
2383 cxd2841er_active_t2_to_sleep_tc(priv);
2384 break;
2385 case SYS_DVBC_ANNEX_A:
2386 cxd2841er_active_c_to_sleep_tc(priv);
2387 break;
2388 default:
2389 dev_warn(&priv->i2c->dev,
2390 "%s(): unknown delivery system %d\n",
2391 __func__, priv->system);
2392 }
2393 }
2394 if (priv->state != STATE_SLEEP_TC) {
2395 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
2396 __func__, priv->state);
2397 return -EINVAL;
2398 }
2399 cxd2841er_sleep_tc_to_shutdown(priv);
2400 return 0;
2401}
2402
2403static int cxd2841er_send_burst(struct dvb_frontend *fe,
2404 enum fe_sec_mini_cmd burst)
2405{
2406 u8 data;
2407 struct cxd2841er_priv *priv = fe->demodulator_priv;
2408
2409 dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
2410 (burst == SEC_MINI_A ? "A" : "B"));
2411 if (priv->state != STATE_SLEEP_S &&
2412 priv->state != STATE_ACTIVE_S) {
2413 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2414 __func__, priv->state);
2415 return -EINVAL;
2416 }
2417 data = (burst == SEC_MINI_A ? 0 : 1);
2418 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2419 cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
2420 cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
2421 return 0;
2422}
2423
2424static int cxd2841er_set_tone(struct dvb_frontend *fe,
2425 enum fe_sec_tone_mode tone)
2426{
2427 u8 data;
2428 struct cxd2841er_priv *priv = fe->demodulator_priv;
2429
2430 dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
2431 (tone == SEC_TONE_ON ? "On" : "Off"));
2432 if (priv->state != STATE_SLEEP_S &&
2433 priv->state != STATE_ACTIVE_S) {
2434 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2435 __func__, priv->state);
2436 return -EINVAL;
2437 }
2438 data = (tone == SEC_TONE_ON ? 1 : 0);
2439 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2440 cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
2441 return 0;
2442}
2443
2444static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
2445 struct dvb_diseqc_master_cmd *cmd)
2446{
2447 int i;
2448 u8 data[12];
2449 struct cxd2841er_priv *priv = fe->demodulator_priv;
2450
2451 if (priv->state != STATE_SLEEP_S &&
2452 priv->state != STATE_ACTIVE_S) {
2453 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
2454 __func__, priv->state);
2455 return -EINVAL;
2456 }
2457 dev_dbg(&priv->i2c->dev,
2458 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
2459 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
2460 /* DiDEqC enable */
2461 cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
2462 /* cmd1 length & data */
2463 cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
2464 memset(data, 0, sizeof(data));
2465 for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
2466 data[i] = cmd->msg[i];
2467 cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
2468 /* repeat count for cmd1 */
2469 cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
2470 /* repeat count for cmd2: always 0 */
2471 cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
2472 /* start transmit */
2473 cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
2474 /* wait for 1 sec timeout */
2475 for (i = 0; i < 50; i++) {
2476 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
2477 if (!data[0]) {
2478 dev_dbg(&priv->i2c->dev,
2479 "%s(): DiSEqC cmd has been sent\n", __func__);
2480 return 0;
2481 }
2482 msleep(20);
2483 }
2484 dev_dbg(&priv->i2c->dev,
2485 "%s(): DiSEqC cmd transmit timeout\n", __func__);
2486 return -ETIMEDOUT;
2487}
2488
2489static void cxd2841er_release(struct dvb_frontend *fe)
2490{
2491 struct cxd2841er_priv *priv = fe->demodulator_priv;
2492
2493 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2494 kfree(priv);
2495}
2496
2497static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2498{
2499 struct cxd2841er_priv *priv = fe->demodulator_priv;
2500
2501 dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
2502 cxd2841er_set_reg_bits(
2503 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
2504 return 0;
2505}
2506
2507static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
2508{
2509 struct cxd2841er_priv *priv = fe->demodulator_priv;
2510
2511 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2512 return DVBFE_ALGO_HW;
2513}
2514
2515static int cxd2841er_init_s(struct dvb_frontend *fe)
2516{
2517 struct cxd2841er_priv *priv = fe->demodulator_priv;
2518
2519 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2520 cxd2841er_shutdown_to_sleep_s(priv);
2521 /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
2522 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
2523 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
2524 return 0;
2525}
2526
2527static int cxd2841er_init_tc(struct dvb_frontend *fe)
2528{
2529 struct cxd2841er_priv *priv = fe->demodulator_priv;
2530
2531 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2532 cxd2841er_shutdown_to_sleep_tc(priv);
2533 /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
2534 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2535 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
2536 /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
2537 cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
2538 /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
2539 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2540 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
2541 return 0;
2542}
2543
2544static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
2545static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops;
2546static struct dvb_frontend_ops cxd2841er_dvbc_ops;
2547
2548static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
2549 struct i2c_adapter *i2c,
2550 u8 system)
2551{
2552 u8 chip_id = 0;
2553 const char *type;
2554 struct cxd2841er_priv *priv = NULL;
2555
2556 /* allocate memory for the internal state */
2557 priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
2558 if (!priv)
2559 return NULL;
2560 priv->i2c = i2c;
2561 priv->config = cfg;
2562 priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
2563 priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
2564 /* create dvb_frontend */
2565 switch (system) {
2566 case SYS_DVBS:
2567 memcpy(&priv->frontend.ops,
2568 &cxd2841er_dvbs_s2_ops,
2569 sizeof(struct dvb_frontend_ops));
2570 type = "S/S2";
2571 break;
2572 case SYS_DVBT:
2573 memcpy(&priv->frontend.ops,
2574 &cxd2841er_dvbt_t2_ops,
2575 sizeof(struct dvb_frontend_ops));
2576 type = "T/T2";
2577 break;
2578 case SYS_DVBC_ANNEX_A:
2579 memcpy(&priv->frontend.ops,
2580 &cxd2841er_dvbc_ops,
2581 sizeof(struct dvb_frontend_ops));
2582 type = "C/C2";
2583 break;
2584 default:
2585 kfree(priv);
2586 return NULL;
2587 }
2588 priv->frontend.demodulator_priv = priv;
2589 dev_info(&priv->i2c->dev,
2590 "%s(): attaching CXD2841ER DVB-%s frontend\n",
2591 __func__, type);
2592 dev_info(&priv->i2c->dev,
2593 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
2594 __func__, priv->i2c,
2595 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
2596 chip_id = cxd2841er_chip_id(priv);
2597 if (chip_id != CXD2841ER_CHIP_ID) {
2598 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
2599 __func__, chip_id);
2600 priv->frontend.demodulator_priv = NULL;
2601 kfree(priv);
2602 return NULL;
2603 }
2604 dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
2605 __func__, chip_id);
2606 return &priv->frontend;
2607}
2608
2609struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
2610 struct i2c_adapter *i2c)
2611{
2612 return cxd2841er_attach(cfg, i2c, SYS_DVBS);
2613}
2614EXPORT_SYMBOL(cxd2841er_attach_s);
2615
2616struct dvb_frontend *cxd2841er_attach_t(struct cxd2841er_config *cfg,
2617 struct i2c_adapter *i2c)
2618{
2619 return cxd2841er_attach(cfg, i2c, SYS_DVBT);
2620}
2621EXPORT_SYMBOL(cxd2841er_attach_t);
2622
2623struct dvb_frontend *cxd2841er_attach_c(struct cxd2841er_config *cfg,
2624 struct i2c_adapter *i2c)
2625{
2626 return cxd2841er_attach(cfg, i2c, SYS_DVBC_ANNEX_A);
2627}
2628EXPORT_SYMBOL(cxd2841er_attach_c);
2629
2630static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
2631 .delsys = { SYS_DVBS, SYS_DVBS2 },
2632 .info = {
2633 .name = "Sony CXD2841ER DVB-S/S2 demodulator",
2634 .frequency_min = 500000,
2635 .frequency_max = 2500000,
2636 .frequency_stepsize = 0,
2637 .symbol_rate_min = 1000000,
2638 .symbol_rate_max = 45000000,
2639 .symbol_rate_tolerance = 500,
2640 .caps = FE_CAN_INVERSION_AUTO |
2641 FE_CAN_FEC_AUTO |
2642 FE_CAN_QPSK,
2643 },
2644 .init = cxd2841er_init_s,
2645 .sleep = cxd2841er_sleep_s,
2646 .release = cxd2841er_release,
2647 .set_frontend = cxd2841er_set_frontend_s,
2648 .get_frontend = cxd2841er_get_frontend,
2649 .read_status = cxd2841er_read_status_s,
2650 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2651 .get_frontend_algo = cxd2841er_get_algo,
2652 .set_tone = cxd2841er_set_tone,
2653 .diseqc_send_burst = cxd2841er_send_burst,
2654 .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
2655 .tune = cxd2841er_tune_s
2656};
2657
2658static struct dvb_frontend_ops cxd2841er_dvbt_t2_ops = {
2659 .delsys = { SYS_DVBT, SYS_DVBT2 },
2660 .info = {
2661 .name = "Sony CXD2841ER DVB-T/T2 demodulator",
2662 .caps = FE_CAN_FEC_1_2 |
2663 FE_CAN_FEC_2_3 |
2664 FE_CAN_FEC_3_4 |
2665 FE_CAN_FEC_5_6 |
2666 FE_CAN_FEC_7_8 |
2667 FE_CAN_FEC_AUTO |
2668 FE_CAN_QPSK |
2669 FE_CAN_QAM_16 |
2670 FE_CAN_QAM_32 |
2671 FE_CAN_QAM_64 |
2672 FE_CAN_QAM_128 |
2673 FE_CAN_QAM_256 |
2674 FE_CAN_QAM_AUTO |
2675 FE_CAN_TRANSMISSION_MODE_AUTO |
2676 FE_CAN_GUARD_INTERVAL_AUTO |
2677 FE_CAN_HIERARCHY_AUTO |
2678 FE_CAN_MUTE_TS |
2679 FE_CAN_2G_MODULATION,
2680 .frequency_min = 42000000,
2681 .frequency_max = 1002000000
2682 },
2683 .init = cxd2841er_init_tc,
2684 .sleep = cxd2841er_sleep_tc,
2685 .release = cxd2841er_release,
2686 .set_frontend = cxd2841er_set_frontend_tc,
2687 .get_frontend = cxd2841er_get_frontend,
2688 .read_status = cxd2841er_read_status_tc,
2689 .tune = cxd2841er_tune_tc,
2690 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2691 .get_frontend_algo = cxd2841er_get_algo
2692};
2693
2694static struct dvb_frontend_ops cxd2841er_dvbc_ops = {
2695 .delsys = { SYS_DVBC_ANNEX_A },
2696 .info = {
2697 .name = "Sony CXD2841ER DVB-C demodulator",
2698 .caps = FE_CAN_FEC_1_2 |
2699 FE_CAN_FEC_2_3 |
2700 FE_CAN_FEC_3_4 |
2701 FE_CAN_FEC_5_6 |
2702 FE_CAN_FEC_7_8 |
2703 FE_CAN_FEC_AUTO |
2704 FE_CAN_QAM_16 |
2705 FE_CAN_QAM_32 |
2706 FE_CAN_QAM_64 |
2707 FE_CAN_QAM_128 |
2708 FE_CAN_QAM_256 |
2709 FE_CAN_QAM_AUTO |
2710 FE_CAN_INVERSION_AUTO,
2711 .frequency_min = 42000000,
2712 .frequency_max = 1002000000
2713 },
2714 .init = cxd2841er_init_tc,
2715 .sleep = cxd2841er_sleep_tc,
2716 .release = cxd2841er_release,
2717 .set_frontend = cxd2841er_set_frontend_tc,
2718 .get_frontend = cxd2841er_get_frontend,
2719 .read_status = cxd2841er_read_status_tc,
2720 .tune = cxd2841er_tune_tc,
2721 .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
2722 .get_frontend_algo = cxd2841er_get_algo,
2723};
2724
2725MODULE_DESCRIPTION("Sony CXD2841ER DVB-C/C2/T/T2/S/S2 demodulator driver");
2726MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
2727MODULE_LICENSE("GPL");