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Jeff Kirsherae06c702018-03-22 10:08:48 -07001/* SPDX-License-Identifier: GPL-2.0 */
Yi Zoue92cbea2009-05-13 13:10:01 +00002/*******************************************************************************
3
4 Intel 10 Gigabit PCI Express Linux driver
Don Skidmore434c5e32013-01-08 05:02:28 +00005 Copyright(c) 1999 - 2013 Intel Corporation.
Yi Zoue92cbea2009-05-13 13:10:01 +00006
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Contact Information:
Jacob Kellerb89aae72014-02-22 01:23:50 +000024 Linux NICS <linux.nics@intel.com>
Yi Zoue92cbea2009-05-13 13:10:01 +000025 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30#ifndef _IXGBE_FCOE_H
31#define _IXGBE_FCOE_H
32
Yi Zou3d8fd382009-06-08 14:38:44 +000033#include <scsi/fc/fc_fs.h>
Yi Zoue92cbea2009-05-13 13:10:01 +000034#include <scsi/fc/fc_fcoe.h>
35
36/* shift bits within STAT fo FCSTAT */
37#define IXGBE_RXDADV_FCSTAT_SHIFT 4
38
39/* ddp user buffer */
40#define IXGBE_BUFFCNT_MAX 256 /* 8 bits bufcnt */
41#define IXGBE_FCPTR_ALIGN 16
42#define IXGBE_FCPTR_MAX (IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
43#define IXGBE_FCBUFF_4KB 0x0
44#define IXGBE_FCBUFF_8KB 0x1
45#define IXGBE_FCBUFF_16KB 0x2
46#define IXGBE_FCBUFF_64KB 0x3
47#define IXGBE_FCBUFF_MAX 65536 /* 64KB max */
48#define IXGBE_FCBUFF_MIN 4096 /* 4KB min */
49#define IXGBE_FCOE_DDP_MAX 512 /* 9 bits xid */
Vasu Devea412012015-04-09 22:03:23 -070050#define IXGBE_FCOE_DDP_MAX_X550 2048 /* 11 bits xid */
Yi Zoue92cbea2009-05-13 13:10:01 +000051
Yi Zou6ee16522009-08-31 12:34:28 +000052/* Default traffic class to use for FCoE */
53#define IXGBE_FCOE_DEFTC 3
54
Yi Zoue92cbea2009-05-13 13:10:01 +000055/* fcerr */
56#define IXGBE_FCERR_BADCRC 0x00100000
57
Yi Zou68a683c2011-02-01 07:22:16 +000058/* FCoE DDP for target mode */
59#define __IXGBE_FCOE_TARGET 1
60
Yi Zoue92cbea2009-05-13 13:10:01 +000061struct ixgbe_fcoe_ddp {
62 int len;
63 u32 err;
64 unsigned int sgc;
65 struct scatterlist *sgl;
66 dma_addr_t udp;
Yi Zoud0ed8932009-05-13 13:11:29 +000067 u64 *udl;
Alexander Duyck1bf91cd2012-05-05 05:32:32 +000068 struct dma_pool *pool;
Yi Zoue92cbea2009-05-13 13:10:01 +000069};
70
Alexander Duyck5a1ee272012-05-05 17:14:28 +000071/* per cpu variables */
72struct ixgbe_fcoe_ddp_pool {
73 struct dma_pool *pool;
74 u64 noddp;
75 u64 noddp_ext_buff;
76};
77
Yi Zoue92cbea2009-05-13 13:10:01 +000078struct ixgbe_fcoe {
Alexander Duyck5a1ee272012-05-05 17:14:28 +000079 struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool;
Vasu Devdadbe852011-05-11 05:41:46 +000080 atomic_t refcnt;
81 spinlock_t lock;
Vasu Devea412012015-04-09 22:03:23 -070082 struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550];
Alexander Duyck7c8ae652012-05-05 05:32:47 +000083 void *extra_ddp_buffer;
Vasu Devdadbe852011-05-11 05:41:46 +000084 dma_addr_t extra_ddp_buffer_dma;
85 unsigned long mode;
Yi Zou61a0f422009-12-03 11:32:22 +000086 u8 up;
Yi Zoue92cbea2009-05-13 13:10:01 +000087};
88
89#endif /* _IXGBE_FCOE_H */